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Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6/233BCZ","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6/233BCZ","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 1998","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 5, 1998","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Mobile K6","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":233.33,"unit":"MHz","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Little Foot","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":68,"unit":"mm²","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1013-r2864","location":"Amd/k6/amd-k6/233bcz · revision 2864 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233bcz&oldid=2864","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-360","unit":"","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":360,"unit":"","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.78,"unit":"mm","sourceId":"chipswiki-31128-r91600","location":"Template:Packages/amd/CBGA-360 · revision 91600 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-25. Not an independent measurement.","entityId":"cw-284f7ed06770bd24","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FCBGA-360&oldid=91600","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1013-r2864","chipswiki-31128-r91600"],"url":"https://museum.vlsi.kr/objects/cw-284f7ed06770bd24"},{"id":"cw-285906878d4f7c91","name":"K6-2/266AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1998,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-266afr"],"fields":[{"key":"Model name","value":"K6-2/266AFR","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/266AFR","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/266AFR","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 4, 1998","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266.66,"unit":"MHz","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8386-r26081","location":"Amd/k6-2/k6-2-266afr · revision 26081 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-285906878d4f7c91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266afr&oldid=26081","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8386-r26081"],"url":"https://museum.vlsi.kr/objects/cw-285906878d4f7c91"},{"id":"cw-2877919ded0b4098","name":"Embedded G-Series T56E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"G-Series APU/CPU","year":2012,"architecture":"Bobcat","process":"40 nm","aliases":["Amd embedded t56e"],"fields":[{"key":"Model name","value":"Embedded G-Series T56E","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"T56E","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GET56EGBB22GVE","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Embedded G-Series","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G-Series APU/CPU","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1650,"unit":"MHz","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1815,"unit":"MHz","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bobcat","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"eBrazos","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":20,"unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":451000000,"unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":75,"unit":"mm²","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2 × 512 KiB","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"10.67 GB/s","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon HD 6250","unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":275,"unit":"MHz","sourceId":"chipswiki-415-r887","location":"Amd/embedded/t56e · revision 887 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FT1","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":413,"unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.8-1.0 mm","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.92,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-2877919ded0b4098","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-415-r887","chipswiki-31122-r91589"],"url":"https://museum.vlsi.kr/objects/cw-2877919ded0b4098"},{"id":"cw-28aa785f42a44db4","name":"Xeon Gold 6230","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6230"],"fields":[{"key":"Model name","value":"Xeon Gold 6230","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6230,"unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504193701","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806956230","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF8W","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-01-19. 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Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. 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Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. 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Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. 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Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":27.5,"unit":"MiB","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x1.375 MiB","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. 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Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-535-r1094","location":"Intel/xeon gold/6230 · revision 1094 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-19. Not an independent measurement.","entityId":"cw-28aa785f42a44db4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6230&oldid=1094","sourceDate":"2022-01-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-535-r1094"],"url":"https://museum.vlsi.kr/objects/cw-28aa785f42a44db4"},{"id":"cw-28e50912f34b1760","name":"Core i7-2627M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2627m"],"fields":[{"key":"Model name","value":"Core i7-2627M","unit":"","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2627M","unit":"","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701121700","unit":"","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701121701","unit":"","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2011,"unit":"","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2627m&oldid=25401","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7897-r25401","location":"Intel/core i7/i7-2627m · revision 25401 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-28e50912f34b1760","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7897-r25401","chipswiki-31339-r92076","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-28e50912f34b1760"},{"id":"cw-2902bf26de3ed9d0","name":"AM9080A-2DCB","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-2dcb"],"fields":[{"key":"Model name","value":"AMD AM9080A-2DCB","unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-2DCB","unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-2DCB","unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.632,"unit":"MHz","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8481-r26674","location":"Amd/am9080/am9080a-2dcb · revision 26674 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2902bf26de3ed9d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dcb&oldid=26674","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8481-r26674"],"url":"https://museum.vlsi.kr/objects/cw-2902bf26de3ed9d0"},{"id":"cw-2912bf76b87eb455","name":"Celeron N3350","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N Series","year":2016,"architecture":"Goldmont","process":"14 nm","aliases":["Intel celeron n3350"],"fields":[{"key":"Model name","value":"Celeron N3350","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N3350","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066802980002","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066802980002","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N Series","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2YB","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2Z7","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Apollo Lake","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-1296","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1296","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8027-r25610","location":"Intel/celeron/n3350 · revision 25610 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2912bf76b87eb455","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8027-r25610"],"url":"https://museum.vlsi.kr/objects/cw-2912bf76b87eb455"},{"id":"cw-29171d90a644bcfe","name":"EPYC 7713P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7713p"],"fields":[{"key":"Model name","value":"EPYC 7713P","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7713P","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000337","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000337WOF","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3675,"unit":"MHz","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":64,"unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":128,"unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":225,"unit":"W","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"MiB","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64 × 32 KiB","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"MiB","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64 × 32 KiB","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"64 × 512 KiB","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 32 MiB","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-750-r1792","location":"Amd/epyc/7713p · revision 1792 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-29171d90a644bcfe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713p&oldid=1792","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-750-r1792"],"url":"https://museum.vlsi.kr/objects/cw-29171d90a644bcfe"},{"id":"cw-294749cb411e45f0","name":"Alchemy Au1500-333MBC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2001,"architecture":"Au1","process":"180 nm","aliases":["Alchemy au1500-333mbc"],"fields":[{"key":"Model name","value":"Alchemy Au1500-333MBC","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1500-333MBC","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1500-333MBC","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 11, 2001","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 2001","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AB","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AC","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AD","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.333 GB/s","unit":"","sourceId":"chipswiki-484-r968","location":"Alchemy/au1500-333mbc · revision 968 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-294749cb411e45f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-484-r968"],"url":"https://museum.vlsi.kr/objects/cw-294749cb411e45f0"},{"id":"cw-2948d75756a01382","name":"Core i5-8650","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-8650"],"fields":[{"key":"Model name","value":"Core i5-8650","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8650","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4963-r16057","location":"Intel/core i5/i5-8650 · revision 16057 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-2948d75756a01382","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650&oldid=16057","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4963-r16057"],"url":"https://museum.vlsi.kr/objects/cw-2948d75756a01382"},{"id":"cw-2968f2aef6b304e8","name":"Core i3-2350LM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2350lm"],"fields":[{"key":"Model name","value":"Core i3-2350LM","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2350LM","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701066002","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR03P","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October, 2011","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 2011","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-8009-r25590","location":"Intel/core i3/i3-2350lm · revision 25590 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350lm&oldid=25590","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2968f2aef6b304e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2133","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303533204","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3LL","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-2000","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x1 MiB","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8.25,"unit":"MiB","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.375 MiB","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-2531-r8691","location":"Intel/xeon w/w-2133 · revision 8691 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-2972341a9c4f59ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2531-r8691"],"url":"https://museum.vlsi.kr/objects/cw-2972341a9c4f59ba"},{"id":"cw-2974c4b61940b677","name":"Helio P70","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio P","year":2018,"architecture":"Cortex-A73","process":"12 nm","aliases":["Mediatek helio p70"],"fields":[{"key":"Model name","value":"Helio P70","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P70","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 24, 2018","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 24, 2018","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio P","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2100,"unit":"MHz","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A73","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A73","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3600","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.41,"unit":"GiB/s","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G72","unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":900,"unit":"MHz","sourceId":"chipswiki-219-r446","location":"Mediatek/helio/p70 · revision 446 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-23. Not an independent measurement.","entityId":"cw-2974c4b61940b677","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp70&oldid=446","sourceDate":"2022-08-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-219-r446"],"url":"https://museum.vlsi.kr/objects/cw-2974c4b61940b677"},{"id":"cw-2977f00b202a3e21","name":"Am186CC-25KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CC","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186cc-25ki\\w"],"fields":[{"key":"Model name","value":"Am186CC-25KI\\W","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CC-25KI\\W","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CC-25KI\\W","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CC","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14690-r44751","location":"Amd/am186cx/am186cc-25ki\\w · revision 44751 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2977f00b202a3e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14690-r44751"],"url":"https://museum.vlsi.kr/objects/cw-2977f00b202a3e21"},{"id":"cw-299bc37d93c139af","name":"Mobile Duron 600 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dm600avs1b"],"fields":[{"key":"Model name","value":"Duron 600","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 600","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DM600AVS1B","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 15, 2001","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 15, 2001","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.4,"unit":"V","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8407-r26115","location":"Amd/duron/dm600avs1b · revision 26115 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-299bc37d93c139af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8407-r26115"],"url":"https://museum.vlsi.kr/objects/cw-299bc37d93c139af"},{"id":"cw-29bc4b6f2df3e7ce","name":"Core i7-2960XM Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7ee i7-2960xm"],"fields":[{"key":"Model name","value":"Core i7-2960XM Extreme","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2960XM","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700834603","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR02F","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":55,"unit":"W","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"FCPGA988","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-5556-r17976","location":"Intel/core i7ee/i7-2960xm · revision 17976 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2960xm&oldid=17976","sourceDate":"2018-06-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-26. Not an independent measurement.","entityId":"cw-29bc4b6f2df3e7ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5556-r17976","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-29bc4b6f2df3e7ce"},{"id":"cw-29c476f8cd2d8bf8","name":"Pentium G4400T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel pentium (2009) g4400t"],"fields":[{"key":"Model name","value":"Pentium G4400T","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4400T","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201927506","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2HQ","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-7788-r25223","location":"Intel/pentium (2009)/g4400t · revision 25223 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29c476f8cd2d8bf8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400t&oldid=25223","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7788-r25223"],"url":"https://museum.vlsi.kr/objects/cw-29c476f8cd2d8bf8"},{"id":"cw-29d0268298ffbf95","name":"Xeon D-2177NT","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-2000","year":2018,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon d d-2177nt"],"fields":[{"key":"Model name","value":"Xeon D-2177NT","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2177NT","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8067303870800","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZY","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M1","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":14,"unit":"MiB","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x1 MiB","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-7148-r22565","location":"Intel/xeon d/d-2177nt · revision 22565 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2518,"unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":52.5,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-29d0268298ffbf95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7148-r22565","chipswiki-31304-r92006"],"url":"https://museum.vlsi.kr/objects/cw-29d0268298ffbf95"},{"id":"cw-29d1cfbb2344fb6d","name":"Duron 750 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2000,"architecture":"K7","process":"180 nm","aliases":["Amd duron d750aut1b"],"fields":[{"key":"Model name","value":"Duron 750","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 750","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D750AUT1B","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D0750AUT1B","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 5, 2000","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 5, 2000","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":750,"unit":"MHz","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":33.4,"unit":"W","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-29d1cfbb2344fb6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8434-r26142","location":"Amd/duron/d750aut1b · revision 26142 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-29d855e1a896b73b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000-64&oldid=11677","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Phytium","unit":"","sourceId":"chipswiki-3761-r11677","location":"Phytium/feiteng/ft-2000-64 · revision 11677 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-29d855e1a896b73b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000-64&oldid=11677","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-3761-r11677","location":"Phytium/feiteng/ft-2000-64 · revision 11677 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-29d855e1a896b73b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000-64&oldid=11677","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"FT-2000/64","unit":"","sourceId":"chipswiki-3761-r11677","location":"Phytium/feiteng/ft-2000-64 · revision 11677 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-29d855e1a896b73b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000-64&oldid=11677","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3761-r11677","location":"Phytium/feiteng/ft-2000-64 · revision 11677 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-29d855e1a896b73b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000-64&oldid=11677","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2016,"unit":"","sourceId":"chipswiki-3761-r11677","location":"Phytium/feiteng/ft-2000-64 · revision 11677 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. 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Not an independent measurement.","entityId":"cw-29d855e1a896b73b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000-64&oldid=11677","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-3761-r11677","location":"Phytium/feiteng/ft-2000-64 · revision 11677 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. 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Not an independent measurement.","entityId":"cw-29d855e1a896b73b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000-64&oldid=11677","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-3761-r11677","location":"Phytium/feiteng/ft-2000-64 · revision 11677 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. 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Not an independent measurement.","entityId":"cw-29d855e1a896b73b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000-64&oldid=11677","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-3761-r11677","location":"Phytium/feiteng/ft-2000-64 · revision 11677 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-29d855e1a896b73b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000-64&oldid=11677","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3761-r11677","location":"Phytium/feiteng/ft-2000-64 · revision 11677 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-29d855e1a896b73b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000-64&oldid=11677","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":95.37,"unit":"GiB/s","sourceId":"chipswiki-3761-r11677","location":"Phytium/feiteng/ft-2000-64 · revision 11677 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-29d855e1a896b73b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-2000-64&oldid=11677","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3761-r11677"],"url":"https://museum.vlsi.kr/objects/cw-29d855e1a896b73b"},{"id":"cw-29e5ce198f39a6d7","name":"Cortex-A35","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2015,"aliases":["Arm holdings microarchitectures cortex-a35"],"fields":[{"key":"Architecture name","value":"Cortex-A35","unit":"","sourceId":"chipswiki-1829-r6162","location":"Arm holdings/microarchitectures/cortex-a35 · revision 6162 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-29e5ce198f39a6d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a35&oldid=6162","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-1829-r6162","location":"Arm holdings/microarchitectures/cortex-a35 · revision 6162 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-29e5ce198f39a6d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a35&oldid=6162","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1829-r6162","location":"Arm holdings/microarchitectures/cortex-a35 · revision 6162 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-29e5ce198f39a6d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a35&oldid=6162","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"November 10, 2015","unit":"","sourceId":"chipswiki-1829-r6162","location":"Arm holdings/microarchitectures/cortex-a35 · revision 6162 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-29e5ce198f39a6d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a35&oldid=6162","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1829-r6162","location":"Arm holdings/microarchitectures/cortex-a35 · revision 6162 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-29e5ce198f39a6d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a35&oldid=6162","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A5","unit":"","sourceId":"chipswiki-1829-r6162","location":"Arm holdings/microarchitectures/cortex-a35 · revision 6162 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-29e5ce198f39a6d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a35&oldid=6162","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A32","unit":"","sourceId":"chipswiki-1829-r6162","location":"Arm holdings/microarchitectures/cortex-a35 · revision 6162 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-29e5ce198f39a6d7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a35&oldid=6162","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A34","unit":"","sourceId":"chipswiki-1829-r6162","location":"Arm holdings/microarchitectures/cortex-a35 · revision 6162 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-29e5ce198f39a6d7","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a35&oldid=6162","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1829-r6162"],"url":"https://museum.vlsi.kr/objects/cw-29e5ce198f39a6d7"},{"id":"cw-2a126043bd10211f","name":"Athlon 3000G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen","process":"14 nm","aliases":["Amd athlon 3000g"],"fields":[{"key":"Model name","value":"Athlon 3000G","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3000G","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD3000C6M2OFH","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD3000C6FHBOX","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD3000C6FBBOX","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD3000C6FHMPK","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD3000C6M2OFB","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 7, 2019","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 20, 2019","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Dali","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","alternatives":[{"value":"128 GiB","sourceId":"chipswiki-187-r375","reason":"Amd/athlon/3000g · revision 375 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-187-r375","location":"Amd/athlon/3000g · revision 375 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-23. Not an independent measurement.","entityId":"cw-2a126043bd10211f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","sourceDate":"2022-09-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-187-r375"],"url":"https://museum.vlsi.kr/objects/cw-2a126043bd10211f"},{"id":"cw-2a665c15b017e648","name":"Celeron B860E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron b860e"],"fields":[{"key":"Model name","value":"Celeron B860E","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B860E","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701082400","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0BX","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-2a665c15b017e648","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6923-r21609","location":"Intel/celeron/b860e · revision 21609 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2123IT","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8067303784201","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZW","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DE","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M1","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":60,"unit":"W","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x1 MiB","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8.25,"unit":"MiB","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.375 MiB","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":71.53,"unit":"GiB/s","sourceId":"chipswiki-7157-r22592","location":"Intel/xeon d/d-2123it · revision 22592 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2518,"unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":52.5,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-2a6c72dd0524bf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7157-r22592","chipswiki-31304-r92006"],"url":"https://museum.vlsi.kr/objects/cw-2a6c72dd0524bf3e"},{"id":"cw-2a7f238a2c1029cb","name":"Celeron 857","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 857"],"fields":[{"key":"Model name","value":"Celeron 857","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":857,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701149001","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701022701","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0FL","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0V2","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2011","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2011","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6937-r21624","location":"Intel/celeron/857 · revision 21624 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2a7f238a2c1029cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6937-r21624","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-2a7f238a2c1029cb"},{"id":"cw-2a8c275a26ad73f2","name":"Athlon MP 1000","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd athlon mp ahx1000ams3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 1000","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 1000","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AHX1000AMS3C","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2001","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2001","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Palomino","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37500000,"unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":128,"unit":"mm²","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":46.1,"unit":"W","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8462-r26655","location":"Amd/athlon mp/ahx1000ams3c · revision 26655 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2a8c275a26ad73f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Fahx1000ams3c&oldid=26655","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8462-r26655"],"url":"https://museum.vlsi.kr/objects/cw-2a8c275a26ad73f2"},{"id":"cw-2a944d89d0b76c06","name":"ARM11","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2002,"aliases":["Arm holdings microarchitectures arm11"],"fields":[{"key":"Architecture name","value":"ARM11","unit":"","sourceId":"chipswiki-4152-r13229","location":"Arm holdings/microarchitectures/arm11 · revision 13229 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-2a944d89d0b76c06","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm11&oldid=13229","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-4152-r13229","location":"Arm holdings/microarchitectures/arm11 · revision 13229 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-2a944d89d0b76c06","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm11&oldid=13229","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4152-r13229","location":"Arm holdings/microarchitectures/arm11 · revision 13229 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-2a944d89d0b76c06","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm11&oldid=13229","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"April 29, 2002","unit":"","sourceId":"chipswiki-4152-r13229","location":"Arm holdings/microarchitectures/arm11 · revision 13229 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-2a944d89d0b76c06","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm11&oldid=13229","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"ARM10","unit":"","sourceId":"chipswiki-4152-r13229","location":"Arm holdings/microarchitectures/arm11 · revision 13229 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-2a944d89d0b76c06","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm11&oldid=13229","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A8","unit":"","sourceId":"chipswiki-4152-r13229","location":"Arm holdings/microarchitectures/arm11 · revision 13229 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-31. Not an independent measurement.","entityId":"cw-2a944d89d0b76c06","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm11&oldid=13229","sourceDate":"2018-12-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4152-r13229"],"url":"https://museum.vlsi.kr/objects/cw-2a944d89d0b76c06"},{"id":"cw-2ac74fb20b641b32","name":"Ezra","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"VIA Technologies","year":null,"process":"0.13 µm","aliases":["Via technologies microarchitectures ezra"],"fields":[{"key":"Architecture name","value":"Ezra","unit":"","sourceId":"chipswiki-7380-r23866","location":"Via technologies/microarchitectures/ezra · revision 23866 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2ac74fb20b641b32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fezra&oldid=23866","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"VIA Technologies","unit":"","sourceId":"chipswiki-7380-r23866","location":"Via technologies/microarchitectures/ezra · revision 23866 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2ac74fb20b641b32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fezra&oldid=23866","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7380-r23866","location":"Via technologies/microarchitectures/ezra · revision 23866 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2ac74fb20b641b32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fezra&oldid=23866","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.13,"unit":"µm","sourceId":"chipswiki-7380-r23866","location":"Via technologies/microarchitectures/ezra · revision 23866 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2ac74fb20b641b32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fezra&oldid=23866","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-7380-r23866","location":"Via technologies/microarchitectures/ezra · revision 23866 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2ac74fb20b641b32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fezra&oldid=23866","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":12,"unit":"","sourceId":"chipswiki-7380-r23866","location":"Via technologies/microarchitectures/ezra · revision 23866 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2ac74fb20b641b32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fezra&oldid=23866","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-7380-r23866","location":"Via technologies/microarchitectures/ezra · revision 23866 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2ac74fb20b641b32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fezra&oldid=23866","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Samuel 2","unit":"","sourceId":"chipswiki-7380-r23866","location":"Via technologies/microarchitectures/ezra · revision 23866 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2ac74fb20b641b32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fezra&oldid=23866","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Nehemiah","unit":"","sourceId":"chipswiki-7380-r23866","location":"Via technologies/microarchitectures/ezra · revision 23866 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-15. Not an independent measurement.","entityId":"cw-2ac74fb20b641b32","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fezra&oldid=23866","sourceDate":"2018-01-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7380-r23866"],"url":"https://museum.vlsi.kr/objects/cw-2ac74fb20b641b32"},{"id":"cw-2b23704dbabadae6","name":"Core i5-6350HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6350hq"],"fields":[{"key":"Model name","value":"Core i5-6350HQ","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6350HQ","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2QZ","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"N0","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7925-r25464","location":"Intel/core i5/i5-6350hq · revision 25464 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6350hq&oldid=25464","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2b23704dbabadae6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 2600","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD260BBBM6IAF","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 6, 2018","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 6, 2018","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Pinnacle Ridge","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x64 KiB","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x8 MiB","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-4912-r15849","location":"Amd/ryzen 5/pro 2600 · revision 15849 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-2b72bbee9b22770b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4912-r15849","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-2b72bbee9b22770b"},{"id":"cw-2b901a82bcdc1086","name":"Am486DX4-100NV8T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX4V","year":1995,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx4-100nv8t"],"fields":[{"key":"Model name","value":"Am486DX4-100NV8T","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-100NV8T","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-100NV8T","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4V","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":100,"unit":"MHz","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4V","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8558-r26754","location":"Amd/am486/am486dx4-100nv8t · revision 26754 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2b901a82bcdc1086","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8558-r26754"],"url":"https://museum.vlsi.kr/objects/cw-2b901a82bcdc1086"},{"id":"cw-2b9348124837c40a","name":"Xeon Gold 6134M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6134m"],"fields":[{"key":"Model name","value":"Xeon Gold 6134M","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6134M","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303330402","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3AS","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. 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Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. 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Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. 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Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. 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Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. 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Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-2b9348124837c40a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6134m&oldid=8416","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-2474-r8416","location":"Intel/xeon gold/6134m · revision 8416 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. 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Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7100H","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR32T","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7100","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-6421-r20022","location":"Intel/core i3/i3-7100h · revision 20022 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-2b9559524004ed4e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6421-r20022","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-2b9559524004ed4e"},{"id":"cw-2ba35fe8e61f20f3","name":"CN3860-400 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3860-400bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3860-400 EXP","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3860-400 EXP","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3860-400BG1521-EXP","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x8 KiB","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8202-r25861","location":"Cavium/octeon/cn3860-400bg1521-exp · revision 25861 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-exp&oldid=25861","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ba35fe8e61f20f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8202-r25861","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-2ba35fe8e61f20f3"},{"id":"cw-2bd151c4ce57d3f6","name":"Pentium U5600","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P6000","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel pentium (2009) u5600"],"fields":[{"key":"Model name","value":"Intel Pentium U5600","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"U5600","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617005190AG","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 11, 2011","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 11, 2011","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P6000","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1333.33,"unit":"MHz","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBSM","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-7775-r25206","location":"Intel/pentium (2009)/u5600 · revision 25206 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fu5600&oldid=25206","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd151c4ce57d3f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2bd8224f6e028156","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd8224f6e028156","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2bd8224f6e028156","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8141-r25800","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-2bd8224f6e028156"},{"id":"cw-2be5f30cbee7efc8","name":"Celeron G3930","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"G3900","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel celeron g3930"],"fields":[{"key":"Model name","value":"Celeron G3930","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G3930","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80677G3930","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35K","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G3900","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80677G3930","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 610","unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-6434-r20119","location":"Intel/celeron/g3930 · revision 20119 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-2be5f30cbee7efc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6434-r20119"],"url":"https://museum.vlsi.kr/objects/cw-2be5f30cbee7efc8"},{"id":"cw-2c08c6b0b7028812","name":"MSM6245","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2006,"architecture":"ARM9","process":"65 nm","aliases":["Qualcomm msm6xxx msm6245"],"fields":[{"key":"Model name","value":"Qualcomm MSM6245","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6245","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 17, 2005","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 2006","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":180,"unit":"MHz","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1314-r4410","location":"Qualcomm/msm6xxx/msm6245 · revision 4410 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-05. Not an independent measurement.","entityId":"cw-2c08c6b0b7028812","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6245&oldid=4410","sourceDate":"2020-02-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1314-r4410"],"url":"https://museum.vlsi.kr/objects/cw-2c08c6b0b7028812"},{"id":"cw-2c771f5d65d567af","name":"Exynos 9611","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 9","year":2019,"architecture":"Cortex-A73","process":"10 nm finfet","aliases":["Samsung exynos 9611"],"fields":[{"key":"Model name","value":"Exynos 9611","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":9611,"unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 19, 2019","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 19, 2019","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 9","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2314,"unit":"MHz","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1742,"unit":"MHz","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A73","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A73","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"10 nm finfet","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3200","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G72","unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":850,"unit":"MHz","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1053,"unit":"MHz","sourceId":"chipswiki-92-r97051","location":"Samsung/exynos/9611 · revision 97051 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-03. Not an independent measurement.","entityId":"cw-2c771f5d65d567af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9611&oldid=97051","sourceDate":"2022-10-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-92-r97051"],"url":"https://museum.vlsi.kr/objects/cw-2c771f5d65d567af"},{"id":"cw-2c813a3179b24e43","name":"AM9080A-1PC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-1pc"],"fields":[{"key":"Model name","value":"AMD AM9080A-1PC","unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-1PC","unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-1PC","unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3.125,"unit":"MHz","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"DIP-40","unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"DIP","unit":"","sourceId":"chipswiki-8485-r26678","location":"Amd/am9080/am9080a-1pc · revision 26678 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2c813a3179b24e43","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pc&oldid=26678","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8485-r26678"],"url":"https://museum.vlsi.kr/objects/cw-2c813a3179b24e43"},{"id":"cw-2ca242676c9dc000","name":"Core i5-7210U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-7200","year":null,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-7210u"],"fields":[{"key":"Model name","value":"Core i5-7210U","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7210U","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR34G","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 2017","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7200","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2ca242676c9dc000","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7210u&oldid=25447","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7910-r25447","location":"Intel/core i5/i5-7210u · revision 25447 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-500 EXP","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3120-500BG868-EXP","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8244-r25904","location":"Cavium/octeon/cn3120-500bg868-exp · revision 25904 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-exp&oldid=25904","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2cfcdcf462129f8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8244-r25904","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-2cfcdcf462129f8e"},{"id":"cw-2d06e7a6cac48b11","name":"K6-2/200AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1998,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-200afr"],"fields":[{"key":"Model name","value":"K6-2/200AFR","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/200AFR","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/200AFR","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 4, 1998","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":200,"unit":"MHz","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-4124-r13094","location":"Amd/k6-2/k6-2-200afr · revision 13094 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-05. Not an independent measurement.","entityId":"cw-2d06e7a6cac48b11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","sourceDate":"2019-01-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4124-r13094"],"url":"https://museum.vlsi.kr/objects/cw-2d06e7a6cac48b11"},{"id":"cw-2d206b56afe896b2","name":"Athlon Gold 3150U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2020,"architecture":"Zen","process":"14 nm","aliases":["Amd athlon gold 3150u"],"fields":[{"key":"Model name","value":"Athlon Gold 3150U","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3150U","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM3150C4T2OFG","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon Gold","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Dali","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-1395-r4696","location":"Amd/athlon gold/3150u · revision 4696 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-08. Not an independent measurement.","entityId":"cw-2d206b56afe896b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","sourceDate":"2020-01-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1395-r4696"],"url":"https://museum.vlsi.kr/objects/cw-2d206b56afe896b2"},{"id":"cw-2d2a542e0691b872","name":"Helios","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":null,"process":"10 nm","aliases":["Arm holdings microarchitectures helios"],"fields":[{"key":"Architecture name","value":"Helios","unit":"","sourceId":"chipswiki-4179-r13364","location":"Arm holdings/microarchitectures/helios · revision 13364 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-2d2a542e0691b872","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhelios&oldid=13364","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-4179-r13364","location":"Arm holdings/microarchitectures/helios · revision 13364 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-2d2a542e0691b872","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhelios&oldid=13364","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4179-r13364","location":"Arm holdings/microarchitectures/helios · revision 13364 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-2d2a542e0691b872","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhelios&oldid=13364","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-4179-r13364","location":"Arm holdings/microarchitectures/helios · revision 13364 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-2d2a542e0691b872","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhelios&oldid=13364","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-4179-r13364","location":"Arm holdings/microarchitectures/helios · revision 13364 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-2d2a542e0691b872","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhelios&oldid=13364","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A55","unit":"","sourceId":"chipswiki-4179-r13364","location":"Arm holdings/microarchitectures/helios · revision 13364 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-2d2a542e0691b872","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhelios&oldid=13364","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4179-r13364"],"url":"https://museum.vlsi.kr/objects/cw-2d2a542e0691b872"},{"id":"cw-2d427147400f86c9","name":"K6-2/380ACK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-380ack"],"fields":[{"key":"Model name","value":"K6-2/380ACK","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/380ACK","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/380ACK","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":380,"unit":"MHz","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95 MT/s","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8361-r26056","location":"Amd/k6-2/k6-2-380ack · revision 26056 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d427147400f86c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380ack&oldid=26056","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8361-r26056"],"url":"https://museum.vlsi.kr/objects/cw-2d427147400f86c9"},{"id":"cw-2d6a6d9b80ca78e9","name":"Core i3-350M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-300","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i3 i3-350m"],"fields":[{"key":"Model name","value":"Intel Core i3-350M","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-350M","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004161AC","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004161AC","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-300","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2266.66,"unit":"MHz","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBPK","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBPL","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBU5","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBU6","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-350m&oldid=25572","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7992-r25572","location":"Intel/core i3/i3-350m · revision 25572 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":36,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":35,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":2.12,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket — package module 1","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6a6d9b80ca78e9","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7992-r25572","chipswiki-31578-r92969","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-2d6a6d9b80ca78e9"},{"id":"cw-2d6dc82c1ba1a01e","name":"Godson-2D1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Loongson","series":"Godson 2","year":2006,"architecture":"GS464","process":"130 nm","aliases":["Loongson godson 2 2d1"],"fields":[{"key":"Model name","value":"Godson-2D1","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Loongson","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"STMicroelectronics","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2D1","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2006","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2006,"unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Godson 2","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Godson 2","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"GS464","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"GS464","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7681-r24976","location":"Loongson/godson 2/2d1 · revision 24976 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d6dc82c1ba1a01e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d1&oldid=24976","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7681-r24976"],"url":"https://museum.vlsi.kr/objects/cw-2d6dc82c1ba1a01e"},{"id":"cw-2d83ecd5dbc108a2","name":"AMD-K6-III/433ACK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III Mobile","year":1999,"architecture":"K6-III","process":"0.25 µm","aliases":["Amd k6-iii-p amd-k6-iii-433ack"],"fields":[{"key":"Model name","value":"AMD-K6-III/433ACK","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III/433ACK","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III/433ACK","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III-P","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III Mobile","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":433,"unit":"MHz","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"96.22 MT/s","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sharptooth","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":9,"unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21300000,"unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118,"unit":"mm²","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8305-r25995","location":"Amd/k6-iii-p/amd-k6-iii-433ack · revision 25995 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2d83ecd5dbc108a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-433ack&oldid=25995","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8305-r25995"],"url":"https://museum.vlsi.kr/objects/cw-2d83ecd5dbc108a2"},{"id":"cw-2d88deaca15cc652","name":"Sophon BM1880","kind":"sku","entityType":"product-model","subtype":"sku","company":"Bitmain","year":2018,"architecture":"Cortex-A53","aliases":["Bitmain sophon bm1880"],"fields":[{"key":"Model name","value":"Sophon BM1880","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Bitmain","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"BM1880","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Edge Compute","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 17, 2018","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 17, 2018","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Sophon","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"RV32I","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"RISC-V","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.9,"unit":"V","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-4218-r13533","location":"Bitmain/sophon/bm1880 · revision 13533 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-25. Not an independent measurement.","entityId":"cw-2d88deaca15cc652","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1880&oldid=13533","sourceDate":"2018-12-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4218-r13533"],"url":"https://museum.vlsi.kr/objects/cw-2d88deaca15cc652"},{"id":"cw-2d89e22991dde542","name":"Ryzen 9 4900HS","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 9 4900hs"],"fields":[{"key":"Model name","value":"Ryzen 9 4900HS","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4900HS","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 16, 2020","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 16, 2020","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 9","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1750,"unit":"MHz","sourceId":"chipswiki-688-r1682","location":"Amd/ryzen 9/4900hs · revision 1682 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-2d89e22991dde542","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-688-r1682"],"url":"https://museum.vlsi.kr/objects/cw-2d89e22991dde542"},{"id":"cw-2da9f04091c2227c","name":"MSM6600","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2003,"architecture":"ARM9","aliases":["Qualcomm msm6xxx msm6600"],"fields":[{"key":"Model name","value":"Qualcomm MSM6600","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6600","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 20, 2001","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2003,"unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7656-r24917","location":"Qualcomm/msm6xxx/msm6600 · revision 24917 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2da9f04091c2227c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6600&oldid=24917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7656-r24917"],"url":"https://museum.vlsi.kr/objects/cw-2da9f04091c2227c"},{"id":"cw-2dba3f74ecc6fdcc","name":"CN3860-600 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3860-600bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3860-600 EXP","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3860-600 EXP","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3860-600BG1521-EXP","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x8 KiB","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8196-r25855","location":"Cavium/octeon/cn3860-600bg1521-exp · revision 25855 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-exp&oldid=25855","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2dba3f74ecc6fdcc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8196-r25855","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-2dba3f74ecc6fdcc"},{"id":"cw-2e1ec38f30ced26f","name":"Xeon Gold 6238T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6238t"],"fields":[{"key":"Model name","value":"Xeon Gold 6238T","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6238T","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504200401","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF9C","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":44,"unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.375,"unit":"MiB","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":704,"unit":"KiB","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":704,"unit":"KiB","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"22x1 MiB","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30.25,"unit":"MiB","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"22x1.375 MiB","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1486-r4936","location":"Intel/xeon gold/6238t · revision 4936 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2e1ec38f30ced26f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1486-r4936"],"url":"https://museum.vlsi.kr/objects/cw-2e1ec38f30ced26f"},{"id":"cw-2e32b8761ab84c5d","name":"Atom Z520PT","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z500","year":2009,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z520pt"],"fields":[{"key":"Model name","value":"Atom Z520PT","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z520PT","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CH80566EE014DT","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLGPP","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 2, 2009","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 2, 2009","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z500","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1333.33,"unit":"MHz","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"533.33 MT/s","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Menlow","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Poulsbo","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":28,"unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":24.18,"unit":"mm²","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2,"unit":"W","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":"-40 °C","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":110,"unit":"°C","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8065-r25701","location":"Intel/atom/z520pt · revision 25701 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-437","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":437,"unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e32b8761ab84c5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8065-r25701","chipswiki-31502-r92564"],"url":"https://museum.vlsi.kr/objects/cw-2e32b8761ab84c5d"},{"id":"cw-2e5f46c6e211a0e5","name":"CN5740-800 SSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5740-800bg1217-ssp"],"fields":[{"key":"Model name","value":"Cavium CN5740-800 SSP","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5740-800 SSP","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5740-800BG1217-SSP","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8180-r25839","location":"Cavium/octeon plus/cn5740-800bg1217-ssp · revision 25839 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2e5f46c6e211a0e5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8180-r25839","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-2e5f46c6e211a0e5"},{"id":"cw-2e85fda7feb43cce","name":"X-Gene 1 APM883204-X1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AppliedMicro","series":"X-Gene 1","year":2012,"architecture":"Storm","process":"40 nm","aliases":["Apm x-gene apm883204-x1"],"fields":[{"key":"Model name","value":"APM883204-X1","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AppliedMicro","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"APM883204-X1","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 28, 2011","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"X-Gene","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"X-Gene 1","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Storm","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Potenza","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.9,"unit":"V","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1866","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-4752-r15332","location":"Apm/x-gene/apm883204-x1 · revision 15332 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-2e85fda7feb43cce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883204-x1&oldid=15332","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4752-r15332"],"url":"https://museum.vlsi.kr/objects/cw-2e85fda7feb43cce"},{"id":"cw-2e8d4c6eff0119e4","name":"Exynos 9825","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 9","year":2019,"architecture":"M4","process":"7 nm","aliases":["Samsung exynos 9825"],"fields":[{"key":"Model name","value":"Exynos 9825","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":9825,"unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 6, 2019","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2019,"unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 9","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"M4","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cheetah","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A75","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":12,"unit":"GiB","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":192,"unit":"KiB","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":128,"unit":"KiB","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"2x64 KiB","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":64,"unit":"KiB","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 1)","value":"8-way set associative","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":1,"unit":"MiB","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"2x512 KiB","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 1)","value":"16-way set associative","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache — Cache (section 1)","value":2,"unit":"MiB","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization — Cache (section 1)","value":"2x1 MiB","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"2x64 KiB","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 2)","value":"4-way set associative","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"2x64 KiB","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 2)","value":"16-way set associative","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":512,"unit":"KiB","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"2x256 KiB","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 2)","value":"8-way set associative","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3600","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":26.82,"unit":"GiB/s","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G76","unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":600,"unit":"MHz","sourceId":"chipswiki-1182-r3689","location":"Samsung/exynos/9825 · revision 3689 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-26. Not an independent measurement.","entityId":"cw-2e8d4c6eff0119e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","sourceDate":"2020-04-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1182-r3689"],"url":"https://museum.vlsi.kr/objects/cw-2e8d4c6eff0119e4"},{"id":"cw-2e903e0f17276d3f","name":"Celeron 807","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 807"],"fields":[{"key":"Model name","value":"Celeron 807","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":807,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701079702","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701079700S","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701345600","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0PW","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR07G","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0VL","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2012","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2012","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x1.5 MiB","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-6945-r21632","location":"Intel/celeron/807 · revision 21632 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2e903e0f17276d3f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7871-r25374","location":"Intel/core i7/i7-4760hq · revision 25374 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4760hq&oldid=25374","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2ea08fb6459344df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-IIIE+/400ITZ","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-IIIE+/400ITZ","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. 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Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III+","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III+ Embedded","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":3,"unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21400000,"unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9.5,"unit":"W","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1010-r2861","location":"Amd/k6-iii+/amd-k6-iiie+-400itz · revision 2861 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400itz&oldid=2861","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OBGA-349","unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":349,"unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.47,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-2ea13478199793dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1010-r2861","chipswiki-31127-r91599"],"url":"https://museum.vlsi.kr/objects/cw-2ea13478199793dc"},{"id":"cw-2eacc1fb35de86c6","name":"Ryzen 7 PRO 4750U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 7 pro 4750u"],"fields":[{"key":"Model name","value":"Ryzen 7 PRO 4750U","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 4750U","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000101","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 07, 2020","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 07, 2020","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1600,"unit":"MHz","sourceId":"chipswiki-728-r1749","location":"Amd/ryzen 7/pro 4750u · revision 1749 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-2eacc1fb35de86c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-728-r1749"],"url":"https://museum.vlsi.kr/objects/cw-2eacc1fb35de86c6"},{"id":"cw-2efd4851bb5e4985","name":"Exynos 4412","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 4","year":2012,"architecture":"Cortex-A9","process":"32 nm","aliases":["Samsung exynos 4412"],"fields":[{"key":"Model name","value":"Exynos 4412","unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4412,"unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 2012","unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 2012","unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 4","unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A9","unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"HKMG","unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5172-r16835","location":"Samsung/exynos/4412 · revision 16835 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-02. Not an independent measurement.","entityId":"cw-2efd4851bb5e4985","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","sourceDate":"2018-08-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5172-r16835"],"url":"https://museum.vlsi.kr/objects/cw-2efd4851bb5e4985"},{"id":"cw-2f04f8a66375fea4","name":"Celeron 827","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 827"],"fields":[{"key":"Model name","value":"Celeron 827","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":827,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701079900","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701079901","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701079902","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR07J","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0EG","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0PY","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x1.5 MiB","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-6942-r21629","location":"Intel/celeron/827 · revision 21629 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-2f04f8a66375fea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6942-r21629","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-2f04f8a66375fea4"},{"id":"cw-2f2215a0bea9730d","name":"Atom C3858","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3858"],"fields":[{"key":"Model name","value":"Atom C3858","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3858","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502639501","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR38A","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":672,"unit":"KiB","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":288,"unit":"KiB","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x24 KiB","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-1862-r6398","location":"Intel/atom/c3858 · revision 6398 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-2f2215a0bea9730d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1862-r6398","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-2f2215a0bea9730d"},{"id":"cw-2f4c329f3b292112","name":"Alchemy Au1100-333MBC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2002,"architecture":"Au1","process":"130 nm","aliases":["Alchemy au1100-333mbc"],"fields":[{"key":"Model name","value":"Alchemy Au1100-333MBC","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1100-333MBC","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBCBA","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBCBC","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBCBD","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBCBE","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBCBF","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2002","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BA","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BC","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BD","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BE","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BF","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / core stepping 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 5","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"core stepping 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.22,"unit":"V","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.333 GB/s","unit":"","sourceId":"chipswiki-475-r956","location":"Alchemy/au1100-333mbc · revision 956 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-2f4c329f3b292112","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-475-r956"],"url":"https://museum.vlsi.kr/objects/cw-2f4c329f3b292112"},{"id":"cw-2f4d0ac37ff1e005","name":"Gen8","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2014,"process":"14 nm","aliases":["Intel microarchitectures gen8"],"fields":[{"key":"Architecture name","value":"Gen8","unit":"","sourceId":"chipswiki-15966-r52701","location":"Intel/microarchitectures/gen8 · revision 52701 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-2f4d0ac37ff1e005","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen8&oldid=52701","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-15966-r52701","location":"Intel/microarchitectures/gen8 · revision 52701 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-2f4d0ac37ff1e005","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen8&oldid=52701","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-15966-r52701","location":"Intel/microarchitectures/gen8 · revision 52701 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-2f4d0ac37ff1e005","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen8&oldid=52701","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October, 2014","unit":"","sourceId":"chipswiki-15966-r52701","location":"Intel/microarchitectures/gen8 · revision 52701 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-2f4d0ac37ff1e005","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen8&oldid=52701","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-15966-r52701","location":"Intel/microarchitectures/gen8 · revision 52701 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-2f4d0ac37ff1e005","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen8&oldid=52701","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen7.5","unit":"","sourceId":"chipswiki-15966-r52701","location":"Intel/microarchitectures/gen8 · revision 52701 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-2f4d0ac37ff1e005","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen8&oldid=52701","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen9","unit":"","sourceId":"chipswiki-15966-r52701","location":"Intel/microarchitectures/gen8 · revision 52701 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-28. Not an independent measurement.","entityId":"cw-2f4d0ac37ff1e005","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen8&oldid=52701","sourceDate":"2017-01-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15966-r52701"],"url":"https://museum.vlsi.kr/objects/cw-2f4d0ac37ff1e005"},{"id":"cw-2f6ba9fa9e7001ac","name":"Celeron N3150","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N3000","year":2015,"architecture":"Airmont","process":"14 nm","aliases":["Intel celeron n3150"],"fields":[{"key":"Model name","value":"Intel Celeron N3150","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N3150","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715913","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715924","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR29F","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2A8","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March, 2015","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2015","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N3000","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2080,"unit":"MHz","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"IDI","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Braswell","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1170","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-4336-r13971","location":"Intel/celeron/n3150 · revision 13971 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-02. Not an independent measurement.","entityId":"cw-2f6ba9fa9e7001ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","sourceDate":"2018-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4336-r13971"],"url":"https://museum.vlsi.kr/objects/cw-2f6ba9fa9e7001ac"},{"id":"cw-2f95da75eca9d402","name":"AMD-K5-PR90ABQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"SSA/5","year":1996,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr90abq"],"fields":[{"key":"Model name","value":"AMD-K5-PR90ABQ","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR90ABQ","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR90ABQ","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1996,"unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 7, 1996","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"SSA/5","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":90,"unit":"MHz","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8392-r26088","location":"Amd/k5/amd-k5-pr90abq · revision 26088 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2f95da75eca9d402","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr90abq&oldid=26088","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8392-r26088"],"url":"https://museum.vlsi.kr/objects/cw-2f95da75eca9d402"},{"id":"cw-2f9d4867166ec9fd","name":"Am186EMLV–25VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186EM","year":1997,"architecture":"80186","aliases":["Amd am186ex am186emlv–25vc\\w"],"fields":[{"key":"Model name","value":"Am186EMLV–25VC\\W","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EMLV–25VC\\W","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EMLV–25VC\\W","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14659-r44720","location":"Amd/am186ex/am186emlv–25vc\\w · revision 44720 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-2f9d4867166ec9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14659-r44720"],"url":"https://museum.vlsi.kr/objects/cw-2f9d4867166ec9fd"},{"id":"cw-2fa11637fc9baf05","name":"Xeon E5-2699A v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2699a v4"],"fields":[{"key":"Model name","value":"Xeon E5-2699A v4","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2699A v4","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066003197800","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR30Y","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 25, 2016","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 25, 2016","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-06-16. 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Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7200000000,"unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. 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Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. 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Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. 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Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5.5,"unit":"MiB","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"22x256 KiB","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":55,"unit":"MiB","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"22x2.5 MiB","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-343-r699","location":"Intel/xeon e5/e5-2699a v4 · revision 699 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-16. Not an independent measurement.","entityId":"cw-2fa11637fc9baf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2699a%20v4&oldid=699","sourceDate":"2022-06-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-343-r699"],"url":"https://museum.vlsi.kr/objects/cw-2fa11637fc9baf05"},{"id":"cw-2fa9d7c382145a1f","name":"TMS1000","kind":"sku","entityType":"product-model","subtype":"sku","company":"Texas Instruments","year":1974,"architecture":"TMS1000","process":"8 µm","aliases":["Ti tms1000 tms1000"],"fields":[{"key":"Model name","value":"TMS1000","unit":"","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Texas Instruments","unit":"","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Texas Instruments","unit":"","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"TMS1000","unit":"","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1974,"unit":"","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1974,"unit":"","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"TMS1000","unit":"","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"kHz","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"TMS1000","unit":"","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":8,"unit":"µm","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000,"unit":"","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":4,"unit":"bit","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"KiB","sourceId":"chipswiki-8444-r26152","location":"Ti/tms1000/tms1000 · revision 26152 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1000&oldid=26152","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"PDIP-28","unit":"","sourceId":"chipswiki-31335-r92066","location":"Template:Packages/pdip-28 · revision 92066 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpdip-28&oldid=92066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"PDIP","unit":"","sourceId":"chipswiki-31335-r92066","location":"Template:Packages/pdip-28 · revision 92066 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpdip-28&oldid=92066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":28,"unit":"","sourceId":"chipswiki-31335-r92066","location":"Template:Packages/pdip-28 · revision 92066 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpdip-28&oldid=92066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"CDIP-28","unit":"","sourceId":"chipswiki-31334-r92065","location":"Template:Packages/cdip-28 · revision 92065 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcdip-28&oldid=92065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"CDIP","unit":"","sourceId":"chipswiki-31334-r92065","location":"Template:Packages/cdip-28 · revision 92065 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcdip-28&oldid=92065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":28,"unit":"","sourceId":"chipswiki-31334-r92065","location":"Template:Packages/cdip-28 · revision 92065 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fa9d7c382145a1f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcdip-28&oldid=92065","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8444-r26152","chipswiki-31335-r92066","chipswiki-31334-r92065"],"url":"https://museum.vlsi.kr/objects/cw-2fa9d7c382145a1f"},{"id":"cw-2faa9aa6b752ee4a","name":"Xeon Gold 6126","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6126"],"fields":[{"key":"Model name","value":"Xeon Gold 6126","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6126,"unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303405900","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3B3","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1516-r4968","location":"Intel/xeon gold/6126 · revision 4968 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2faa9aa6b752ee4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1516-r4968"],"url":"https://museum.vlsi.kr/objects/cw-2faa9aa6b752ee4a"},{"id":"cw-2fdc5ac74c908114","name":"CN5830-800 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5830-800bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5830-800 EXP","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5830-800 EXP","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5830-800BG1521-EXP","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x16 KiB","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8155-r25814","location":"Cavium/octeon plus/cn5830-800bg1521-exp · revision 25814 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-800bg1521-exp&oldid=25814","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-2fdc5ac74c908114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8155-r25814","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-2fdc5ac74c908114"},{"id":"cw-2feb2f83e5b308e3","name":"Xeon Platinum 8153","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8153"],"fields":[{"key":"Model name","value":"Xeon Platinum 8153","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8153,"unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303408900","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3BA","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1474-r4922","location":"Intel/xeon platinum/8153 · revision 4922 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-2feb2f83e5b308e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8153&oldid=4922","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1474-r4922"],"url":"https://museum.vlsi.kr/objects/cw-2feb2f83e5b308e3"},{"id":"cw-301237f982416c64","name":"Atom x5-E8000","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E8000","year":2016,"architecture":"Airmont","process":"14 nm","aliases":["Intel atom x5 x5-e8000"],"fields":[{"key":"Model name","value":"Intel Atom x5-E8000","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x5-E8000","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715946","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LV","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 8, 2016","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 8, 2016","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x5","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E8000","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1040,"unit":"MHz","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2000,"unit":"MHz","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Braswell","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Braswell","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":5,"unit":"W","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1170","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-6858-r21411","location":"Intel/atom x5/x5-e8000 · revision 21411 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-301237f982416c64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6858-r21411"],"url":"https://museum.vlsi.kr/objects/cw-301237f982416c64"},{"id":"cw-3044cecc9fb1dc57","name":"Exynos 7570","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 7","year":2016,"architecture":"Cortex-A53","process":"14 nm","aliases":["Samsung exynos 7570"],"fields":[{"key":"Model name","value":"Exynos 7570","unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7570,"unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 7","unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6844-r21329","location":"Samsung/exynos/7570 · revision 21329 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-3044cecc9fb1dc57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6844-r21329"],"url":"https://museum.vlsi.kr/objects/cw-3044cecc9fb1dc57"},{"id":"cw-305221e1b17b11e0","name":"Core i7-5850EQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5800","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core i7 i7-5850eq"],"fields":[{"key":"Model name","value":"Intel Core i7-5850EQ","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-5850EQ","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065802420503","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 2, 2015","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 2, 2015","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5800,"unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2E8","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"G0","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"shared","unit":"","sourceId":"chipswiki-7859-r25359","location":"Intel/core i7/i7-5850eq · revision 25359 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850eq&oldid=25359","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-305221e1b17b11e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7859-r25359","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-305221e1b17b11e0"},{"id":"cw-307e0d32b83eaafc","name":"i486DX-20","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486DX","year":1989,"architecture":"80486","process":"1 µm","aliases":["Intel 80486 486dx-20"],"fields":[{"key":"Model name","value":"Intel i486DX-20","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486DX-20","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX-20","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 10, 1989","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 1989","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486DX","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"20 MT/s","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-307e0d32b83eaafc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-20&oldid=25745","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8092-r25745","location":"Intel/80486/486dx-20 · revision 25745 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B800","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701142600","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0EW","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6929-r21615","location":"Intel/celeron/b800 · revision 21615 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-3089e9879458d851","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6929-r21615","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-3089e9879458d851"},{"id":"cw-30ac8db02ecb1a53","name":"Ryzen 3 2300X","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Ryzen","year":2018,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 3 2300x"],"fields":[{"key":"Model name","value":"Ryzen 3 2300X","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2300X","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 10, 2018","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 10, 2018","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Ryzen","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Pinnacle Ridge","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-4248-r13714","location":"Amd/ryzen 3/2300x · revision 13714 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","sourceDate":"2018-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-15. Not an independent measurement.","entityId":"cw-30ac8db02ecb1a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4248-r13714","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-30ac8db02ecb1a53"},{"id":"cw-30b6c98691286d7d","name":"Opteron A1150","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"A1100","year":2016,"architecture":"Cortex-A57","process":"28 nm","aliases":["Amd opteron a1150"],"fields":[{"key":"Model name","value":"Opteron A1150","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Global Foundries","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A1150","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"OA1150AQD8NAD","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2014","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2016","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Opteron","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"A1100","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A57","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Seattle","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":32,"unit":"W","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":80,"unit":"°C","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8 × 48 KiB","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"3-way set associative","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8 × 32 KiB","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4 × 1 MiB","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1866","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"29.9 GB/s","unit":"","sourceId":"chipswiki-956-r2706","location":"Amd/opteron/a1150 · revision 2706 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1150&oldid=2706","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SP1","unit":"","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1021,"unit":"","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":27,"unit":"mm","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":27,"unit":"mm","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.46,"unit":"mm","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-30b6c98691286d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-956-r2706","chipswiki-31113-r91580"],"url":"https://museum.vlsi.kr/objects/cw-30b6c98691286d7d"},{"id":"cw-30c6e95040121ca7","name":"Xeon E3-1505M v6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1500","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel xeon e3 e3-1505m v6"],"fields":[{"key":"Model name","value":"Xeon E3-1505M v6","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1505M v6","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR32K","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics P630","unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-6409-r20008","location":"Intel/xeon e3/e3-1505m v6 · revision 20008 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v6&oldid=20008","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-30c6e95040121ca7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6409-r20008","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-30c6e95040121ca7"},{"id":"cw-30f11fc9c4967e53","name":"Xeon Gold 6248","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6248"],"fields":[{"key":"Model name","value":"Xeon Gold 6248","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6248,"unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504194301","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806956248","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF90","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":27.5,"unit":"MiB","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x1.375 MiB","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-30f11fc9c4967e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6248&oldid=4927","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1479-r4927","location":"Intel/xeon gold/6248 · revision 4927 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1637","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8068204237101","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRG0A","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1600","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. 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Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Hewitt Lake","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":55,"unit":"W","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. 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Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-30f330b1e2731e9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1637&oldid=11009","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3681-r11009","location":"Intel/xeon d/d-1637 · revision 11009 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. 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Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":449.99,"unit":"MHz","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.1,"unit":"V","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8346-r26041","location":"Amd/k6-2/k6-2-450adk · revision 26041 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-310ddcaaecd2e2e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450adk&oldid=26041","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8346-r26041"],"url":"https://museum.vlsi.kr/objects/cw-310ddcaaecd2e2e2"},{"id":"cw-313fb659d1b2b5b5","name":"Xeon E-2274G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2200","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2274g"],"fields":[{"key":"Model name","value":"Xeon E-2274G","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2274G","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068404174407","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFDE","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4000,"unit":"MHz","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4900,"unit":"MHz","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake ER","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2408-r8042","location":"Intel/xeon e/e-2274g · revision 8042 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-313fb659d1b2b5b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2408-r8042"],"url":"https://museum.vlsi.kr/objects/cw-313fb659d1b2b5b5"},{"id":"cw-3149058dd651dad9","name":"Atom Z605","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z605","year":2010,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z605"],"fields":[{"key":"Model name","value":"Atom Z605","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z605","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AY80609005805AA","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3C","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z605","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"cDMI","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Moorestown","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Langwell","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lincroft","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":38,"unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":140000000,"unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":65.2526,"unit":"mm²","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2.2,"unit":"W","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX535","unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8058-r25694","location":"Intel/atom/z605 · revision 25694 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-518","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":518,"unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.1,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3149058dd651dad9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8058-r25694","chipswiki-31501-r92563"],"url":"https://museum.vlsi.kr/objects/cw-3149058dd651dad9"},{"id":"cw-31a14c1d4008d459","name":"EPYC 75F3","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 75f3"],"fields":[{"key":"Model name","value":"EPYC 75F3","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. 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Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"75F3","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000313","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000313WOF","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2950,"unit":"MHz","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. 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Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":280,"unit":"W","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32 × 512 KiB","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 32 MiB","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-749-r1790","location":"Amd/epyc/75f3 · revision 1790 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-19. Not an independent measurement.","entityId":"cw-31a14c1d4008d459","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","sourceDate":"2021-05-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-749-r1790"],"url":"https://museum.vlsi.kr/objects/cw-31a14c1d4008d459"},{"id":"cw-31b1e3d1cd9e50d5","name":"R-Car H1","kind":"sku","entityType":"product-model","subtype":"soc","company":"Renesas","series":"1st Gen","year":2011,"architecture":"Cortex-A9","process":"40 nm","aliases":["Renesas r-car h1"],"fields":[{"key":"Model name","value":"R-Car H1","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"H1","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"R8A77790","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 21, 2011","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2011","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"1st Gen","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":800,"unit":"MHz","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1000,"unit":"MHz","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A9","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A9","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SH-4A","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":5,"unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":5,"unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":7.95,"unit":"GiB/s","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX543","unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":250,"unit":"MHz","sourceId":"chipswiki-7651-r24912","location":"Renesas/r-car/h1 · revision 24912 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh1&oldid=24912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-832","unit":"","sourceId":"chipswiki-31428-r92299","location":"Template:Packages/renesas/fcbga-832 · revision 92299 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-832&oldid=92299","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31428-r92299","location":"Template:Packages/renesas/fcbga-832 · revision 92299 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-832&oldid=92299","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":832,"unit":"","sourceId":"chipswiki-31428-r92299","location":"Template:Packages/renesas/fcbga-832 · revision 92299 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-832&oldid=92299","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31428-r92299","location":"Template:Packages/renesas/fcbga-832 · revision 92299 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-832&oldid=92299","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":27,"unit":"mm","sourceId":"chipswiki-31428-r92299","location":"Template:Packages/renesas/fcbga-832 · revision 92299 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-832&oldid=92299","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":27,"unit":"mm","sourceId":"chipswiki-31428-r92299","location":"Template:Packages/renesas/fcbga-832 · revision 92299 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31b1e3d1cd9e50d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-832&oldid=92299","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7651-r24912","chipswiki-31428-r92299"],"url":"https://museum.vlsi.kr/objects/cw-31b1e3d1cd9e50d5"},{"id":"cw-31c0b4d80db1cef8","name":"D8086","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 d8086"],"fields":[{"key":"Model name","value":"AMD D8086","unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D8086","unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D8086","unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D8086","unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":5,"unit":"MHz","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8518-r26711","location":"Amd/am8086/d8086 · revision 26711 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31c0b4d80db1cef8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8518-r26711"],"url":"https://museum.vlsi.kr/objects/cw-31c0b4d80db1cef8"},{"id":"cw-31d2cafeab95c760","name":"Duron 900 (Camaro)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhm0900aqs1b"],"fields":[{"key":"Model name","value":"Duron 900","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 900","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHM0900AQS1B","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 20, 2001","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 20, 2001","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.45,"unit":"V","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8413-r26121","location":"Amd/duron/dhm0900aqs1b · revision 26121 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31d2cafeab95c760","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8413-r26121"],"url":"https://museum.vlsi.kr/objects/cw-31d2cafeab95c760"},{"id":"cw-31da306ea195ba3e","name":"Pentium 957","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"900","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel pentium (2009) 957"],"fields":[{"key":"Model name","value":"Pentium 957","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":957,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700852600","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR089","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 13, 2011","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 13, 2011","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F957&oldid=25234","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-7796-r25234","location":"Intel/pentium (2009)/957 · revision 25234 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-31da306ea195ba3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8164,"unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806738164","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303408800","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3BB","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":26,"unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":52,"unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.625,"unit":"MiB","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":832,"unit":"KiB","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"26x32 KiB","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":832,"unit":"KiB","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"26x32 KiB","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":26,"unit":"MiB","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"26x1 MiB","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1472-r4919","location":"Intel/xeon platinum/8164 · revision 4919 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-31dd12612f877c27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8164&oldid=4919","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1472-r4919"],"url":"https://museum.vlsi.kr/objects/cw-31dd12612f877c27"},{"id":"cw-320cf44003d23aea","name":"CN3110-550 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-550bg868-cp"],"fields":[{"key":"Model name","value":"Cavium CN3110-550 CP","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-550 CP","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-550BG868-CP","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":550,"unit":"MHz","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8257-r25917","location":"Cavium/octeon/cn3110-550bg868-cp · revision 25917 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-cp&oldid=25917","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-320cf44003d23aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8257-r25917","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-320cf44003d23aea"},{"id":"cw-3214b6729702f7b9","name":"Core i3-6098P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 i3-6098p"],"fields":[{"key":"Model name","value":"Core i3-6098P","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6098P","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80662I36098P","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80662I36098P","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201927211","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2NN","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 27, 2015","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 27, 2015","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54,"unit":"W","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7988-r25566","location":"Intel/core i3/i3-6098p · revision 25566 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6098p&oldid=25566","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3214b6729702f7b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02CY227","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02CY227","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.6,"unit":"GHz","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":88,"unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":190,"unit":"W","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.375,"unit":"MiB","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":704,"unit":"KiB","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":704,"unit":"KiB","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5.5,"unit":"MiB","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"11x512 KiB","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":110,"unit":"MiB","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"11x10 MiB","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3949-r12595","location":"Ibm/power/02cy227 · revision 12595 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-323a75851046c596","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy227&oldid=12595","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3949-r12595"],"url":"https://museum.vlsi.kr/objects/cw-323a75851046c596"},{"id":"cw-326c583ed9a962be","name":"Xeon Silver 4112","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon silver 4112"],"fields":[{"key":"Model name","value":"Xeon Silver 4112","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4112,"unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806734112","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303562100","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3GN","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8.25,"unit":"MiB","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-326c583ed9a962be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4112&oldid=4894","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1450-r4894","location":"Intel/xeon silver/4112 · revision 4894 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5830-900 NSP","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5830-900BG1521-NSP","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x16 KiB","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8151-r25810","location":"Cavium/octeon plus/cn5830-900bg1521-nsp · revision 25810 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-nsp&oldid=25810","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-32c6047ca69d8451","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8151-r25810","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-32c6047ca69d8451"},{"id":"cw-32f0bfbbff12407d","name":"Hexagon","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Qualcomm","year":null,"process":"65 - 28","aliases":["Qualcomm microarchitectures hexagon"],"fields":[{"key":"Architecture name","value":"Hexagon","unit":"","sourceId":"chipswiki-3931-r12520","location":"Qualcomm/microarchitectures/hexagon · revision 12520 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-32f0bfbbff12407d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fhexagon&oldid=12520","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-3931-r12520","location":"Qualcomm/microarchitectures/hexagon · revision 12520 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-32f0bfbbff12407d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fhexagon&oldid=12520","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-3931-r12520","location":"Qualcomm/microarchitectures/hexagon · revision 12520 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-32f0bfbbff12407d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fhexagon&oldid=12520","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"65 - 28","unit":"","sourceId":"chipswiki-3931-r12520","location":"Qualcomm/microarchitectures/hexagon · revision 12520 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-32f0bfbbff12407d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fhexagon&oldid=12520","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"4-way VLIW, 4-thread SMT","unit":"","sourceId":"chipswiki-3931-r12520","location":"Qualcomm/microarchitectures/hexagon · revision 12520 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-32f0bfbbff12407d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fhexagon&oldid=12520","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-3931-r12520","location":"Qualcomm/microarchitectures/hexagon · revision 12520 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-28. Not an independent measurement.","entityId":"cw-32f0bfbbff12407d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmicroarchitectures%2Fhexagon&oldid=12520","sourceDate":"2019-01-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3931-r12520"],"url":"https://museum.vlsi.kr/objects/cw-32f0bfbbff12407d"},{"id":"cw-33183613b33bda96","name":"Ryzen 3 PRO 2300U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000U","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 3 pro 2300u"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 2300U","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 2300U","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 8, 2018","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 8, 2018","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"2000U","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-6283-r19492","location":"Amd/ryzen 3/pro 2300u · revision 19492 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-33183613b33bda96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6283-r19492","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-33183613b33bda96"},{"id":"cw-332e88c9aa15c0c6","name":"EPYC 7371","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2019,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7371"],"fields":[{"key":"Model name","value":"EPYC 7371","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7371,"unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS7371BDVGPAF","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 13, 2018","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2019,"unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":200,"unit":"W","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x64 KiB","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x512 KiB","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x8 MiB","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-2859-r9637","location":"Amd/epyc/7371 · revision 9637 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7371&oldid=9637","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-332e88c9aa15c0c6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2859-r9637","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-332e88c9aa15c0c6"},{"id":"cw-33339feca7af9c78","name":"Core i7-2660M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2660m"],"fields":[{"key":"Model name","value":"Core i7-2660M","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2660M","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701122000","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0GC","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2011,"unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7887-r25391","location":"Intel/core i7/i7-2660m · revision 25391 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2660m&oldid=25391","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33339feca7af9c78","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7887-r25391","chipswiki-31339-r92076","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-33339feca7af9c78"},{"id":"cw-33542571c3e7eafd","name":"D8086B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 d8086b"],"fields":[{"key":"Model name","value":"AMD D8086B","unit":"","sourceId":"chipswiki-8513-r26706","location":"Amd/am8086/d8086b · revision 26706 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33542571c3e7eafd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086b&oldid=26706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8513-r26706","location":"Amd/am8086/d8086b · revision 26706 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-33542571c3e7eafd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086b&oldid=26706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D8086B","unit":"","sourceId":"chipswiki-8513-r26706","location":"Amd/am8086/d8086b · revision 26706 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33542571c3e7eafd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086b&oldid=26706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D8086B","unit":"","sourceId":"chipswiki-8513-r26706","location":"Amd/am8086/d8086b · revision 26706 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33542571c3e7eafd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086b&oldid=26706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8513-r26706","location":"Amd/am8086/d8086b · revision 26706 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33542571c3e7eafd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086b&oldid=26706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8513-r26706","location":"Amd/am8086/d8086b · revision 26706 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33542571c3e7eafd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086b&oldid=26706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8513-r26706","location":"Amd/am8086/d8086b · revision 26706 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33542571c3e7eafd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086b&oldid=26706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D8086","unit":"","sourceId":"chipswiki-8513-r26706","location":"Amd/am8086/d8086b · revision 26706 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33542571c3e7eafd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086b&oldid=26706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":5,"unit":"MHz","sourceId":"chipswiki-8513-r26706","location":"Amd/am8086/d8086b · revision 26706 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33542571c3e7eafd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086b&oldid=26706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8513-r26706","location":"Amd/am8086/d8086b · revision 26706 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-33542571c3e7eafd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086b&oldid=26706","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8513-r26706","location":"Amd/am8086/d8086b · revision 26706 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6142M","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303405700","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3B1","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1501-r4953","location":"Intel/xeon gold/6142m · revision 4953 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3354f62d748c7121","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142m&oldid=4953","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1501-r4953"],"url":"https://museum.vlsi.kr/objects/cw-3354f62d748c7121"},{"id":"cw-335834d8217a1a41","name":"Ryzen Embedded V1605B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"V1000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen embedded v1605b"],"fields":[{"key":"Model name","value":"Ryzen Embedded V1605B","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"V1605B","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YE1605C4T4MFB","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"V1000","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Great Horned Owl","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-928-r2552","location":"Amd/ryzen embedded/v1605b · revision 2552 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1605b&oldid=2552","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-335834d8217a1a41","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-928-r2552","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-335834d8217a1a41"},{"id":"cw-335a606687df5a36","name":"Core i3-9100T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-9000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-9100t"],"fields":[{"key":"Model name","value":"Core i3-9100T","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-9100T","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403377425","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRCZX","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-9000","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake R","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":82,"unit":"°C","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-953-r2703","location":"Intel/core i3/i3-9100t · revision 2703 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-09. Not an independent measurement.","entityId":"cw-335a606687df5a36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9100t&oldid=2703","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-953-r2703"],"url":"https://museum.vlsi.kr/objects/cw-335a606687df5a36"},{"id":"cw-339105ba48acacc0","name":"Cortex-A57","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2012,"aliases":["Arm holdings microarchitectures cortex-a57"],"fields":[{"key":"Architecture name","value":"Cortex-A57","unit":"","sourceId":"chipswiki-780-r1918","location":"Arm holdings/microarchitectures/cortex-a57 · revision 1918 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-339105ba48acacc0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a57&oldid=1918","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-780-r1918","location":"Arm holdings/microarchitectures/cortex-a57 · revision 1918 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-339105ba48acacc0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a57&oldid=1918","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-780-r1918","location":"Arm holdings/microarchitectures/cortex-a57 · revision 1918 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-339105ba48acacc0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a57&oldid=1918","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"Oct 30, 2012","unit":"","sourceId":"chipswiki-780-r1918","location":"Arm holdings/microarchitectures/cortex-a57 · revision 1918 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-339105ba48acacc0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a57&oldid=1918","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-780-r1918","location":"Arm holdings/microarchitectures/cortex-a57 · revision 1918 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-339105ba48acacc0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a57&oldid=1918","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A15","unit":"","sourceId":"chipswiki-780-r1918","location":"Arm holdings/microarchitectures/cortex-a57 · revision 1918 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-339105ba48acacc0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a57&oldid=1918","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A72","unit":"","sourceId":"chipswiki-780-r1918","location":"Arm holdings/microarchitectures/cortex-a57 · revision 1918 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-339105ba48acacc0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a57&oldid=1918","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-780-r1918"],"url":"https://museum.vlsi.kr/objects/cw-339105ba48acacc0"},{"id":"cw-3395d581dfec29eb","name":"CN3120-550 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-550bg868-scp"],"fields":[{"key":"Model name","value":"Cavium CN3120-550 SCP","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-550 SCP","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3120-550BG868-SCP","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":550,"unit":"MHz","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. 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Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. 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Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. 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Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-802-r2031","location":"Cavium/octeon/cn3120-550bg868-scp · revision 2031 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-scp&oldid=2031","sourceDate":"2021-03-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-14. Not an independent measurement.","entityId":"cw-3395d581dfec29eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-802-r2031","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-3395d581dfec29eb"},{"id":"cw-33a082258db632d5","name":"K6-2E+/400ITZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2e+-400itz"],"fields":[{"key":"Model name","value":"K6-2E+/400ITZ","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E+/400ITZ","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E+/400ITZ","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9.5,"unit":"W","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Embedded","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1004-r2855","location":"Amd/k6-2+/k6-2e+-400itz · revision 2855 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400itz&oldid=2855","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OBGA-349","unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":349,"unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.47,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-33a082258db632d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1004-r2855","chipswiki-31127-r91599"],"url":"https://museum.vlsi.kr/objects/cw-33a082258db632d5"},{"id":"cw-33a3242edf3c9acf","name":"Xeon E5-2650L v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2650l v4"],"fields":[{"key":"Model name","value":"Xeon E5-2650L v4","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2650L v4","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002033006","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2N8","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3.5,"unit":"MiB","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x256 KiB","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35,"unit":"MiB","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x2.5 MiB","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7734-r25111","location":"Intel/xeon e5/e5-2650l v4 · revision 25111 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-33a3242edf3c9acf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2650l%20v4&oldid=25111","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7734-r25111"],"url":"https://museum.vlsi.kr/objects/cw-33a3242edf3c9acf"},{"id":"cw-33cb469cb7e2a45c","name":"Ryzen 3 4300G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 3 4300g"],"fields":[{"key":"Model name","value":"Ryzen 3 4300G","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4300G","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000144","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 21, 2020","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1700,"unit":"MHz","sourceId":"chipswiki-697-r1692","location":"Amd/ryzen 3/4300g · revision 1692 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-33cb469cb7e2a45c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F4300g&oldid=1692","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-697-r1692"],"url":"https://museum.vlsi.kr/objects/cw-33cb469cb7e2a45c"},{"id":"cw-33cf9aef5c700fc9","name":"Ryzen 5 PRO 3400GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 5 pro 3400ge"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 3400GE","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3400GE","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD340BC6M4MFH","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon RX Vega 11","unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":11,"unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-1552-r5093","location":"Amd/ryzen 5/pro 3400ge · revision 5093 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-21. Not an independent measurement.","entityId":"cw-33cf9aef5c700fc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","sourceDate":"2019-12-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1552-r5093"],"url":"https://museum.vlsi.kr/objects/cw-33cf9aef5c700fc9"},{"id":"cw-3405752115738822","name":"Xeon Gold 6238L","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6238l"],"fields":[{"key":"Model name","value":"Xeon Gold 6238L","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6238L","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":44,"unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4.5 TiB","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.375,"unit":"MiB","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":704,"unit":"KiB","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":704,"unit":"KiB","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"22x1 MiB","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30.25,"unit":"MiB","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"22x1.375 MiB","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1487-r4937","location":"Intel/xeon gold/6238l · revision 4937 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3405752115738822","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1487-r4937"],"url":"https://museum.vlsi.kr/objects/cw-3405752115738822"},{"id":"cw-341ee4891f99025f","name":"Core i7-620M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-600","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7 i7-620m"],"fields":[{"key":"Model name","value":"Intel Core i7-620M","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-620M","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617003981AH","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617003981AH","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617006930AA","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2666.66,"unit":"MHz","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3333.33,"unit":"MHz","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBPD","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBTQ","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBPE","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBTR","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBZT","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. 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Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. 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Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-1228-r3848","location":"Intel/core i7/i7-620m · revision 3848 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-26. 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Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620m&oldid=3848","sourceDate":"2020-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"rPGA-988A","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-03-26. 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Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":988,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":1,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":36,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":35,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":2.12,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket — package module 1","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-03-26. Not an independent measurement.","entityId":"cw-341ee4891f99025f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2020-03-26. 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Not an independent measurement.","entityId":"cw-34384110aa41a9dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114t&oldid=546","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-271-r546","location":"Intel/xeon silver/4114t · revision 546 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. 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Not an independent measurement.","entityId":"cw-34384110aa41a9dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114t&oldid=546","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-271-r546","location":"Intel/xeon silver/4114t · revision 546 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. 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Not an independent measurement.","entityId":"cw-34384110aa41a9dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114t&oldid=546","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-271-r546","location":"Intel/xeon silver/4114t · revision 546 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. 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Not an independent measurement.","entityId":"cw-34384110aa41a9dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114t&oldid=546","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-271-r546","location":"Intel/xeon silver/4114t · revision 546 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. 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Not an independent measurement.","entityId":"cw-34384110aa41a9dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114t&oldid=546","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-271-r546","location":"Intel/xeon silver/4114t · revision 546 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. 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Not an independent measurement.","entityId":"cw-34384110aa41a9dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114t&oldid=546","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-271-r546","location":"Intel/xeon silver/4114t · revision 546 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-34384110aa41a9dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114t&oldid=546","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-271-r546","location":"Intel/xeon silver/4114t · revision 546 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-34384110aa41a9dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114t&oldid=546","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-271-r546","location":"Intel/xeon silver/4114t · revision 546 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-34384110aa41a9dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114t&oldid=546","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-271-r546","location":"Intel/xeon silver/4114t · revision 546 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-34384110aa41a9dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114t&oldid=546","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-271-r546","location":"Intel/xeon silver/4114t · revision 546 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-34384110aa41a9dd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114t&oldid=546","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-271-r546"],"url":"https://museum.vlsi.kr/objects/cw-34384110aa41a9dd"},{"id":"cw-34480573aa3bcdb0","name":"Embedded G-Series T40N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"G-Series APU/CPU","year":2011,"architecture":"Bobcat","process":"40 nm","aliases":["Amd embedded t40n"],"fields":[{"key":"Model name","value":"Embedded G-Series T40N","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"T40N","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GET40NFPB22GVE","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 19, 2011","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Embedded G-Series","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G-Series APU/CPU","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bobcat","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"eBrazos","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":20,"unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":451000000,"unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":75,"unit":"mm²","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. 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Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2 × 512 KiB","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"8.53 GB/s","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon HD 6290","unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":280,"unit":"MHz","sourceId":"chipswiki-422-r894","location":"Amd/embedded/t40n · revision 894 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40n&oldid=894","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FT1","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":413,"unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.8-1.0 mm","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.92,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-34480573aa3bcdb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-422-r894","chipswiki-31122-r91589"],"url":"https://museum.vlsi.kr/objects/cw-34480573aa3bcdb0"},{"id":"cw-344e6a1f2d2d4908","name":"K6-2/450AFX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-450afx"],"fields":[{"key":"Model name","value":"K6-2/450AFX","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/450AFX","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/450AFX","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 26, 1999","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 11, 1999","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":449.99,"unit":"MHz","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8345-r26040","location":"Amd/k6-2/k6-2-450afx · revision 26040 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-344e6a1f2d2d4908","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-450afx&oldid=26040","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8345-r26040"],"url":"https://museum.vlsi.kr/objects/cw-344e6a1f2d2d4908"},{"id":"cw-3451cae5770d69bf","name":"CN3860-500 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3860-500bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3860-500 EXP","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3860-500 EXP","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3860-500BG1521-EXP","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x8 KiB","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8199-r25858","location":"Cavium/octeon/cn3860-500bg1521-exp · revision 25858 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-exp&oldid=25858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3451cae5770d69bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8199-r25858","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-3451cae5770d69bf"},{"id":"cw-346caad54c923841","name":"CN5830-900 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5830-900bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5830-900 SCP","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5830-900 SCP","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5830-900BG1521-SCP","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x16 KiB","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8150-r25809","location":"Cavium/octeon plus/cn5830-900bg1521-scp · revision 25809 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-900bg1521-scp&oldid=25809","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-346caad54c923841","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8150-r25809","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-346caad54c923841"},{"id":"cw-347f82866164ec5b","name":"EyeQ5","kind":"sku","entityType":"product-model","subtype":"sku","company":"Mobileye","year":2021,"process":"7 nm","aliases":["Mobileye eyeq eyeq5"],"fields":[{"key":"Model name","value":"EyeQ5","unit":"","sourceId":"chipswiki-2935-r9821","location":"Mobileye/eyeq/eyeq5 · revision 9821 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-347f82866164ec5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq5&oldid=9821","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Mobileye","unit":"","sourceId":"chipswiki-2935-r9821","location":"Mobileye/eyeq/eyeq5 · revision 9821 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-347f82866164ec5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq5&oldid=9821","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2935-r9821","location":"Mobileye/eyeq/eyeq5 · revision 9821 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-347f82866164ec5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq5&oldid=9821","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Automotive","unit":"","sourceId":"chipswiki-2935-r9821","location":"Mobileye/eyeq/eyeq5 · revision 9821 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-347f82866164ec5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq5&oldid=9821","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 17, 2016","unit":"","sourceId":"chipswiki-2935-r9821","location":"Mobileye/eyeq/eyeq5 · revision 9821 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-347f82866164ec5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq5&oldid=9821","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2021","unit":"","sourceId":"chipswiki-2935-r9821","location":"Mobileye/eyeq/eyeq5 · revision 9821 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-347f82866164ec5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq5&oldid=9821","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EyeQ","unit":"","sourceId":"chipswiki-2935-r9821","location":"Mobileye/eyeq/eyeq5 · revision 9821 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-347f82866164ec5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq5&oldid=9821","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-2935-r9821","location":"Mobileye/eyeq/eyeq5 · revision 9821 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-347f82866164ec5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq5&oldid=9821","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2935-r9821","location":"Mobileye/eyeq/eyeq5 · revision 9821 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-347f82866164ec5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq5&oldid=9821","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":10,"unit":"W","sourceId":"chipswiki-2935-r9821","location":"Mobileye/eyeq/eyeq5 · revision 9821 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-347f82866164ec5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq5&oldid=9821","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2935-r9821"],"url":"https://museum.vlsi.kr/objects/cw-347f82866164ec5b"},{"id":"cw-349687c1d4daf14a","name":"Am186ED–33VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186ed–33vc\\w"],"fields":[{"key":"Model name","value":"Am186ED–33VC\\W","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ED–33VC\\W","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ED–33VC\\W","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8.25 MT/s","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14665-r44726","location":"Amd/am186ex/am186ed–33vc\\w · revision 44726 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-349687c1d4daf14a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14665-r44726"],"url":"https://museum.vlsi.kr/objects/cw-349687c1d4daf14a"},{"id":"cw-34a750b45ecd5197","name":"Ryzen Embedded V1756B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"V1000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen embedded v1756b"],"fields":[{"key":"Model name","value":"Ryzen Embedded V1756B","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"V1756B","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YE1756C3T4MFB","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"V1000","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3250,"unit":"MHz","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Great Horned Owl","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-929-r2553","location":"Amd/ryzen embedded/v1756b · revision 2553 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1756b&oldid=2553","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-34a750b45ecd5197","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-929-r2553","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-34a750b45ecd5197"},{"id":"cw-34abf0654850fca8","name":"i486DX2-50","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486DX2","year":1992,"architecture":"80486","process":"1 µm","aliases":["Intel 80486 486dx2-50"],"fields":[{"key":"Model name","value":"Intel i486DX2-50","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486DX2-50","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-50","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MA80486DX2-50","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MQ80486DX2-50","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"TQ80486DX250","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"SB80486DX2-50","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 3, 1992","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486DX2","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"25 MT/s","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX626","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX627","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX641","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX721","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX738","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX749","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 6","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX760","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 7","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX761","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 8","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX768","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 9","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 9","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 9","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX808","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 10","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 10","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 10","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX825","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 11","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 11","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 11","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX912","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 12","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 12","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 12","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX920","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 13","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 13","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 13","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX954","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / s-spec 14","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 14","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"s-spec 14","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8088-r25740","location":"Intel/80486/486dx2-50 · revision 25740 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34abf0654850fca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx2-50&oldid=25740","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8088-r25740"],"url":"https://museum.vlsi.kr/objects/cw-34abf0654850fca8"},{"id":"cw-34b0a55b7a9d6539","name":"80186/BZC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 80186-bzc"],"fields":[{"key":"Model name","value":"80186/BZC","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"80186/BZC","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"80186/BZC","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"2 MT/s","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8657-r26856","location":"Amd/am186/80186-bzc · revision 26856 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34b0a55b7a9d6539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8657-r26856"],"url":"https://museum.vlsi.kr/objects/cw-34b0a55b7a9d6539"},{"id":"cw-34c56b3199255f07","name":"Pixel Visual Core (PVC)","kind":"sku","entityType":"product-model","subtype":"sku","company":"Google","year":2017,"process":"28 nm","aliases":["Google pixel visual core"],"fields":[{"key":"Model name","value":"Pixel Visual Core","unit":"","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Google","unit":"","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"X726C502","unit":"","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3HX","unit":"","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 17, 2017","unit":"","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 17, 2017","unit":"","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"vISA","unit":"","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":8,"unit":"W","sourceId":"chipswiki-3043-r10190","location":"Google/pixel visual core · revision 10190 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-34c56b3199255f07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Google%2Fpixel%20visual%20core&oldid=10190","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3043-r10190"],"url":"https://museum.vlsi.kr/objects/cw-34c56b3199255f07"},{"id":"cw-34d71f9f9c4a6d71","name":"N8086-1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N8086","year":null,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 n8086-1"],"fields":[{"key":"Model name","value":"AMD N8086-1","unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N8086-1","unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"N8086-1","unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N8086","unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-44","unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8498-r26691","location":"Amd/am8086/n8086-1 · revision 26691 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-34d71f9f9c4a6d71","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8498-r26691"],"url":"https://museum.vlsi.kr/objects/cw-34d71f9f9c4a6d71"},{"id":"cw-350a2e30fdf65d90","name":"Zen 4","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":null,"process":"5nm, 6nm","aliases":["Amd microarchitectures zen 4"],"fields":[{"key":"Architecture name","value":"Zen 4","unit":"","sourceId":"chipswiki-21-r96948","location":"Amd/microarchitectures/zen 4 · revision 96948 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. 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Not an independent measurement.","entityId":"cw-350a2e30fdf65d90","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%204&oldid=96948","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Zen 3","unit":"","sourceId":"chipswiki-21-r96948","location":"Amd/microarchitectures/zen 4 · revision 96948 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-350a2e30fdf65d90","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%204&oldid=96948","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Zen 5","unit":"","sourceId":"chipswiki-21-r96948","location":"Amd/microarchitectures/zen 4 · revision 96948 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. 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Not an independent measurement.","entityId":"cw-351f7d103217f444","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Farctic%20sound&oldid=19679","sourceDate":"2018-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6346-r19679","location":"Intel/microarchitectures/arctic sound · revision 19679 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-30. 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Not an independent measurement.","entityId":"cw-351f7d103217f444","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Farctic%20sound&oldid=19679","sourceDate":"2018-04-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-6346-r19679","location":"Intel/microarchitectures/arctic sound · revision 19679 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-30. 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Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 32 KiB","unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1 × 512 KiB","unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"8.53 GB/s","unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon HD 6250","unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":280,"unit":"MHz","sourceId":"chipswiki-421-r893","location":"Amd/embedded/t40r · revision 893 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft40r&oldid=893","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FT1","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":413,"unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.8-1.0 mm","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.92,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3531b359c47c0540","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-421-r893","chipswiki-31122-r91589"],"url":"https://museum.vlsi.kr/objects/cw-3531b359c47c0540"},{"id":"cw-3532bcb5c15853df","name":"Embedded G-Series T30L","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"G-Series APU/CPU","year":2011,"architecture":"Bobcat","process":"40 nm","aliases":["Amd embedded t30l"],"fields":[{"key":"Model name","value":"Embedded G-Series T30L","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"T30L","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GET30LGBB12GVE","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 1, 2011","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Embedded G-Series","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G-Series APU/CPU","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bobcat","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"eBrazos","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":20,"unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":451000000,"unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":75,"unit":"mm²","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 32 KiB","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 32 KiB","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1 × 512 KiB","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"8.53 GB/s","unit":"","sourceId":"chipswiki-424-r896","location":"Amd/embedded/t30l · revision 896 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft30l&oldid=896","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FT1","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":413,"unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.8-1.0 mm","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.92,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-3532bcb5c15853df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-424-r896","chipswiki-31122-r91589"],"url":"https://museum.vlsi.kr/objects/cw-3532bcb5c15853df"},{"id":"cw-353b71f0fc298aae","name":"Xeon Gold 6238M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6238m"],"fields":[{"key":"Model name","value":"Xeon Gold 6238M","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6238M","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":44,"unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.375,"unit":"MiB","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":704,"unit":"KiB","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":704,"unit":"KiB","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"22x1 MiB","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30.25,"unit":"MiB","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"22x1.375 MiB","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1485-r4935","location":"Intel/xeon gold/6238m · revision 4935 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-353b71f0fc298aae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1485-r4935"],"url":"https://museum.vlsi.kr/objects/cw-353b71f0fc298aae"},{"id":"cw-354027a4edf9e748","name":"Xeon Gold 6252N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6252n"],"fields":[{"key":"Model name","value":"Xeon Gold 6252N","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6252N","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1477-r4925","location":"Intel/xeon gold/6252n · revision 4925 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-354027a4edf9e748","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1477-r4925"],"url":"https://museum.vlsi.kr/objects/cw-354027a4edf9e748"},{"id":"cw-354aacefb34d0683","name":"Ryzen 5 PRO 5650U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 5 pro 5650u"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 5650U","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. 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Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5650U","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000290","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 16, 2021","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 16, 2021","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1800,"unit":"MHz","sourceId":"chipswiki-717-r1724","location":"Amd/ryzen 5/pro 5650u · revision 1724 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-354aacefb34d0683","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-717-r1724"],"url":"https://museum.vlsi.kr/objects/cw-354aacefb34d0683"},{"id":"cw-3568109049390d6f","name":"Celeron G3900","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel celeron g3900"],"fields":[{"key":"Model name","value":"Celeron G3900","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G3900","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80662G3900","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80662G3900","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2HV","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-8033-r25637","location":"Intel/celeron/g3900 · revision 25637 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3568109049390d6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8033-r25637","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-3568109049390d6f"},{"id":"cw-35b07c58acb0c1f4","name":"Mars I","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Phytium","year":2017,"process":"28 nm","aliases":["Phytium microarchitectures mars i"],"fields":[{"key":"Architecture name","value":"Mars I","unit":"","sourceId":"chipswiki-1667-r5833","location":"Phytium/microarchitectures/mars i · revision 5833 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. 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Not an independent measurement.","entityId":"cw-35b07c58acb0c1f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fmars%20i&oldid=5833","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1667-r5833","location":"Phytium/microarchitectures/mars i · revision 5833 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-35b07c58acb0c1f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fmars%20i&oldid=5833","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2017,"unit":"","sourceId":"chipswiki-1667-r5833","location":"Phytium/microarchitectures/mars i · revision 5833 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-35b07c58acb0c1f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fmars%20i&oldid=5833","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-1667-r5833","location":"Phytium/microarchitectures/mars i · revision 5833 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-35b07c58acb0c1f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fmars%20i&oldid=5833","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":64,"unit":"","sourceId":"chipswiki-1667-r5833","location":"Phytium/microarchitectures/mars i · revision 5833 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. 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Not an independent measurement.","entityId":"cw-35b07c58acb0c1f4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fmars%20i&oldid=5833","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Mars II","unit":"","sourceId":"chipswiki-1667-r5833","location":"Phytium/microarchitectures/mars i · revision 5833 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. 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Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-1630 v4","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002395300","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. 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Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-1000","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. 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Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2PF","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP Workstation","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. 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Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. 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Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-35ccbd0ec94856cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1630%20v4&oldid=24675","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7591-r24675","location":"Intel/xeon e5/e5-1630 v4 · revision 24675 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. 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Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 2018","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 2018","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"V1000","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":16,"unit":"W","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4 × 64 KiB","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4 × 32 KiB","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4 × 512 KiB","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1 × 4 MiB","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-931-r2556","location":"Amd/ryzen embedded/v1500b · revision 2556 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-361d2319c5f50a91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1500b&oldid=2556","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-931-r2556"],"url":"https://museum.vlsi.kr/objects/cw-361d2319c5f50a91"},{"id":"cw-362e8c45433701c9","name":"Core i3-8145U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":2018,"architecture":"Whiskey Lake","process":"14 nm","aliases":["Intel core i3 i3-8145u"],"fields":[{"key":"Model name","value":"Core i3-8145U","unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8145U","unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8068404064702","unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRD1V","unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 28, 2018","unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. 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Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 620","unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-754-r1796","location":"Intel/core i3/i3-8145u · revision 1796 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-362e8c45433701c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8145u&oldid=1796","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-754-r1796"],"url":"https://museum.vlsi.kr/objects/cw-362e8c45433701c9"},{"id":"cw-363b9b586dd06738","name":"Atom C3538","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3538"],"fields":[{"key":"Model name","value":"Atom C3538","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3538","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502444301","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3L7","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":224,"unit":"KiB","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.82,"unit":"GiB/s","sourceId":"chipswiki-1075-r3109","location":"Intel/atom/c3538 · revision 3109 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","sourceDate":"2020-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-23. Not an independent measurement.","entityId":"cw-363b9b586dd06738","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1075-r3109","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-363b9b586dd06738"},{"id":"cw-364984ec3014723a","name":"80186/BUC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 80186-buc"],"fields":[{"key":"Model name","value":"80186/BUC","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"80186/BUC","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"80186/BUC","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"2 MT/s","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8658-r26857","location":"Amd/am186/80186-buc · revision 26857 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-364984ec3014723a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8658-r26857"],"url":"https://museum.vlsi.kr/objects/cw-364984ec3014723a"},{"id":"cw-36a849cb83cd2333","name":"QorIQ P1020","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":2009,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1020"],"fields":[{"key":"Model name","value":"QorIQ P1020","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1020","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 16, 2008","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2009,"unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":125,"unit":"°C","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8099-r25758","location":"Freescale/qoriq/p1020 · revision 25758 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1020&oldid=25758","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-II-689","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":689,"unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-36a849cb83cd2333","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8099-r25758","chipswiki-31374-r92168"],"url":"https://museum.vlsi.kr/objects/cw-36a849cb83cd2333"},{"id":"cw-36adc15c3cd2b321","name":"Xeon Gold 6209U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6209u"],"fields":[{"key":"Model name","value":"Xeon Gold 6209U","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6209U","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. 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Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. 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Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. 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Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. 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Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. 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Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. 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Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1586-r5292","location":"Intel/xeon gold/6209u · revision 5292 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-36adc15c3cd2b321","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6209u&oldid=5292","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1586-r5292"],"url":"https://museum.vlsi.kr/objects/cw-36adc15c3cd2b321"},{"id":"cw-36ff14f0d8782433","name":"Am186EMLV–20KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186EM","year":1997,"architecture":"80186","aliases":["Amd am186ex am186emlv–20kc\\w"],"fields":[{"key":"Model name","value":"Am186EMLV–20KC\\W","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EMLV–20KC\\W","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EMLV–20KC\\W","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14662-r44723","location":"Amd/am186ex/am186emlv–20kc\\w · revision 44723 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-36ff14f0d8782433","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14662-r44723"],"url":"https://museum.vlsi.kr/objects/cw-36ff14f0d8782433"},{"id":"cw-371769b2b44a4f23","name":"Raptor Lake","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2022,"process":"Intel 7","aliases":["Intel microarchitectures raptor lake"],"fields":[{"key":"Architecture name","value":"Raptor Lake","unit":"","sourceId":"chipswiki-35-r96973","location":"Intel/microarchitectures/raptor lake · revision 96973 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-02. Not an independent measurement.","entityId":"cw-371769b2b44a4f23","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fraptor%20lake&oldid=96973","sourceDate":"2022-11-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-35-r96973","location":"Intel/microarchitectures/raptor lake · revision 96973 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-02. Not an independent measurement.","entityId":"cw-371769b2b44a4f23","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fraptor%20lake&oldid=96973","sourceDate":"2022-11-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-35-r96973","location":"Intel/microarchitectures/raptor lake · revision 96973 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-02. Not an independent measurement.","entityId":"cw-371769b2b44a4f23","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fraptor%20lake&oldid=96973","sourceDate":"2022-11-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"September 27, 2022","unit":"","sourceId":"chipswiki-35-r96973","location":"Intel/microarchitectures/raptor lake · revision 96973 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-02. Not an independent measurement.","entityId":"cw-371769b2b44a4f23","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fraptor%20lake&oldid=96973","sourceDate":"2022-11-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"Intel 7","unit":"","sourceId":"chipswiki-35-r96973","location":"Intel/microarchitectures/raptor lake · revision 96973 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-02. Not an independent measurement.","entityId":"cw-371769b2b44a4f23","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fraptor%20lake&oldid=96973","sourceDate":"2022-11-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":24,"unit":"","sourceId":"chipswiki-35-r96973","location":"Intel/microarchitectures/raptor lake · revision 96973 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-02. Not an independent measurement.","entityId":"cw-371769b2b44a4f23","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fraptor%20lake&oldid=96973","sourceDate":"2022-11-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-35-r96973","location":"Intel/microarchitectures/raptor lake · revision 96973 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-02. Not an independent measurement.","entityId":"cw-371769b2b44a4f23","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fraptor%20lake&oldid=96973","sourceDate":"2022-11-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-35-r96973","location":"Intel/microarchitectures/raptor lake · revision 96973 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cluster","note":"Source-reported parameter; source revision 2022-11-02. Not an independent measurement.","entityId":"cw-371769b2b44a4f23","scope":"Cluster","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fraptor%20lake&oldid=96973","sourceDate":"2022-11-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Alder Lake","unit":"","sourceId":"chipswiki-35-r96973","location":"Intel/microarchitectures/raptor lake · revision 96973 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-02. Not an independent measurement.","entityId":"cw-371769b2b44a4f23","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fraptor%20lake&oldid=96973","sourceDate":"2022-11-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Meteor Lake","unit":"","sourceId":"chipswiki-35-r96973","location":"Intel/microarchitectures/raptor lake · revision 96973 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-02. Not an independent measurement.","entityId":"cw-371769b2b44a4f23","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fraptor%20lake&oldid=96973","sourceDate":"2022-11-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-35-r96973"],"url":"https://museum.vlsi.kr/objects/cw-371769b2b44a4f23"},{"id":"cw-373393a2f32bbcce","name":"EPYC 7452","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7452"],"fields":[{"key":"Model name","value":"EPYC 7452","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7452,"unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000057","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000057WOF","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2350,"unit":"MHz","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3350,"unit":"MHz","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x512 KiB","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x16 MiB","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-680-r1668","location":"Amd/epyc/7452 · revision 1668 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-09. Not an independent measurement.","entityId":"cw-373393a2f32bbcce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","sourceDate":"2021-06-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-680-r1668"],"url":"https://museum.vlsi.kr/objects/cw-373393a2f32bbcce"},{"id":"cw-3770753b0ffe23a7","name":"Poseidon","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2021,"process":"5 nm","aliases":["Arm holdings microarchitectures poseidon"],"fields":[{"key":"Architecture name","value":"Poseidon","unit":"","sourceId":"chipswiki-1854-r6316","location":"Arm holdings/microarchitectures/poseidon · revision 6316 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-29. Not an independent measurement.","entityId":"cw-3770753b0ffe23a7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fposeidon&oldid=6316","sourceDate":"2019-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-1854-r6316","location":"Arm holdings/microarchitectures/poseidon · revision 6316 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-29. Not an independent measurement.","entityId":"cw-3770753b0ffe23a7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fposeidon&oldid=6316","sourceDate":"2019-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1854-r6316","location":"Arm holdings/microarchitectures/poseidon · revision 6316 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-29. Not an independent measurement.","entityId":"cw-3770753b0ffe23a7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fposeidon&oldid=6316","sourceDate":"2019-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2021,"unit":"","sourceId":"chipswiki-1854-r6316","location":"Arm holdings/microarchitectures/poseidon · revision 6316 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-29. Not an independent measurement.","entityId":"cw-3770753b0ffe23a7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fposeidon&oldid=6316","sourceDate":"2019-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":5,"unit":"nm","sourceId":"chipswiki-1854-r6316","location":"Arm holdings/microarchitectures/poseidon · revision 6316 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-29. Not an independent measurement.","entityId":"cw-3770753b0ffe23a7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fposeidon&oldid=6316","sourceDate":"2019-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Zeus","unit":"","sourceId":"chipswiki-1854-r6316","location":"Arm holdings/microarchitectures/poseidon · revision 6316 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-29. Not an independent measurement.","entityId":"cw-3770753b0ffe23a7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fposeidon&oldid=6316","sourceDate":"2019-08-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1854-r6316"],"url":"https://museum.vlsi.kr/objects/cw-3770753b0ffe23a7"},{"id":"cw-37831831ef3e43cc","name":"R-Car M2","kind":"sku","entityType":"product-model","subtype":"soc","company":"Renesas","series":"2nd Gen","year":2015,"architecture":"Cortex-A15","process":"28 nm","aliases":["Renesas r-car m2"],"fields":[{"key":"Model name","value":"R-Car M2","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"M2","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"R8A7791","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 26, 2013","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2015","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"2nd Gen","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A15","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A15","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SH-4A","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":3,"unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":3,"unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.03,"unit":"V","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":96,"unit":"KiB","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"3x32 KiB","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"3x32 KiB","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX544","unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":520,"unit":"MHz","sourceId":"chipswiki-7645-r24905","location":"Renesas/r-car/m2 · revision 24905 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fm2&oldid=24905","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-831","unit":"","sourceId":"chipswiki-31425-r92293","location":"Template:Packages/renesas/fcbga-831 · revision 92293 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31425-r92293","location":"Template:Packages/renesas/fcbga-831 · revision 92293 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":831,"unit":"","sourceId":"chipswiki-31425-r92293","location":"Template:Packages/renesas/fcbga-831 · revision 92293 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31425-r92293","location":"Template:Packages/renesas/fcbga-831 · revision 92293 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":27,"unit":"mm","sourceId":"chipswiki-31425-r92293","location":"Template:Packages/renesas/fcbga-831 · revision 92293 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":27,"unit":"mm","sourceId":"chipswiki-31425-r92293","location":"Template:Packages/renesas/fcbga-831 · revision 92293 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37831831ef3e43cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-831&oldid=92293","sourceDate":"2017-07-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7645-r24905","chipswiki-31425-r92293"],"url":"https://museum.vlsi.kr/objects/cw-37831831ef3e43cc"},{"id":"cw-378562a0d6a69e6a","name":"ARM250","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":1992,"process":"1 µm","aliases":["Arm holdings microarchitectures arm250"],"fields":[{"key":"Architecture name","value":"ARM250","unit":"","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":1992,"unit":"","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Scalar","unit":"","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":3,"unit":"","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"1-way","unit":"","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv2a","unit":"","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM250","unit":"","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"ARM3","unit":"","sourceId":"chipswiki-13387-r40185","location":"Arm holdings/microarchitectures/arm250 · revision 40185 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-10. Not an independent measurement.","entityId":"cw-378562a0d6a69e6a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","sourceDate":"2017-07-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-13387-r40185"],"url":"https://museum.vlsi.kr/objects/cw-378562a0d6a69e6a"},{"id":"cw-379986f50d98c7ef","name":"P8086","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 p8086"],"fields":[{"key":"Model name","value":"AMD P8086","unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P8086","unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"P8086","unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":5,"unit":"MHz","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PDIP-40","unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PDIP","unit":"","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8496-r26689","location":"Amd/am8086/p8086 · revision 26689 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-379986f50d98c7ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086&oldid=26689","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8496-r26689"],"url":"https://museum.vlsi.kr/objects/cw-379986f50d98c7ef"},{"id":"cw-37a3d07bd1d56310","name":"Am186CU-25KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CU","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186cu-25kc\\w"],"fields":[{"key":"Model name","value":"Am186CU-25KC\\W","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CU-25KC\\W","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CU-25KC\\W","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CU","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14681-r44742","location":"Amd/am186cx/am186cu-25kc\\w · revision 44742 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-37a3d07bd1d56310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14681-r44742"],"url":"https://museum.vlsi.kr/objects/cw-37a3d07bd1d56310"},{"id":"cw-37a45504bcb1e959","name":"Xeon Gold 6242","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6242"],"fields":[{"key":"Model name","value":"Xeon Gold 6242","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6242,"unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504194101","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806956242","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF8Y","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1482-r4930","location":"Intel/xeon gold/6242 · revision 4930 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-37a45504bcb1e959","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6242&oldid=4930","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1482-r4930"],"url":"https://museum.vlsi.kr/objects/cw-37a45504bcb1e959"},{"id":"cw-37c0b92308d47a66","name":"Core i5-2515E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2515e"],"fields":[{"key":"Model name","value":"Core i5-2515E","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2515E","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700853208","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR075","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37c0b92308d47a66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2515e&oldid=25501","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7953-r25501","location":"Intel/core i5/i5-2515e · revision 25501 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37c4504c59591270","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbd&oldid=963","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1500-400MBD","unit":"","sourceId":"chipswiki-479-r963","location":"Alchemy/au1500-400mbd · revision 963 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-37c4504c59591270","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbd&oldid=963","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 11, 2001","unit":"","sourceId":"chipswiki-479-r963","location":"Alchemy/au1500-400mbd · revision 963 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-37c4504c59591270","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbd&oldid=963","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-479-r963","location":"Alchemy/au1500-400mbd · revision 963 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-37c4504c59591270","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbd&oldid=963","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-479-r963","location":"Alchemy/au1500-400mbd · revision 963 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-37c4504c59591270","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbd&oldid=963","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-479-r963","location":"Alchemy/au1500-400mbd · revision 963 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-37da2fea2d86c8f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1537&oldid=11450","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3741-r11450","location":"Intel/xeon d/d-1537 · revision 11450 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-37da2fea2d86c8f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1537&oldid=11450","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3741-r11450","location":"Intel/xeon d/d-1537 · revision 11450 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-37da2fea2d86c8f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1537&oldid=11450","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3741-r11450","location":"Intel/xeon d/d-1537 · revision 11450 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-37da2fea2d86c8f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1537&oldid=11450","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3741-r11450","location":"Intel/xeon d/d-1537 · revision 11450 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-37da2fea2d86c8f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1537&oldid=11450","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3741-r11450","location":"Intel/xeon d/d-1537 · revision 11450 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-37da2fea2d86c8f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1537&oldid=11450","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-3741-r11450","location":"Intel/xeon d/d-1537 · revision 11450 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-37da2fea2d86c8f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1537&oldid=11450","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3741-r11450","location":"Intel/xeon d/d-1537 · revision 11450 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-37da2fea2d86c8f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1537&oldid=11450","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3741-r11450","location":"Intel/xeon d/d-1537 · revision 11450 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-37da2fea2d86c8f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1537&oldid=11450","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-3741-r11450","location":"Intel/xeon d/d-1537 · revision 11450 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-37da2fea2d86c8f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1537&oldid=11450","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3741-r11450","location":"Intel/xeon d/d-1537 · revision 11450 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR18G","unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Shark Bay","unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":46,"unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7864-r25366","location":"Intel/core i7/i7-4950hq · revision 25366 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4950hq&oldid=25366","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37df6820d862abe2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. 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Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 16, 2019","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4800,"unit":"MHz","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-01. 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Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Whiskey Lake","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Whiskey Lake U","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-05-01. 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Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 620","unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-2926-r9784","location":"Intel/core i7/i7-8665u · revision 9784 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-37e84d177a05e495","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8665u&oldid=9784","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2926-r9784"],"url":"https://museum.vlsi.kr/objects/cw-37e84d177a05e495"},{"id":"cw-3823962c1db1cdce","name":"Xeon Silver 4116","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon silver 4116"],"fields":[{"key":"Model name","value":"Xeon Silver 4116","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4116,"unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806734116","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303567200","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3HQ","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1447-r4887","location":"Intel/xeon silver/4116 · revision 4887 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3823962c1db1cdce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116&oldid=4887","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1447-r4887"],"url":"https://museum.vlsi.kr/objects/cw-3823962c1db1cdce"},{"id":"cw-382b4f52225fef89","name":"EPYC 7543","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7543"],"fields":[{"key":"Model name","value":"EPYC 7543","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7543,"unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000345","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000319WOF","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":225,"unit":"W","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32 × 512 KiB","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 32 MiB","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-735-r1756","location":"Amd/epyc/7543 · revision 1756 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-382b4f52225fef89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-735-r1756"],"url":"https://museum.vlsi.kr/objects/cw-382b4f52225fef89"},{"id":"cw-384916bbe3f62eec","name":"Xeon D-1529","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1529"],"fields":[{"key":"Model name","value":"Xeon D-1529","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1529","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402570001","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DR","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 2016","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 2016","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"V2","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":20,"unit":"W","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1600","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-3728-r11428","location":"Intel/xeon d/d-1529 · revision 11428 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-384916bbe3f62eec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3728-r11428"],"url":"https://museum.vlsi.kr/objects/cw-384916bbe3f62eec"},{"id":"cw-38651d1266e62895","name":"SpiNNaker - APT","kind":"sku","entityType":"product-model","subtype":"cpu","company":"APT Advanced Processor Technologies Research Group","year":2011,"architecture":"ARM968","aliases":["University of manchester spinnaker"],"fields":[{"key":"Model name","value":"SpiNNaker multicore SoC","unit":"","sourceId":"chipswiki-6266-r19330","location":"University of manchester/spinnaker · revision 19330 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-19. 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Not an independent measurement.","entityId":"cw-38651d1266e62895","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=University%20of%20manchester%2Fspinnaker&oldid=19330","sourceDate":"2018-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Artificial Intelligence","unit":"","sourceId":"chipswiki-6266-r19330","location":"University of manchester/spinnaker · revision 19330 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-19. Not an independent measurement.","entityId":"cw-38651d1266e62895","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=University%20of%20manchester%2Fspinnaker&oldid=19330","sourceDate":"2018-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"20th May, 2011","unit":"","sourceId":"chipswiki-6266-r19330","location":"University of manchester/spinnaker · revision 19330 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-19. Not an independent measurement.","entityId":"cw-38651d1266e62895","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=University%20of%20manchester%2Fspinnaker&oldid=19330","sourceDate":"2018-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":200,"unit":"MHz","sourceId":"chipswiki-6266-r19330","location":"University of manchester/spinnaker · revision 19330 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-19. Not an independent measurement.","entityId":"cw-38651d1266e62895","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=University%20of%20manchester%2Fspinnaker&oldid=19330","sourceDate":"2018-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARM9","unit":"","sourceId":"chipswiki-6266-r19330","location":"University of manchester/spinnaker · revision 19330 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-19. Not an independent measurement.","entityId":"cw-38651d1266e62895","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=University%20of%20manchester%2Fspinnaker&oldid=19330","sourceDate":"2018-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM968","unit":"","sourceId":"chipswiki-6266-r19330","location":"University of manchester/spinnaker · revision 19330 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-19. Not an independent measurement.","entityId":"cw-38651d1266e62895","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=University%20of%20manchester%2Fspinnaker&oldid=19330","sourceDate":"2018-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":102,"unit":"mm²","sourceId":"chipswiki-6266-r19330","location":"University of manchester/spinnaker · revision 19330 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-19. Not an independent measurement.","entityId":"cw-38651d1266e62895","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=University%20of%20manchester%2Fspinnaker&oldid=19330","sourceDate":"2018-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-6266-r19330","location":"University of manchester/spinnaker · revision 19330 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-19. 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Not an independent measurement.","entityId":"cw-38651d1266e62895","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=University%20of%20manchester%2Fspinnaker&oldid=19330","sourceDate":"2018-05-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"128MB (chip), 7TB (system)","unit":"","sourceId":"chipswiki-6266-r19330","location":"University of manchester/spinnaker · revision 19330 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-19. Not an independent measurement.","entityId":"cw-38651d1266e62895","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=University%20of%20manchester%2Fspinnaker&oldid=19330","sourceDate":"2018-05-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6266-r19330"],"url":"https://museum.vlsi.kr/objects/cw-38651d1266e62895"},{"id":"cw-3875d6701a9bc79f","name":"Am486SX-40","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486SX","year":1993,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486sx-40"],"fields":[{"key":"Model name","value":"Am486SX-40","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 1992","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486SX","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"40 MT/s","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SX","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":900000,"unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8538-r26734","location":"Amd/am486/am486sx-40 · revision 26734 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3875d6701a9bc79f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8538-r26734"],"url":"https://museum.vlsi.kr/objects/cw-3875d6701a9bc79f"},{"id":"cw-38b0bbd66b035eec","name":"Colossus","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Graphcore","year":2018,"process":"16 nm","aliases":["Graphcore microarchitectures colossus"],"fields":[{"key":"Architecture name","value":"Colossus","unit":"","sourceId":"chipswiki-5566-r18059","location":"Graphcore/microarchitectures/colossus · revision 18059 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-24. Not an independent measurement.","entityId":"cw-38b0bbd66b035eec","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Graphcore%2Fmicroarchitectures%2Fcolossus&oldid=18059","sourceDate":"2018-06-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Graphcore","unit":"","sourceId":"chipswiki-5566-r18059","location":"Graphcore/microarchitectures/colossus · revision 18059 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-24. Not an independent measurement.","entityId":"cw-38b0bbd66b035eec","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Graphcore%2Fmicroarchitectures%2Fcolossus&oldid=18059","sourceDate":"2018-06-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-5566-r18059","location":"Graphcore/microarchitectures/colossus · revision 18059 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-24. Not an independent measurement.","entityId":"cw-38b0bbd66b035eec","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Graphcore%2Fmicroarchitectures%2Fcolossus&oldid=18059","sourceDate":"2018-06-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2018,"unit":"","sourceId":"chipswiki-5566-r18059","location":"Graphcore/microarchitectures/colossus · revision 18059 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-24. Not an independent measurement.","entityId":"cw-38b0bbd66b035eec","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Graphcore%2Fmicroarchitectures%2Fcolossus&oldid=18059","sourceDate":"2018-06-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-5566-r18059","location":"Graphcore/microarchitectures/colossus · revision 18059 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-24. Not an independent measurement.","entityId":"cw-38b0bbd66b035eec","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Graphcore%2Fmicroarchitectures%2Fcolossus&oldid=18059","sourceDate":"2018-06-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5566-r18059"],"url":"https://museum.vlsi.kr/objects/cw-38b0bbd66b035eec"},{"id":"cw-38b8476f39d129f1","name":"AM9080ADI","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080adi"],"fields":[{"key":"Model name","value":"AMD AM9080ADI","unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080ADI","unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080ADI","unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Industrial","unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.083,"unit":"MHz","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8467-r26660","location":"Amd/am9080/am9080adi · revision 26660 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38b8476f39d129f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8467-r26660"],"url":"https://museum.vlsi.kr/objects/cw-38b8476f39d129f1"},{"id":"cw-38c130a7dc3cc684","name":"Core i7-8706G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":2018,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-8706g"],"fields":[{"key":"Model name","value":"Core i7-8706G","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8706G","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2018","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2018","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake G","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 1)","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","alternatives":[{"value":"DDR4-2400","sourceId":"chipswiki-5288-r17294","reason":"Intel/core i7/i7-8706g · revision 17294 · {{memory controller}} / type 2. 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Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 1)","value":64,"unit":"GiB","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 1)","value":1,"unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 1)","value":2,"unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 1)","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller / HBM 2 (section 2)","value":"HBM2","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Memory controller / HBM 2 (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller / HBM 2 (section 2)","value":4,"unit":"GiB","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Memory controller / HBM 2 (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller / HBM 2 (section 2)","value":166.9,"unit":"GiB/s","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Memory controller / HBM 2 (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model — Graphics / Integrated graphics (section 1)","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units — Graphics / Integrated graphics (section 1)","value":24,"unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count — Graphics / Integrated graphics (section 1)","value":3,"unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock — Graphics / Integrated graphics (section 1)","value":350,"unit":"MHz","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock — Graphics / Integrated graphics (section 1)","value":1100,"unit":"MHz","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model — Graphics / Discrete graphics (section 2)","value":"Radeon RX Vega M GL","unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units — Graphics / Discrete graphics (section 2)","value":20,"unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock — Graphics / Discrete graphics (section 2)","value":931,"unit":"MHz","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock — Graphics / Discrete graphics (section 2)","value":1011,"unit":"MHz","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count — Graphics / Discrete graphics (section 2)","value":6,"unit":"","sourceId":"chipswiki-5288-r17294","location":"Intel/core i7/i7-8706g · revision 17294 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-38c130a7dc3cc684","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8706g&oldid=17294","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5288-r17294"],"url":"https://museum.vlsi.kr/objects/cw-38c130a7dc3cc684"},{"id":"cw-38e1a65ffce5bc4d","name":"Celeron N3450","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N Series","year":2016,"architecture":"Goldmont","process":"14 nm","aliases":["Intel celeron n3450"],"fields":[{"key":"Model name","value":"Celeron N3450","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N3450","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066802979803","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066802979803","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N Series","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2YA","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2Z6","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Apollo Lake","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-1296","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1296","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-1856-r6338","location":"Intel/celeron/n3450 · revision 6338 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-26. Not an independent measurement.","entityId":"cw-38e1a65ffce5bc4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3450&oldid=6338","sourceDate":"2019-08-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1856-r6338"],"url":"https://museum.vlsi.kr/objects/cw-38e1a65ffce5bc4d"},{"id":"cw-38fd623709ace730","name":"Am186ESLV–25VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ES","year":1997,"architecture":"80186","aliases":["Amd am186ex am186eslv–25vc\\w"],"fields":[{"key":"Model name","value":"Am186ESLV–25VC\\W","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ESLV–25VC\\W","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ESLV–25VC\\W","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14628-r44689","location":"Amd/am186ex/am186eslv–25vc\\w · revision 44689 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-38fd623709ace730","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14628-r44689"],"url":"https://museum.vlsi.kr/objects/cw-38fd623709ace730"},{"id":"cw-38fd7ba1bedc68a4","name":"Am2012","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Ambric","series":"Gen 1","year":2007,"architecture":"Ambric","process":"130 nm","aliases":["Ambric am2000 am2012"],"fields":[{"key":"Model name","value":"Am2012","unit":"","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Ambric","unit":"","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am2012","unit":"","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am2012","unit":"","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 10, 2006","unit":"","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2007","unit":"","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am2000","unit":"","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Gen 1","unit":"","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ambric","unit":"","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":96,"unit":"","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8668-r26867","location":"Ambric/am2000/am2012 · revision 26867 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-38fd7ba1bedc68a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8668-r26867"],"url":"https://museum.vlsi.kr/objects/cw-38fd7ba1bedc68a4"},{"id":"cw-39292e0fde440656","name":"Alchemy Au1200-333MGI","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2005,"architecture":"Au1","aliases":["Alchemy au1200-333mgi"],"fields":[{"key":"Model name","value":"Alchemy Au1200-333MGI","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1200-333MGI","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1200-333MGI","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2005","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2005","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1500 mW","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.332 GB/s","unit":"","sourceId":"chipswiki-455-r936","location":"Alchemy/au1200-333mgi · revision 936 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-39292e0fde440656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgi&oldid=936","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-455-r936"],"url":"https://museum.vlsi.kr/objects/cw-39292e0fde440656"},{"id":"cw-394671e801d5e031","name":"Xeon E3-1515M v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1500 v5","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1515m v5"],"fields":[{"key":"Model name","value":"Xeon E3-1515M v5","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1515M v5","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"JQ8066202193208","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2QT","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500 v5","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"N0","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Pro Graphics P580","unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":72,"unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7759-r25142","location":"Intel/xeon e3/e3-1515m v5 · revision 25142 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1515m%20v5&oldid=25142","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-394671e801d5e031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7759-r25142","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-394671e801d5e031"},{"id":"cw-3975b2792450a7d2","name":"Xeon E7-4860","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-4800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-4860"],"fields":[{"key":"Model name","value":"Xeon E7-4860","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615007254AA","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-4800","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2666.66,"unit":"MHz","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.56,"unit":"MiB","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24,"unit":"MiB","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x2.4 MiB","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.77,"unit":"GiB/s","sourceId":"chipswiki-7698-r25068","location":"Intel/xeon e7/e7-4860 · revision 25068 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4860&oldid=25068","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-8","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1567,"unit":"","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.1,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":56.4,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.2,"unit":"mm","sourceId":"chipswiki-31576-r92962","location":"Template:Packages/intel/lga-1567 · revision 92962 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3975b2792450a7d2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7698-r25068","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-3975b2792450a7d2"},{"id":"cw-398f2df5bc516f04","name":"ThunderX2 CN9978","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","year":2018,"architecture":"Vulcan","process":"16 nm","aliases":["Cavium thunderx2 cn9978"],"fields":[{"key":"Model name","value":"ThunderX2 CN9978","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN9978","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9978-2300LG4077-Y21-G","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9978-2200LG4077-Y21-G","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9978-2100LG4077-Y21-G","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9978-2000LG4077-Y21-G","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9978-1800LG4077-Y21-G","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 7, 2018","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 7, 2018","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"ThunderX2","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":2100,"unit":"MHz","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 4","value":2200,"unit":"MHz","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / frequency 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 4","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"Multiple clock domains; raw parameter frequency 4","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 5","value":2300,"unit":"MHz","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / frequency 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 5","note":"Source-reported parameter; source revision 2018-12-04. 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Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Vulcan","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":30,"unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":120,"unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.87,"unit":"MiB","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":960,"unit":"KiB","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"30x32 KiB","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":960,"unit":"KiB","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"30x32 KiB","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":7.5,"unit":"MiB","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"30x256 KiB","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30,"unit":"MiB","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"30x1 MiB","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-4332-r13944","location":"Cavium/thunderx2/cn9978 · revision 13944 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-398f2df5bc516f04","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9978&oldid=13944","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4332-r13944"],"url":"https://museum.vlsi.kr/objects/cw-398f2df5bc516f04"},{"id":"cw-39a49c08c466353f","name":"Ryzen 3 PRO 4350G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 3 pro 4350g"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 4350G","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 4350G","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000148","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000148MPK","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 21, 2020","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1700,"unit":"MHz","sourceId":"chipswiki-698-r1694","location":"Amd/ryzen 3/pro 4350g · revision 1694 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-39a49c08c466353f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350g&oldid=1694","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-698-r1694"],"url":"https://museum.vlsi.kr/objects/cw-39a49c08c466353f"},{"id":"cw-39c64378ba93db2b","name":"EyeQ2","kind":"sku","entityType":"product-model","subtype":"sku","company":"Mobileye","year":2010,"process":"90 nm","aliases":["Mobileye eyeq eyeq2"],"fields":[{"key":"Model name","value":"EyeQ2","unit":"","sourceId":"chipswiki-2936-r9826","location":"Mobileye/eyeq/eyeq2 · revision 9826 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-39c64378ba93db2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq2&oldid=9826","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Mobileye","unit":"","sourceId":"chipswiki-2936-r9826","location":"Mobileye/eyeq/eyeq2 · revision 9826 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-39c64378ba93db2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq2&oldid=9826","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"STMicroelectronics","unit":"","sourceId":"chipswiki-2936-r9826","location":"Mobileye/eyeq/eyeq2 · revision 9826 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-39c64378ba93db2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq2&oldid=9826","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Automotive","unit":"","sourceId":"chipswiki-2936-r9826","location":"Mobileye/eyeq/eyeq2 · revision 9826 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-39c64378ba93db2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq2&oldid=9826","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 07, 2007","unit":"","sourceId":"chipswiki-2936-r9826","location":"Mobileye/eyeq/eyeq2 · revision 9826 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-39c64378ba93db2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq2&oldid=9826","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2010,"unit":"","sourceId":"chipswiki-2936-r9826","location":"Mobileye/eyeq/eyeq2 · revision 9826 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-39c64378ba93db2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq2&oldid=9826","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EyeQ","unit":"","sourceId":"chipswiki-2936-r9826","location":"Mobileye/eyeq/eyeq2 · revision 9826 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-39c64378ba93db2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq2&oldid=9826","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-2936-r9826","location":"Mobileye/eyeq/eyeq2 · revision 9826 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-39c64378ba93db2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq2&oldid=9826","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2936-r9826","location":"Mobileye/eyeq/eyeq2 · revision 9826 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-39c64378ba93db2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq2&oldid=9826","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2.5,"unit":"W","sourceId":"chipswiki-2936-r9826","location":"Mobileye/eyeq/eyeq2 · revision 9826 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-39c64378ba93db2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq2&oldid=9826","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2936-r9826"],"url":"https://museum.vlsi.kr/objects/cw-39c64378ba93db2b"},{"id":"cw-39da1a342d512f78","name":"Montvale","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2007,"process":"90 nm","aliases":["Intel microarchitectures montvale"],"fields":[{"key":"Architecture name","value":"Montvale","unit":"","sourceId":"chipswiki-8763-r27225","location":"Intel/microarchitectures/montvale · revision 27225 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-39da1a342d512f78","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmontvale&oldid=27225","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8763-r27225","location":"Intel/microarchitectures/montvale · revision 27225 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-39da1a342d512f78","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmontvale&oldid=27225","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8763-r27225","location":"Intel/microarchitectures/montvale · revision 27225 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-39da1a342d512f78","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmontvale&oldid=27225","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October 31, 2007","unit":"","sourceId":"chipswiki-8763-r27225","location":"Intel/microarchitectures/montvale · revision 27225 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-39da1a342d512f78","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmontvale&oldid=27225","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8763-r27225","location":"Intel/microarchitectures/montvale · revision 27225 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-39da1a342d512f78","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmontvale&oldid=27225","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-8763-r27225","location":"Intel/microarchitectures/montvale · revision 27225 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-39da1a342d512f78","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmontvale&oldid=27225","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"IA-64","unit":"","sourceId":"chipswiki-8763-r27225","location":"Intel/microarchitectures/montvale · revision 27225 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-39da1a342d512f78","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmontvale&oldid=27225","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Montecito","unit":"","sourceId":"chipswiki-8763-r27225","location":"Intel/microarchitectures/montvale · revision 27225 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-39da1a342d512f78","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmontvale&oldid=27225","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Tukwila","unit":"","sourceId":"chipswiki-8763-r27225","location":"Intel/microarchitectures/montvale · revision 27225 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-39da1a342d512f78","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmontvale&oldid=27225","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8763-r27225"],"url":"https://museum.vlsi.kr/objects/cw-39da1a342d512f78"},{"id":"cw-3a1186c1df4aee83","name":"C80286-10","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"C80286","year":1984,"architecture":"80286","process":"1.5 µm","aliases":["Amd am286 c80286-10"],"fields":[{"key":"Model name","value":"C80286-10","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C80286-10","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"C80286","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":134000,"unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73,"unit":"mm²","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8606-r26804","location":"Amd/am286/c80286-10 · revision 26804 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a1186c1df4aee83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8606-r26804"],"url":"https://museum.vlsi.kr/objects/cw-3a1186c1df4aee83"},{"id":"cw-3a19246f3c6df272","name":"Mobile Pentium II 233","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":1998,"architecture":"P6","process":"250 nm","aliases":["Intel mobile pentium ii 233"],"fields":[{"key":"Model name","value":"Mobile Pentium II 233","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":233,"unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"80523TX233512","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PMD23305001AA","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PMD23305002AB","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PME23305001AA","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1997","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 1998","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Mobile Pentium II","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":233,"unit":"MHz","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL2KH","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL2RQ","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL2U8","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"P6","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Tonga","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":5,"unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdA0","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdB0","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdA0","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7500000,"unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9,"unit":"W","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"240-pin connector","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a19246f3c6df272","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7808-r25247","location":"Intel/mobile pentium ii/233 · revision 25247 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3005-300BG350-SCP","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3000","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1,017 MiB/s","unit":"","sourceId":"chipswiki-8280-r25940","location":"Cavium/octeon/cn3005-300bg350-scp · revision 25940 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a456e03ee789ac5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-300bg350-scp&oldid=25940","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8280-r25940"],"url":"https://museum.vlsi.kr/objects/cw-3a456e03ee789ac5"},{"id":"cw-3a8de65e92e8375a","name":"Atom Z540","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z500","year":2008,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z540"],"fields":[{"key":"Model name","value":"Atom Z540","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z540","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AC80566UE036DW","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLB2M","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z500","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1866.66,"unit":"MHz","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"533.33 MT/s","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Menlow","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Poulsbo","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":28,"unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":24.18,"unit":"mm²","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2.4,"unit":"W","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8062-r25698","location":"Intel/atom/z540 · revision 25698 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-441","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3a8de65e92e8375a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8062-r25698","chipswiki-31513-r92656"],"url":"https://museum.vlsi.kr/objects/cw-3a8de65e92e8375a"},{"id":"cw-3a9e7ed307611f31","name":"Xeon W-2175","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-2000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon w w-2175"],"fields":[{"key":"Model name","value":"Xeon W-2175","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2175","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303842300","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3W2","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":896,"unit":"KiB","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":14,"unit":"MiB","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x1 MiB","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-2528-r8677","location":"Intel/xeon w/w-2175 · revision 8677 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3a9e7ed307611f31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2175&oldid=8677","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2528-r8677"],"url":"https://museum.vlsi.kr/objects/cw-3a9e7ed307611f31"},{"id":"cw-3aa6b127b18317ea","name":"Xeon Silver 4214","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon silver 4214"],"fields":[{"key":"Model name","value":"Xeon Silver 4214","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4214,"unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504212601","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806954214","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFB9","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4200,"unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L0","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L1","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1445-r4885","location":"Intel/xeon silver/4214 · revision 4885 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3aa6b127b18317ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4214&oldid=4885","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1445-r4885"],"url":"https://museum.vlsi.kr/objects/cw-3aa6b127b18317ea"},{"id":"cw-3afa8556d42fb3ec","name":"IG80186-6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 ig80186-6"],"fields":[{"key":"Model name","value":"IG80186-6","unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"IG80186-6","unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"IG80186-6","unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"IG80186-6B","unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":6,"unit":"MHz","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"1.5 MT/s","unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3afa8556d42fb3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8645-r26844","location":"Amd/am186/ig80186-6 · revision 26844 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":6,"unit":"MHz","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"1.5 MT/s","unit":"","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8659-r26858","location":"Amd/am186/80186-6-bzc · revision 26858 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3b4ed67be3e3e92f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8659-r26858"],"url":"https://museum.vlsi.kr/objects/cw-3b4ed67be3e3e92f"},{"id":"cw-3b845fbd1f5dc831","name":"K6-2+/550ACZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Mobile","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2+-550acz"],"fields":[{"key":"Model name","value":"K6-2+/550ACZ","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2+/550ACZ","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2+/550ACZ","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":550,"unit":"MHz","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 5, 2000","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Mobile","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-997-r2843","location":"Amd/k6-2+/k6-2+-550acz · revision 2843 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-550acz&oldid=2843","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":321,"unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":2.54,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.3,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super Socket 7","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-3b845fbd1f5dc831","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-997-r2843","chipswiki-31126-r91598"],"url":"https://museum.vlsi.kr/objects/cw-3b845fbd1f5dc831"},{"id":"cw-3ba04ed8b6d9a804","name":"Am186EMLV–25KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186EM","year":1997,"architecture":"80186","aliases":["Amd am186ex am186emlv–25kc\\w"],"fields":[{"key":"Model name","value":"Am186EMLV–25KC\\W","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EMLV–25KC\\W","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EMLV–25KC\\W","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14660-r44721","location":"Amd/am186ex/am186emlv–25kc\\w · revision 44721 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3ba04ed8b6d9a804","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14660-r44721"],"url":"https://museum.vlsi.kr/objects/cw-3ba04ed8b6d9a804"},{"id":"cw-3bbb70edbc45d6c9","name":"Xeon Platinum 8253","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8253"],"fields":[{"key":"Model name","value":"Xeon Platinum 8253","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8253,"unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504194601","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF93","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1465-r4912","location":"Intel/xeon platinum/8253 · revision 4912 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3bbb70edbc45d6c9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8253&oldid=4912","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1465-r4912"],"url":"https://museum.vlsi.kr/objects/cw-3bbb70edbc45d6c9"},{"id":"cw-3bd5f13c25c8e5f2","name":"Ryzen 7 3750H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 7 3750h"],"fields":[{"key":"Model name","value":"Ryzen 7 3750H","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3750H","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM3700C4T4MFG","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","alternatives":[{"value":"32 GiB","sourceId":"chipswiki-781-r1919","reason":"Amd/ryzen 7/3750h · revision 1919 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 10","unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":10,"unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1400,"unit":"MHz","sourceId":"chipswiki-781-r1919","location":"Amd/ryzen 7/3750h · revision 1919 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-26. Not an independent measurement.","entityId":"cw-3bd5f13c25c8e5f2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3750h&oldid=1919","sourceDate":"2021-04-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-781-r1919"],"url":"https://museum.vlsi.kr/objects/cw-3bd5f13c25c8e5f2"},{"id":"cw-3bdfdb0671f47b6d","name":"Ryzen 3 2200GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 3 2200ge"],"fields":[{"key":"Model name","value":"Ryzen 3 2200GE","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2200GE","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD2200C6M4MFB","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 19, 2018","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 19, 2018","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-1245-r3997","location":"Amd/ryzen 3/2200ge · revision 3997 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-3bdfdb0671f47b6d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1245-r3997","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-3bdfdb0671f47b6d"},{"id":"cw-3be8ec89a2a47cbe","name":"MSM6225","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2005,"architecture":"ARM9","process":"90 nm","aliases":["Qualcomm msm6xxx msm6225"],"fields":[{"key":"Model name","value":"Qualcomm MSM6225","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6225","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 23, 2004","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 14, 2005","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":146,"unit":"MHz","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7663-r24929","location":"Qualcomm/msm6xxx/msm6225 · revision 24929 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be8ec89a2a47cbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6225&oldid=24929","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7663-r24929"],"url":"https://museum.vlsi.kr/objects/cw-3be8ec89a2a47cbe"},{"id":"cw-3be92354ea464331","name":"CN5750-600 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5750-600bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5750-600 SP","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5750-600 SP","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5750-600BG1217-SP","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8167-r25826","location":"Cavium/octeon plus/cn5750-600bg1217-sp · revision 25826 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-sp&oldid=25826","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3be92354ea464331","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8167-r25826","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-3be92354ea464331"},{"id":"cw-3c0f8b115533dfad","name":"X-Gene 2 APM883208-X2","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AppliedMicro","series":"X-Gene 2","year":2015,"architecture":"Shadowcat","process":"28 nm","aliases":["Apm x-gene apm883208-x2"],"fields":[{"key":"Model name","value":"APM883208-X2","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AppliedMicro","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"APM883208-X2","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2014","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2015","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"X-Gene","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"X-Gene 2","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Shadowcat","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.9,"unit":"V","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. 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Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x8 MiB","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1866","unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. 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Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-3c0f8b115533dfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883208-x2&oldid=15346","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.82,"unit":"GiB/s","sourceId":"chipswiki-4759-r15346","location":"Apm/x-gene/apm883208-x2 · revision 15346 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. 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Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2173IT","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZS","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DE","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M1","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":70,"unit":"W","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":896,"unit":"KiB","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":14,"unit":"MiB","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x1 MiB","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-7153-r22580","location":"Intel/xeon d/d-2173it · revision 22580 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-3c4190a7f9203bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DE2-66V8T","unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am486DE2-66V8TGC","unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1996,"unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DE2","unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":66,"unit":"MHz","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DE2","unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8576-r26774","location":"Amd/am486/am486de2-66v8t · revision 26774 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3c6e1133404836ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8576-r26774"],"url":"https://museum.vlsi.kr/objects/cw-3c6e1133404836ef"},{"id":"cw-3ca6486e1d6dfba7","name":"Xeon E3-1505M v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1500 v5","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1505m v5"],"fields":[{"key":"Model name","value":"Xeon E3-1505M v5","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1505M v5","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066202191415","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2FN","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500 v5","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics P530","unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-5305-r17319","location":"Intel/xeon e3/e3-1505m v5 · revision 17319 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1505m%20v5&oldid=17319","sourceDate":"2018-07-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-14. Not an independent measurement.","entityId":"cw-3ca6486e1d6dfba7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5305-r17319","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-3ca6486e1d6dfba7"},{"id":"cw-3ca6e07279bc8439","name":"EPYC 7642","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7642"],"fields":[{"key":"Model name","value":"EPYC 7642","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7642,"unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000074","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000074WOF","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":48,"unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":96,"unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":3,"unit":"MiB","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"48x32 KiB","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"48x32 KiB","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"48x512 KiB","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x16 MiB","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-866-r2250","location":"Amd/epyc/7642 · revision 2250 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-3ca6e07279bc8439","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7642&oldid=2250","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-866-r2250"],"url":"https://museum.vlsi.kr/objects/cw-3ca6e07279bc8439"},{"id":"cw-3cb4c69b5c73c075","name":"Atom C3308","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3308"],"fields":[{"key":"Model name","value":"Atom C3308","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3308","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502639802","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR38D","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9.5,"unit":"W","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":112,"unit":"KiB","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1866","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-1864-r6400","location":"Intel/atom/c3308 · revision 6400 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3308&oldid=6400","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-3cb4c69b5c73c075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1864-r6400","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-3cb4c69b5c73c075"},{"id":"cw-3cbaef8134ae8f97","name":"Xeon W-2170B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-2000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon w w-2170b"],"fields":[{"key":"Model name","value":"Xeon W-2170B","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. 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Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2170B","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. 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Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2017","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. 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Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-10-24. 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Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. 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Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. 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Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. 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Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. 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Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. 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Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":14,"unit":"MiB","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x1 MiB","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-3cbaef8134ae8f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4516-r14678","location":"Intel/xeon w/w-2170b · revision 14678 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. 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Not an independent measurement.","entityId":"cw-3cc9a375fbb655aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3550h&oldid=1798","sourceDate":"2021-05-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-755-r1798","location":"Amd/ryzen 5/3550h · revision 1798 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-17. 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Not an independent measurement.","entityId":"cw-3cc9a375fbb655aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3550h&oldid=1798","sourceDate":"2021-05-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-755-r1798","location":"Amd/ryzen 5/3550h · revision 1798 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-17. 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Not an independent measurement.","entityId":"cw-3cc9a375fbb655aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3550h&oldid=1798","sourceDate":"2021-05-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-755-r1798","location":"Amd/ryzen 5/3550h · revision 1798 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-17. Not an independent measurement.","entityId":"cw-3cc9a375fbb655aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3550h&oldid=1798","sourceDate":"2021-05-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-755-r1798","location":"Amd/ryzen 5/3550h · revision 1798 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-17. Not an independent measurement.","entityId":"cw-3cc9a375fbb655aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3550h&oldid=1798","sourceDate":"2021-05-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-755-r1798","location":"Amd/ryzen 5/3550h · revision 1798 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-17. Not an independent measurement.","entityId":"cw-3cc9a375fbb655aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3550h&oldid=1798","sourceDate":"2021-05-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-755-r1798","location":"Amd/ryzen 5/3550h · revision 1798 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-17. 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Not an independent measurement.","entityId":"cw-3cc9a375fbb655aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3550h&oldid=1798","sourceDate":"2021-05-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-755-r1798","location":"Amd/ryzen 5/3550h · revision 1798 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-17. Not an independent measurement.","entityId":"cw-3cc9a375fbb655aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3550h&oldid=1798","sourceDate":"2021-05-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-755-r1798","location":"Amd/ryzen 5/3550h · revision 1798 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-17. Not an independent measurement.","entityId":"cw-3cc9a375fbb655aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3550h&oldid=1798","sourceDate":"2021-05-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-755-r1798","location":"Amd/ryzen 5/3550h · revision 1798 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-17. 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Not an independent measurement.","entityId":"cw-3cc9a375fbb655aa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3550h&oldid=1798","sourceDate":"2021-05-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-755-r1798","location":"Amd/ryzen 5/3550h · revision 1798 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-17. 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Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2635QM","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-7894-r25398","location":"Intel/core i7/i7-2635qm · revision 25398 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2635qm&oldid=25398","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1224","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":58.5,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":51,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.347,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3cd0c7f0aefc25a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7894-r25398","chipswiki-31408-r92251"],"url":"https://museum.vlsi.kr/objects/cw-3cd0c7f0aefc25a5"},{"id":"cw-3cd90b39018fc6d4","name":"Zen 5","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":null,"process":"3 nm","aliases":["Amd microarchitectures zen 5"],"fields":[{"key":"Architecture name","value":"Zen 5","unit":"","sourceId":"chipswiki-77-r97031","location":"Amd/microarchitectures/zen 5 · revision 97031 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. 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Not an independent measurement.","entityId":"cw-3cd90b39018fc6d4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%205&oldid=97031","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"nm","sourceId":"chipswiki-77-r97031","location":"Amd/microarchitectures/zen 5 · revision 97031 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. 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Not an independent measurement.","entityId":"cw-3cd90b39018fc6d4","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%205&oldid=97031","sourceDate":"2022-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-77-r97031","location":"Amd/microarchitectures/zen 5 · revision 97031 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-10. 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Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6240L","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4.5 TiB","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1484-r4933","location":"Intel/xeon gold/6240l · revision 4933 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3d14897ef291c54c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1484-r4933"],"url":"https://museum.vlsi.kr/objects/cw-3d14897ef291c54c"},{"id":"cw-3d2b8be72487d4a7","name":"PEZY-SCnp","kind":"sku","entityType":"product-model","subtype":"cpu","company":"PEZY","year":2016,"process":"28 nm","aliases":["Pezy pezy-scx pezy-scnp"],"fields":[{"key":"Model name","value":"PEZY-SCnp","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. 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Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. 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Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"PEZY-SCx","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":766.66,"unit":"MHz","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1024,"unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8192,"unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.95,"unit":"V","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-2397","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","supportingSources":[{"sourceId":"chipswiki-31372-r92160","location":"Template:Packages/pezy/fcbga-2397 · revision 92160 · {{#subobject:package}} / package","value":"FCBGA-2397","unit":""}],"entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","alternatives":[{"value":"BGA","sourceId":"chipswiki-31372-r92160","reason":"Template:Packages/pezy/fcbga-2397 · revision 92160 · {{#subobject:package}} / package type. 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Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":64,"unit":"KiB","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":32,"unit":"KiB","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"2x16 KiB","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":32,"unit":"KiB","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"2x16 KiB","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":64,"unit":"KiB","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"1x64 KiB","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":3,"unit":"MiB","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":2,"unit":"MiB","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"1024x2 KiB","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 2)","value":"per processor element","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":1,"unit":"MiB","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"512x2 KiB","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 2)","value":"per 2 processor elements","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":4,"unit":"MiB","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"4x2 MiB","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 2)","value":"per city","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache — Cache (section 2)","value":8,"unit":"MiB","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization — Cache (section 2)","value":"4x2 MiB","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity — Cache (section 2)","value":"per prefecture","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":127.156,"unit":"GiB/s","sourceId":"chipswiki-4783-r15451","location":"Pezy/pezy-scx/pezy-scnp · revision 15451 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-scnp&oldid=15451","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":2397,"unit":"","sourceId":"chipswiki-31372-r92160","location":"Template:Packages/pezy/fcbga-2397 · revision 92160 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpezy%2Ffcbga-2397&oldid=92160","sourceDate":"2017-11-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31372-r92160","location":"Template:Packages/pezy/fcbga-2397 · revision 92160 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpezy%2Ffcbga-2397&oldid=92160","sourceDate":"2017-11-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":50,"unit":"mm","sourceId":"chipswiki-31372-r92160","location":"Template:Packages/pezy/fcbga-2397 · revision 92160 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpezy%2Ffcbga-2397&oldid=92160","sourceDate":"2017-11-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":50,"unit":"mm","sourceId":"chipswiki-31372-r92160","location":"Template:Packages/pezy/fcbga-2397 · revision 92160 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-3d2b8be72487d4a7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpezy%2Ffcbga-2397&oldid=92160","sourceDate":"2017-11-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4783-r15451","chipswiki-31372-r92160"],"url":"https://museum.vlsi.kr/objects/cw-3d2b8be72487d4a7"},{"id":"cw-3d40e371ab41937e","name":"Gen12","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2020,"process":"10 nm","aliases":["Intel microarchitectures gen12"],"fields":[{"key":"Architecture name","value":"Gen12","unit":"","sourceId":"chipswiki-2175-r7302","location":"Intel/microarchitectures/gen12 · revision 7302 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-12. Not an independent measurement.","entityId":"cw-3d40e371ab41937e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen12&oldid=7302","sourceDate":"2019-07-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2175-r7302","location":"Intel/microarchitectures/gen12 · revision 7302 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-12. Not an independent measurement.","entityId":"cw-3d40e371ab41937e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen12&oldid=7302","sourceDate":"2019-07-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2175-r7302","location":"Intel/microarchitectures/gen12 · revision 7302 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-12. Not an independent measurement.","entityId":"cw-3d40e371ab41937e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen12&oldid=7302","sourceDate":"2019-07-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2020,"unit":"","sourceId":"chipswiki-2175-r7302","location":"Intel/microarchitectures/gen12 · revision 7302 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-12. Not an independent measurement.","entityId":"cw-3d40e371ab41937e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen12&oldid=7302","sourceDate":"2019-07-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-2175-r7302","location":"Intel/microarchitectures/gen12 · revision 7302 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-12. Not an independent measurement.","entityId":"cw-3d40e371ab41937e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen12&oldid=7302","sourceDate":"2019-07-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen11","unit":"","sourceId":"chipswiki-2175-r7302","location":"Intel/microarchitectures/gen12 · revision 7302 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-12. Not an independent measurement.","entityId":"cw-3d40e371ab41937e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen12&oldid=7302","sourceDate":"2019-07-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen13","unit":"","sourceId":"chipswiki-2175-r7302","location":"Intel/microarchitectures/gen12 · revision 7302 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-12. Not an independent measurement.","entityId":"cw-3d40e371ab41937e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen12&oldid=7302","sourceDate":"2019-07-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2175-r7302"],"url":"https://museum.vlsi.kr/objects/cw-3d40e371ab41937e"},{"id":"cw-3d4e58078efa35f3","name":"Pentium Gold G4600","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"G4600","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel pentium gold g4600"],"fields":[{"key":"Model name","value":"Pentium Gold G4600","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4600","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80677G4600","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80677G4600","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35F","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G4600","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7774-r25201","location":"Intel/pentium gold/g4600 · revision 25201 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3d4e58078efa35f3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg4600&oldid=25201","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7774-r25201"],"url":"https://museum.vlsi.kr/objects/cw-3d4e58078efa35f3"},{"id":"cw-3d5a5d7114716b27","name":"Ryzen 5 PRO 5650GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 5 pro 5650ge"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 5650GE","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5650GE","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000258","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2021","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1900,"unit":"MHz","sourceId":"chipswiki-609-r1431","location":"Amd/ryzen 5/pro 5650ge · revision 1431 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-3d5a5d7114716b27","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-609-r1431"],"url":"https://museum.vlsi.kr/objects/cw-3d5a5d7114716b27"},{"id":"cw-3d72d6547235c714","name":"Core i3-1005G1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-10000","year":2019,"architecture":"Ice Lake (Client)","process":"10 nm","aliases":["Intel core i3 i3-1005g1"],"fields":[{"key":"Model name","value":"Core i3-1005G1","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-1005G1","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-10000","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ice Lake (Client)","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Ice Lake","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake U","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-3d72d6547235c714","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-1005g1&oldid=4088","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1259-r4088","location":"Intel/core i3/i3-1005g1 · revision 4088 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8175,"unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2017,"unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"GHz","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":33,"unit":"MiB","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x1.375 MiB","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-2140-r7119","location":"Intel/xeon platinum/8175 · revision 7119 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-30. Not an independent measurement.","entityId":"cw-3d72eb593c9cd183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8175&oldid=7119","sourceDate":"2019-07-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2140-r7119"],"url":"https://museum.vlsi.kr/objects/cw-3d72eb593c9cd183"},{"id":"cw-3d9917254abc6a53","name":"Core i7-3770K","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-3000","year":2012,"architecture":"Ivy Bridge","process":"22 nm","aliases":["Intel core i7 i7-3770k"],"fields":[{"key":"Model name","value":"Intel Core i7-3770K","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-3770K","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0PL","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2012","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-3000","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ivy Bridge","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ivy Bridge-HE-4","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"E1","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":"1008 million","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-3d9917254abc6a53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-3770k&oldid=11885","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3806-r11885","location":"Intel/core i7/i7-3770k · revision 11885 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2123","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303533002","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80673W2123","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3LJ","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-2000","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Basin Falls","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake W","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x1 MiB","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8.25,"unit":"MiB","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.375 MiB","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-2533-r8697","location":"Intel/xeon w/w-2123 · revision 8697 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-3dd0a56247aebf3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2123&oldid=8697","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2533-r8697"],"url":"https://museum.vlsi.kr/objects/cw-3dd0a56247aebf3a"},{"id":"cw-3de960967a9a58a5","name":"Am186ED–25VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186ed–25vc\\w"],"fields":[{"key":"Model name","value":"Am186ED–25VC\\W","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ED–25VC\\W","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ED–25VC\\W","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14667-r44728","location":"Amd/am186ex/am186ed–25vc\\w · revision 44728 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3de960967a9a58a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14667-r44728"],"url":"https://museum.vlsi.kr/objects/cw-3de960967a9a58a5"},{"id":"cw-3e19540e4a4b2cda","name":"A10 Fusion","kind":"sku","entityType":"product-model","subtype":"soc","company":"Apple","year":2016,"architecture":"Hurricane","process":"16 nm","aliases":["Apple ax a10"],"fields":[{"key":"Model name","value":"A10 Fusion","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Apple","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A10 Fusion","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"T8010","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 7, 2016","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 16, 2016","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ax","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Hurricane","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Hurricane","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Zephyr","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":125,"unit":"mm²","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-896-r2352","location":"Apple/ax/a10 · revision 2352 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-3e19540e4a4b2cda","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-896-r2352"],"url":"https://museum.vlsi.kr/objects/cw-3e19540e4a4b2cda"},{"id":"cw-3e344298515b9a67","name":"Xeon Gold 6240","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6240"],"fields":[{"key":"Model name","value":"Xeon Gold 6240","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6240,"unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504194001","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806956240","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF8X","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. 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Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. 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Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. Not an independent measurement.","entityId":"cw-3e344298515b9a67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","sourceDate":"2020-04-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1218-r3808","location":"Intel/xeon gold/6240 · revision 3808 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-03. 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Not an independent measurement.","entityId":"cw-3e432552608c6ca1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dc&oldid=26682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3.125,"unit":"MHz","sourceId":"chipswiki-8489-r26682","location":"Amd/am9080/am9080a-1dc · revision 26682 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3e432552608c6ca1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dc&oldid=26682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8489-r26682","location":"Amd/am9080/am9080a-1dc · revision 26682 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3e432552608c6ca1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dc&oldid=26682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8489-r26682","location":"Amd/am9080/am9080a-1dc · revision 26682 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3e432552608c6ca1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dc&oldid=26682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8489-r26682","location":"Amd/am9080/am9080a-1dc · revision 26682 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3e432552608c6ca1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dc&oldid=26682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8489-r26682","location":"Amd/am9080/am9080a-1dc · revision 26682 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3e432552608c6ca1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dc&oldid=26682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8489-r26682","location":"Amd/am9080/am9080a-1dc · revision 26682 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3e432552608c6ca1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dc&oldid=26682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8489-r26682","location":"Amd/am9080/am9080a-1dc · revision 26682 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3e432552608c6ca1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dc&oldid=26682","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8489-r26682"],"url":"https://museum.vlsi.kr/objects/cw-3e432552608c6ca1"},{"id":"cw-3e48940cbabbb4bc","name":"Am186CU-25KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CU","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186cu-25ki\\w"],"fields":[{"key":"Model name","value":"Am186CU-25KI\\W","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CU-25KI\\W","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CU-25KI\\W","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CU","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-3e48940cbabbb4bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14680-r44741","location":"Amd/am186cx/am186cu-25ki\\w · revision 44741 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-3e7edd27d2e6ccd5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk9&oldid=13974","sourceDate":"2018-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4337-r13974","location":"Amd/microarchitectures/k9 · revision 13974 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-01. Not an independent measurement.","entityId":"cw-3e7edd27d2e6ccd5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk9&oldid=13974","sourceDate":"2018-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-4337-r13974","location":"Amd/microarchitectures/k9 · revision 13974 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-01. Not an independent measurement.","entityId":"cw-3e7edd27d2e6ccd5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk9&oldid=13974","sourceDate":"2018-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-4337-r13974","location":"Amd/microarchitectures/k9 · revision 13974 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-01. Not an independent measurement.","entityId":"cw-3e7edd27d2e6ccd5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk9&oldid=13974","sourceDate":"2018-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4337-r13974","location":"Amd/microarchitectures/k9 · revision 13974 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-01. Not an independent measurement.","entityId":"cw-3e7edd27d2e6ccd5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk9&oldid=13974","sourceDate":"2018-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"K8","unit":"","sourceId":"chipswiki-4337-r13974","location":"Amd/microarchitectures/k9 · revision 13974 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-01. Not an independent measurement.","entityId":"cw-3e7edd27d2e6ccd5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk9&oldid=13974","sourceDate":"2018-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"K10","unit":"","sourceId":"chipswiki-4337-r13974","location":"Amd/microarchitectures/k9 · revision 13974 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-01. Not an independent measurement.","entityId":"cw-3e7edd27d2e6ccd5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk9&oldid=13974","sourceDate":"2018-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4337-r13974"],"url":"https://museum.vlsi.kr/objects/cw-3e7edd27d2e6ccd5"},{"id":"cw-3eac38affc5685f9","name":"Xeon Gold 6154","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6154"],"fields":[{"key":"Model name","value":"Xeon Gold 6154","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6154,"unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303592700","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3J5","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":200,"unit":"W","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1493-r4945","location":"Intel/xeon gold/6154 · revision 4945 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-3eac38affc5685f9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1493-r4945"],"url":"https://museum.vlsi.kr/objects/cw-3eac38affc5685f9"},{"id":"cw-3ec02c616e7260dc","name":"CN5860-600 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5860-600bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5860-600 SCP","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5860-600 SCP","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5860-600BG1521-SCP","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x16 KiB","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8120-r25779","location":"Cavium/octeon plus/cn5860-600bg1521-scp · revision 25779 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-scp&oldid=25779","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ec02c616e7260dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8120-r25779","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-3ec02c616e7260dc"},{"id":"cw-3ed6209ad5d0fb13","name":"MSM6550","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2004,"architecture":"ARM9","process":"130 nm","aliases":["Qualcomm msm6xxx msm6550"],"fields":[{"key":"Model name","value":"Qualcomm MSM6550","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6550","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 16, 2003","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2004","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":225,"unit":"MHz","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. 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Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. 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Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-938-r2621","location":"Qualcomm/msm6xxx/msm6550 · revision 2621 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-06. 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Not an independent measurement.","entityId":"cw-3ed6209ad5d0fb13","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6550&oldid=2621","sourceDate":"2020-10-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-938-r2621"],"url":"https://museum.vlsi.kr/objects/cw-3ed6209ad5d0fb13"},{"id":"cw-3ee84dfa1f8412d7","name":"Sophon BM1682","kind":"sku","entityType":"product-model","subtype":"sku","company":"Bitmain","year":2018,"process":"28 nm","aliases":["Bitmain sophon bm1682"],"fields":[{"key":"Model name","value":"Sophon BM1682","unit":"","sourceId":"chipswiki-4836-r15647","location":"Bitmain/sophon/bm1682 · revision 15647 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. 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Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1682&oldid=15647","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4836-r15647","location":"Bitmain/sophon/bm1682 · revision 15647 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1682&oldid=15647","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"BM1682","unit":"","sourceId":"chipswiki-4836-r15647","location":"Bitmain/sophon/bm1682 · revision 15647 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1682&oldid=15647","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Artificial Intelligence","unit":"","sourceId":"chipswiki-4836-r15647","location":"Bitmain/sophon/bm1682 · revision 15647 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1682&oldid=15647","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 25, 2017","unit":"","sourceId":"chipswiki-4836-r15647","location":"Bitmain/sophon/bm1682 · revision 15647 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1682&oldid=15647","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2018","unit":"","sourceId":"chipswiki-4836-r15647","location":"Bitmain/sophon/bm1682 · revision 15647 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1682&oldid=15647","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Sophon","unit":"","sourceId":"chipswiki-4836-r15647","location":"Bitmain/sophon/bm1682 · revision 15647 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1682&oldid=15647","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-4836-r15647","location":"Bitmain/sophon/bm1682 · revision 15647 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1682&oldid=15647","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4836-r15647","location":"Bitmain/sophon/bm1682 · revision 15647 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1682&oldid=15647","sourceDate":"2018-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1599","unit":"","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1599,"unit":"","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":33,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":33,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.18,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-16. Not an independent measurement.","entityId":"cw-3ee84dfa1f8412d7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4836-r15647","chipswiki-31370-r92158"],"url":"https://museum.vlsi.kr/objects/cw-3ee84dfa1f8412d7"},{"id":"cw-3eeeafb703b2926e","name":"Am486DXL-40","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DXL","year":1993,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486dxl-40"],"fields":[{"key":"Model name","value":"Am486DXL-40","unit":"","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3eeeafb703b2926e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3eeeafb703b2926e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3eeeafb703b2926e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DXL-40","unit":"","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3eeeafb703b2926e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DXL-40","unit":"","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3eeeafb703b2926e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3eeeafb703b2926e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 1993","unit":"","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3eeeafb703b2926e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3eeeafb703b2926e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DXL","unit":"","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3eeeafb703b2926e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3eeeafb703b2926e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3eeeafb703b2926e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DXL","unit":"","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3eeeafb703b2926e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8545-r26741","location":"Amd/am486/am486dxl-40 · revision 26741 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z612","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AY80609003042AC","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBZN","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 4, 2010","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z612","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1500,"unit":"MHz","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"cDMI","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Moorestown","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Langwell","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lincroft","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":38,"unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":140000000,"unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":65.2526,"unit":"mm²","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":1.3,"unit":"W","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":"-25 °C","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX535","unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8056-r25692","location":"Intel/atom/z612 · revision 25692 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-518","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":518,"unit":"","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":13.8,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.1,"unit":"mm","sourceId":"chipswiki-31501-r92563","location":"Template:Packages/intel/fcbga-518 · revision 92563 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3ef421d1ddeada66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","sourceDate":"2017-04-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8056-r25692","chipswiki-31501-r92563"],"url":"https://museum.vlsi.kr/objects/cw-3ef421d1ddeada66"},{"id":"cw-3ef5d4e01c054ab0","name":"AMD-K6-IIIE+/400ACR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-iii+ amd-k6-iiie+-400acr"],"fields":[{"key":"Model name","value":"AMD-K6-IIIE+/400ACR","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-IIIE+/400ACR","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-IIIE+/400ACR","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III+","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III+ Embedded","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":3,"unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21400000,"unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9.5,"unit":"W","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4506-r14648","location":"Amd/k6-iii+/amd-k6-iiie+-400acr · revision 14648 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-3ef5d4e01c054ab0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400acr&oldid=14648","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4506-r14648"],"url":"https://museum.vlsi.kr/objects/cw-3ef5d4e01c054ab0"},{"id":"cw-3f0be10d787d3a49","name":"Core i5-8269U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-8269u"],"fields":[{"key":"Model name","value":"Core i5-8269U","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8269U","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8068403419614","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRCKA","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake U","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D0","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics 655","unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-1144-r3432","location":"Intel/core i5/i5-8269u · revision 3432 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8269u&oldid=3432","sourceDate":"2020-05-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1528","unit":"","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1528,"unit":"","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":46,"unit":"mm","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-13. Not an independent measurement.","entityId":"cw-3f0be10d787d3a49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1144-r3432","chipswiki-31288-r91954"],"url":"https://museum.vlsi.kr/objects/cw-3f0be10d787d3a49"},{"id":"cw-3f385d49924fc704","name":"Ryzen 7 PRO 5750G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 7 pro 5750g"],"fields":[{"key":"Model name","value":"Ryzen 7 PRO 5750G","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5750G","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000254","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2021","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4600,"unit":"MHz","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2000,"unit":"MHz","sourceId":"chipswiki-608-r1430","location":"Amd/ryzen 7/pro 5750g · revision 1430 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-3f385d49924fc704","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-608-r1430"],"url":"https://museum.vlsi.kr/objects/cw-3f385d49924fc704"},{"id":"cw-3f5bfe4c6760e685","name":"K6-2/337AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1998,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-337afr"],"fields":[{"key":"Model name","value":"K6-2/337AFR","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/337AFR","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/337AFR","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"38L3054","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1998,"unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":337,"unit":"MHz","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"75 MT/s","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8367-r26062","location":"Amd/k6-2/k6-2-337afr · revision 26062 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f5bfe4c6760e685","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-337afr&oldid=26062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8367-r26062"],"url":"https://museum.vlsi.kr/objects/cw-3f5bfe4c6760e685"},{"id":"cw-3f7510acd1b0c945","name":"Atom Z560","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z500","year":2010,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z560"],"fields":[{"key":"Model name","value":"Atom Z560","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z560","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2010","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2010","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z500","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2133.33,"unit":"MHz","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"533.33 MT/s","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Menlow","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Poulsbo","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":28,"unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":24.18,"unit":"mm²","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2.5,"unit":"W","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8060-r25696","location":"Intel/atom/z560 · revision 25696 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-441","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":441,"unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":14,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f7510acd1b0c945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8060-r25696","chipswiki-31513-r92656"],"url":"https://museum.vlsi.kr/objects/cw-3f7510acd1b0c945"},{"id":"cw-3f79cf9416b5794f","name":"Celeron G3900E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel celeron g3900e"],"fields":[{"key":"Model name","value":"Celeron G3900E","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G3900E","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066201939703","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2GH","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-8032-r25636","location":"Intel/celeron/g3900e · revision 25636 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f79cf9416b5794f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z500","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AC80586UC800DE","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AC80566UC800DE","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLB6Q","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z500","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"400 MT/s","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Menlow","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Poulsbo","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":28,"unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":24.18,"unit":"mm²","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"650 mW","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8071-r25707","location":"Intel/atom/z500 · revision 25707 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz500&oldid=25707","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-441","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":441,"unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":14,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-3f9e879c0f3b78cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8071-r25707","chipswiki-31513-r92656"],"url":"https://museum.vlsi.kr/objects/cw-3f9e879c0f3b78cd"},{"id":"cw-3fb3fedddf0f64e6","name":"Cortex-A55","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2017,"process":"16 nm","aliases":["Arm holdings microarchitectures cortex-a55"],"fields":[{"key":"Architecture name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / manufacturer 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 3","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"manufacturer 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"SMIC","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / manufacturer 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 4","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"manufacturer 4","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 29, 2017","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / process 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 3","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"process 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / process 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 4","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"process 4","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / process 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 5","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"process 5","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"In-order","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":8,"unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"2-way","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"64-256 KiB","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":"0-4 MiB","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cluster","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"Cluster","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A13","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Helios","unit":"","sourceId":"chipswiki-27-r96956","location":"Arm holdings/microarchitectures/cortex-a55 · revision 96956 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-12. Not an independent measurement.","entityId":"cw-3fb3fedddf0f64e6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a55&oldid=96956","sourceDate":"2022-11-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-27-r96956"],"url":"https://museum.vlsi.kr/objects/cw-3fb3fedddf0f64e6"},{"id":"cw-3fd76ed1b7e83974","name":"MT6595","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","year":2014,"architecture":"Cortex-A17","process":"28 nm","aliases":["Mediatek mt65xx mt6595"],"fields":[{"key":"Model name","value":"MT6595","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MT6595","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6595","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Februray 11, 2014","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"Februray 11, 2014","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MT65xx","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2500,"unit":"MHz","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1700,"unit":"MHz","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A17","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A17","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A7","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":89,"unit":"mm²","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":512,"unit":"KiB","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"1x512 KiB","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":2,"unit":"MiB","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"1x2 MiB","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR G6200","unit":"","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":600,"unit":"MHz","sourceId":"chipswiki-4180-r13376","location":"Mediatek/mt65xx/mt6595 · revision 13376 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-3fd76ed1b7e83974","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fmt65xx%2Fmt6595&oldid=13376","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4180-r13376"],"url":"https://museum.vlsi.kr/objects/cw-3fd76ed1b7e83974"},{"id":"cw-403f2f6a09abad74","name":"Core i9-8950HK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i9-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i9 i9-8950hk"],"fields":[{"key":"Model name","value":"Core i9-8950HK","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i9-8950HK","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8068403805708","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRCKN","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i9","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i9-8000","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4600,"unit":"MHz","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake H","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-8950hk&oldid=8024","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2401-r8024","location":"Intel/core i9/i9-8950hk · revision 8024 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-403f2f6a09abad74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 650","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D0650AUT1B","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2000","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 19, 2000","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":550,"unit":"MHz","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":29.4,"unit":"W","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8439-r26147","location":"Amd/duron/d650aut1b · revision 26147 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4041108c340a42ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8439-r26147"],"url":"https://museum.vlsi.kr/objects/cw-4041108c340a42ad"},{"id":"cw-40439eeb9d810212","name":"J8086-1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"J8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 j8086-1"],"fields":[{"key":"Model name","value":"AMD J8086-1","unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J8086-1","unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"J8086-1","unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"J8086","unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-44","unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8507-r26700","location":"Amd/am8086/j8086-1 · revision 26700 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40439eeb9d810212","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8507-r26700"],"url":"https://museum.vlsi.kr/objects/cw-40439eeb9d810212"},{"id":"cw-4056b8dd0f3106f1","name":"Core i5-7267U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-7200","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-7267u"],"fields":[{"key":"Model name","value":"Core i5-7267U","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7267U","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR362","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7200","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-03-16. 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Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. 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Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. 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Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. 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Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. 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Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. 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Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4056b8dd0f3106f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7267u&oldid=21646","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-6950-r21646","location":"Intel/core i5/i5-7267u · revision 21646 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. 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Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-100V8T","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-100V8T","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1994,"unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4V","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":100,"unit":"MHz","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4V","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8554-r26750","location":"Amd/am486/am486dx4-100v8t · revision 26750 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-40600432f7583bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8554-r26750"],"url":"https://museum.vlsi.kr/objects/cw-40600432f7583bb0"},{"id":"cw-4070e1480a395f9a","name":"80386","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":1984,"process":"1.5 µm","aliases":["Intel microarchitectures 80386"],"fields":[{"key":"Architecture name","value":80386,"unit":"","sourceId":"chipswiki-8771-r27265","location":"Intel/microarchitectures/80386 · revision 27265 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4070e1480a395f9a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80386&oldid=27265","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8771-r27265","location":"Intel/microarchitectures/80386 · revision 27265 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4070e1480a395f9a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80386&oldid=27265","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8771-r27265","location":"Intel/microarchitectures/80386 · revision 27265 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4070e1480a395f9a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80386&oldid=27265","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"March, 1984","unit":"","sourceId":"chipswiki-8771-r27265","location":"Intel/microarchitectures/80386 · revision 27265 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4070e1480a395f9a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80386&oldid=27265","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8771-r27265","location":"Intel/microarchitectures/80386 · revision 27265 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4070e1480a395f9a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80386&oldid=27265","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8771-r27265","location":"Intel/microarchitectures/80386 · revision 27265 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4070e1480a395f9a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80386&oldid=27265","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":80286,"unit":"","sourceId":"chipswiki-8771-r27265","location":"Intel/microarchitectures/80386 · revision 27265 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4070e1480a395f9a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80386&oldid=27265","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":80486,"unit":"","sourceId":"chipswiki-8771-r27265","location":"Intel/microarchitectures/80386 · revision 27265 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4070e1480a395f9a","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80386&oldid=27265","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8771-r27265"],"url":"https://museum.vlsi.kr/objects/cw-4070e1480a395f9a"},{"id":"cw-4099196ddaa4270b","name":"Exynos 5420","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 5","year":2013,"architecture":"Cortex-A15","process":"28 nm","aliases":["Samsung exynos 5420"],"fields":[{"key":"Model name","value":"Exynos 5420","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5420,"unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 23, 2013","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2013","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 5","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1300,"unit":"MHz","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A15","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A15","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A7","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6849-r21342","location":"Samsung/exynos/5420 · revision 21342 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-4099196ddaa4270b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6849-r21342"],"url":"https://museum.vlsi.kr/objects/cw-4099196ddaa4270b"},{"id":"cw-40c25352a2a9cce8","name":"Gen4","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2006,"process":"65 nm","aliases":["Intel microarchitectures gen4"],"fields":[{"key":"Architecture name","value":"Gen4","unit":"","sourceId":"chipswiki-15957-r52678","location":"Intel/microarchitectures/gen4 · revision 52678 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-40c25352a2a9cce8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen4&oldid=52678","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-15957-r52678","location":"Intel/microarchitectures/gen4 · revision 52678 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-40c25352a2a9cce8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen4&oldid=52678","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-15957-r52678","location":"Intel/microarchitectures/gen4 · revision 52678 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-40c25352a2a9cce8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen4&oldid=52678","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2006,"unit":"","sourceId":"chipswiki-15957-r52678","location":"Intel/microarchitectures/gen4 · revision 52678 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-40c25352a2a9cce8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen4&oldid=52678","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-15957-r52678","location":"Intel/microarchitectures/gen4 · revision 52678 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-40c25352a2a9cce8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen4&oldid=52678","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen3.5","unit":"","sourceId":"chipswiki-15957-r52678","location":"Intel/microarchitectures/gen4 · revision 52678 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-40c25352a2a9cce8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen4&oldid=52678","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen5","unit":"","sourceId":"chipswiki-15957-r52678","location":"Intel/microarchitectures/gen4 · revision 52678 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-40c25352a2a9cce8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen4&oldid=52678","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15957-r52678"],"url":"https://museum.vlsi.kr/objects/cw-40c25352a2a9cce8"},{"id":"cw-41132937a895438f","name":"Xeon Platinum 8170M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8170m"],"fields":[{"key":"Model name","value":"Xeon Platinum 8170M","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8170M","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303319201","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3BD","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":26,"unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":52,"unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.625,"unit":"MiB","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":832,"unit":"KiB","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"26x32 KiB","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":832,"unit":"KiB","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"26x32 KiB","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":26,"unit":"MiB","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"26x1 MiB","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-2556-r8819","location":"Intel/xeon platinum/8170m · revision 8819 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-41132937a895438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170m&oldid=8819","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2556-r8819"],"url":"https://museum.vlsi.kr/objects/cw-41132937a895438f"},{"id":"cw-41175225d993230c","name":"Core i7-610E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-600","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7 i7-610e"],"fields":[{"key":"Model name","value":"Intel Core i7-610E","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-610E","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617005745AB","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2533.33,"unit":"MHz","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3199.99,"unit":"MHz","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBXX","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBRZ","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":766,"unit":"MHz","sourceId":"chipswiki-7856-r25356","location":"Intel/core i7/i7-610e · revision 25356 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-610e&oldid=25356","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41175225d993230c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-411c7f30c09c8e8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1684&oldid=16476","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Artificial Intelligence","unit":"","sourceId":"chipswiki-5067-r16476","location":"Bitmain/sophon/bm1684 · revision 16476 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-411c7f30c09c8e8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1684&oldid=16476","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2018","unit":"","sourceId":"chipswiki-5067-r16476","location":"Bitmain/sophon/bm1684 · revision 16476 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. 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Not an independent measurement.","entityId":"cw-411c7f30c09c8e8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1684&oldid=16476","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Sophon","unit":"","sourceId":"chipswiki-5067-r16476","location":"Bitmain/sophon/bm1684 · revision 16476 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-411c7f30c09c8e8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1684&oldid=16476","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-5067-r16476","location":"Bitmain/sophon/bm1684 · revision 16476 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-411c7f30c09c8e8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1684&oldid=16476","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5067-r16476","location":"Bitmain/sophon/bm1684 · revision 16476 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-411c7f30c09c8e8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Bitmain%2Fsophon%2Fbm1684&oldid=16476","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1599","unit":"","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-411c7f30c09c8e8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-411c7f30c09c8e8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1599,"unit":"","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-411c7f30c09c8e8c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fbitmain%2Ffcbga-1599&oldid=92158","sourceDate":"2017-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31370-r92158","location":"Template:Packages/bitmain/fcbga-1599 · revision 92158 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. 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Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper","unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8374-r26069","location":"Amd/k6-2/k6-2-333afr-66 · revision 26069 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-413108af187d6706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333afr-66&oldid=26069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8374-r26069"],"url":"https://museum.vlsi.kr/objects/cw-413108af187d6706"},{"id":"cw-4176ed2822090a6b","name":"Opteron A1120","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"A1100","year":2016,"architecture":"Cortex-A57","process":"28 nm","aliases":["Amd opteron a1120"],"fields":[{"key":"Model name","value":"Opteron A1120","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Global Foundries","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A1120","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"OA1120ARD4NAD","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2014","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2016","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Opteron","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"A1100","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A57","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Seattle","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":80,"unit":"°C","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4 × 48 KiB","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"3-way set associative","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4 × 32 KiB","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2 × 1 MiB","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1866","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"29.9 GB/s","unit":"","sourceId":"chipswiki-955-r2705","location":"Amd/opteron/a1120 · revision 2705 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fopteron%2Fa1120&oldid=2705","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SP1","unit":"","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1021,"unit":"","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":27,"unit":"mm","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":27,"unit":"mm","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.46,"unit":"mm","sourceId":"chipswiki-31113-r91580","location":"Template:Packages/amd/SP1 · revision 91580 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-09-08. Not an independent measurement.","entityId":"cw-4176ed2822090a6b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FSP1&oldid=91580","sourceDate":"2020-09-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-955-r2705","chipswiki-31113-r91580"],"url":"https://museum.vlsi.kr/objects/cw-4176ed2822090a6b"},{"id":"cw-41b1f84aa63b8557","name":"Mobile Duron 700 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dm700avs1b"],"fields":[{"key":"Model name","value":"Duron 700","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 700","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DM700AVS1B","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 15, 2001","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 15, 2001","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":700,"unit":"MHz","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.4,"unit":"V","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8405-r26113","location":"Amd/duron/dm700avs1b · revision 26113 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41b1f84aa63b8557","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm700avs1b&oldid=26113","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8405-r26113"],"url":"https://museum.vlsi.kr/objects/cw-41b1f84aa63b8557"},{"id":"cw-41cd3d257fffba61","name":"Xeon E5-2658 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2658 v4"],"fields":[{"key":"Model name","value":"Xeon E5-2658 v4","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2658 v4","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002044801","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2NB","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3.5,"unit":"MiB","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x256 KiB","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35,"unit":"MiB","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x2.5 MiB","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7733-r25110","location":"Intel/xeon e5/e5-2658 v4 · revision 25110 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-41cd3d257fffba61","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2658%20v4&oldid=25110","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7733-r25110"],"url":"https://museum.vlsi.kr/objects/cw-41cd3d257fffba61"},{"id":"cw-41fb8e2c52c19036","name":"Core i9-9990XE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i9-9000","year":2019,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel core i9 i9-9990xe"],"fields":[{"key":"Model name","value":"Core i9-9990XE","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. 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Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i9-9990XE","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80673I99990X","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SREZA","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2019","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2019","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i9","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i9-9000","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4000,"unit":"MHz","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":5000,"unit":"MHz","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-03-07. 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Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Basin Falls Refresh","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake X Refresh","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":5,"unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. 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Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":14,"unit":"MiB","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. 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Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. 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Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. 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Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-491-r983","location":"Intel/core i9/i9-9990xe · revision 983 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-07. Not an independent measurement.","entityId":"cw-41fb8e2c52c19036","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9990xe&oldid=983","sourceDate":"2022-03-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-491-r983"],"url":"https://museum.vlsi.kr/objects/cw-41fb8e2c52c19036"},{"id":"cw-427add0572bc90c8","name":"Tremont","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2019,"process":"10 nm","aliases":["Intel microarchitectures tremont"],"fields":[{"key":"Architecture name","value":"Tremont","unit":"","sourceId":"chipswiki-891-r2333","location":"Intel/microarchitectures/tremont · revision 2333 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-10. 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Not an independent measurement.","entityId":"cw-427add0572bc90c8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftremont&oldid=2333","sourceDate":"2020-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-891-r2333","location":"Intel/microarchitectures/tremont · revision 2333 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-10. Not an independent measurement.","entityId":"cw-427add0572bc90c8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftremont&oldid=2333","sourceDate":"2020-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2019,"unit":"","sourceId":"chipswiki-891-r2333","location":"Intel/microarchitectures/tremont · revision 2333 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-10. 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Not an independent measurement.","entityId":"cw-427add0572bc90c8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftremont&oldid=2333","sourceDate":"2020-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-891-r2333","location":"Intel/microarchitectures/tremont · revision 2333 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-10. Not an independent measurement.","entityId":"cw-427add0572bc90c8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftremont&oldid=2333","sourceDate":"2020-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-891-r2333","location":"Intel/microarchitectures/tremont · revision 2333 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-10. Not an independent measurement.","entityId":"cw-427add0572bc90c8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftremont&oldid=2333","sourceDate":"2020-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Elkhart Lake","unit":"","sourceId":"chipswiki-891-r2333","location":"Intel/microarchitectures/tremont · revision 2333 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-10. Not an independent measurement.","entityId":"cw-427add0572bc90c8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftremont&oldid=2333","sourceDate":"2020-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Jasper Lake","unit":"","sourceId":"chipswiki-891-r2333","location":"Intel/microarchitectures/tremont · revision 2333 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-12-10. Not an independent measurement.","entityId":"cw-427add0572bc90c8","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftremont&oldid=2333","sourceDate":"2020-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skyhawk Lake","unit":"","sourceId":"chipswiki-891-r2333","location":"Intel/microarchitectures/tremont · revision 2333 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2020-12-10. Not an independent measurement.","entityId":"cw-427add0572bc90c8","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftremont&oldid=2333","sourceDate":"2020-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lakefield","unit":"","sourceId":"chipswiki-891-r2333","location":"Intel/microarchitectures/tremont · revision 2333 · {{microarchitecture}} / core name 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 4","note":"Source-reported parameter; source revision 2020-12-10. Not an independent measurement.","entityId":"cw-427add0572bc90c8","scope":"core name 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftremont&oldid=2333","sourceDate":"2020-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Snow Ridge","unit":"","sourceId":"chipswiki-891-r2333","location":"Intel/microarchitectures/tremont · revision 2333 · {{microarchitecture}} / core name 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 5","note":"Source-reported parameter; source revision 2020-12-10. Not an independent measurement.","entityId":"cw-427add0572bc90c8","scope":"core name 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftremont&oldid=2333","sourceDate":"2020-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Goldmont Plus","unit":"","sourceId":"chipswiki-891-r2333","location":"Intel/microarchitectures/tremont · revision 2333 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-10. Not an independent measurement.","entityId":"cw-427add0572bc90c8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftremont&oldid=2333","sourceDate":"2020-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gracemont","unit":"","sourceId":"chipswiki-891-r2333","location":"Intel/microarchitectures/tremont · revision 2333 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-10. Not an independent measurement.","entityId":"cw-427add0572bc90c8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftremont&oldid=2333","sourceDate":"2020-12-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-891-r2333"],"url":"https://museum.vlsi.kr/objects/cw-427add0572bc90c8"},{"id":"cw-4295052ca2e5dca8","name":"Am186EM–40VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186EM","year":1995,"architecture":"80186","aliases":["Amd am186ex am186em–40vc\\w"],"fields":[{"key":"Model name","value":"Am186EM–40VC\\W","unit":"","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EM–40VC\\W","unit":"","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14649-r44710","location":"Amd/am186ex/am186em–40vc\\w · revision 44710 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4295052ca2e5dca8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14649-r44710"],"url":"https://museum.vlsi.kr/objects/cw-4295052ca2e5dca8"},{"id":"cw-42a43930765caf96","name":"D8086-2","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 d8086-2"],"fields":[{"key":"Model name","value":"AMD D8086-2","unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D8086-2","unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D8086-2","unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D8086","unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8515-r26708","location":"Amd/am8086/d8086-2 · revision 26708 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42a43930765caf96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8515-r26708"],"url":"https://museum.vlsi.kr/objects/cw-42a43930765caf96"},{"id":"cw-42c25f85b0c5fc79","name":"Core i7-2655QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2655qm"],"fields":[{"key":"Model name","value":"Core i7-2655QM","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2655QM","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700837300","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR031","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-7889-r25393","location":"Intel/core i7/i7-2655qm · revision 25393 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1224","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1224,"unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":58.5,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":51,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.347,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42c25f85b0c5fc79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7889-r25393","chipswiki-31408-r92251"],"url":"https://museum.vlsi.kr/objects/cw-42c25f85b0c5fc79"},{"id":"cw-42cb48fb001b75ed","name":"VY86C060","kind":"sku","entityType":"product-model","subtype":"soc","company":"Arm","year":1993,"architecture":"ARM6","process":"0.8 µm","aliases":["Vti vl86cx vy86c060"],"fields":[{"key":"Model name","value":"VY86C060","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VY86C060","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C060-20FC","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C060-25FC","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1993,"unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":20,"unit":"MHz","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":25,"unit":"MHz","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv3","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM6","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MEMC","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM60","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.8,"unit":"µm","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":35530,"unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":5.89,"unit":"mm²","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"","sourceId":"chipswiki-7632-r24887","location":"Vti/vl86cx/vy86c060 · revision 24887 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-42cb48fb001b75ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c060&oldid=24887","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7632-r24887"],"url":"https://museum.vlsi.kr/objects/cw-42cb48fb001b75ed"},{"id":"cw-42da9d1ebb0cccca","name":"EPYC 7351","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7351"],"fields":[{"key":"Model name","value":"EPYC 7351","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7351,"unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS7351BEVGPAF","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x64 KiB","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x512 KiB","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x8 MiB","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-5071-r16543","location":"Amd/epyc/7351 · revision 16543 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-42da9d1ebb0cccca","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5071-r16543","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-42da9d1ebb0cccca"},{"id":"cw-42de4ae866249bb0","name":"Ryzen 9 3900","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 9 3900"],"fields":[{"key":"Model name","value":"Ryzen 9 3900","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3900,"unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 24, 2019","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 9","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Matisse","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x512 KiB","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x16 MiB","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-1550-r5057","location":"Amd/ryzen 9/3900 · revision 5057 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. 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Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-42de4ae866249bb0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1550-r5057","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-42de4ae866249bb0"},{"id":"cw-42fe970017c89f79","name":"Skylake (server)","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2017,"process":"14 nm","aliases":["Intel microarchitectures skylake (server)"],"fields":[{"key":"Architecture name","value":"Skylake (server)","unit":"","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. 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Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 4, 2017","unit":"","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":4,"unit":"","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.375,"unit":"MiB","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake X","unit":"","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake W","unit":"","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Broadwell","unit":"","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cascade Lake","unit":"","sourceId":"chipswiki-296-r594","location":"Intel/microarchitectures/skylake (server) · revision 594 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-06. Not an independent measurement.","entityId":"cw-42fe970017c89f79","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fskylake%20(server)&oldid=594","sourceDate":"2022-07-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-296-r594"],"url":"https://museum.vlsi.kr/objects/cw-42fe970017c89f79"},{"id":"cw-43013268b2b05e32","name":"CN5850-800 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5850-800bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5850-800 SCP","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5850-800 SCP","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8129-r25788","location":"Cavium/octeon plus/cn5850-800bg1521-scp · revision 25788 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-scp&oldid=25788","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43013268b2b05e32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8129-r25788","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-43013268b2b05e32"},{"id":"cw-431b947084722cd9","name":"AMD-K5-PR166ABQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5k86","year":1997,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr166abq"],"fields":[{"key":"Model name","value":"AMD-K5-PR166ABQ","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR166ABQ","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR166ABQ","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 1997","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 1997","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"5k86","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":116.66,"unit":"MHz","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5k86","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":2,"unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":181,"unit":"mm²","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8397-r26093","location":"Amd/k5/amd-k5-pr166abq · revision 26093 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-431b947084722cd9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abq&oldid=26093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8397-r26093"],"url":"https://museum.vlsi.kr/objects/cw-431b947084722cd9"},{"id":"cw-432491f1b28110cb","name":"Core i5-470UM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-400","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i5 i5-470um"],"fields":[{"key":"Model name","value":"Intel Core i5-470UM","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-470UM","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617005190AI","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 1, 2010","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1, 2010","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-400","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1333.33,"unit":"MHz","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1866.66,"unit":"MHz","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBXP","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-7938-r25485","location":"Intel/core i5/i5-470um · revision 25485 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-470um&oldid=25485","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-432491f1b28110cb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7938-r25485","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-432491f1b28110cb"},{"id":"cw-4342ae670364dc9d","name":"Enhanced NetBurst","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":null,"process":"90 nm","aliases":["Intel microarchitectures enhanced netburst"],"fields":[{"key":"Architecture name","value":"Enhanced NetBurst","unit":"","sourceId":"chipswiki-4186-r13413","location":"Intel/microarchitectures/enhanced netburst · revision 13413 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-4342ae670364dc9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fenhanced%20netburst&oldid=13413","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4186-r13413","location":"Intel/microarchitectures/enhanced netburst · revision 13413 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-4342ae670364dc9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fenhanced%20netburst&oldid=13413","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4186-r13413","location":"Intel/microarchitectures/enhanced netburst · revision 13413 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-4342ae670364dc9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fenhanced%20netburst&oldid=13413","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-4186-r13413","location":"Intel/microarchitectures/enhanced netburst · revision 13413 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-4342ae670364dc9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fenhanced%20netburst&oldid=13413","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-4186-r13413","location":"Intel/microarchitectures/enhanced netburst · revision 13413 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-4342ae670364dc9d","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fenhanced%20netburst&oldid=13413","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-4186-r13413","location":"Intel/microarchitectures/enhanced netburst · revision 13413 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-4342ae670364dc9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fenhanced%20netburst&oldid=13413","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Netburst","unit":"","sourceId":"chipswiki-4186-r13413","location":"Intel/microarchitectures/enhanced netburst · revision 13413 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-4342ae670364dc9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fenhanced%20netburst&oldid=13413","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4186-r13413"],"url":"https://museum.vlsi.kr/objects/cw-4342ae670364dc9d"},{"id":"cw-4348f49707db3711","name":"Core i7-6820EQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6820eq"],"fields":[{"key":"Model name","value":"Core i7-6820EQ","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6820EQ","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066201939103","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DT","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 12, 2015","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7836-r25329","location":"Intel/core i7/i7-6820eq · revision 25329 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4348f49707db3711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820eq&oldid=25329","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701140800","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7955-r25503","location":"Intel/core i5/i5-2497m · revision 25503 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2497m&oldid=25503","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43499911893c1a5f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7955-r25503","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-43499911893c1a5f"},{"id":"cw-436537edb74e9186","name":"D8086-1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 d8086-1"],"fields":[{"key":"Model name","value":"AMD D8086-1","unit":"","sourceId":"chipswiki-8517-r26710","location":"Amd/am8086/d8086-1 · revision 26710 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-436537edb74e9186","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1&oldid=26710","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8517-r26710","location":"Amd/am8086/d8086-1 · revision 26710 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-436537edb74e9186","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1&oldid=26710","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D8086-1","unit":"","sourceId":"chipswiki-8517-r26710","location":"Amd/am8086/d8086-1 · revision 26710 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-436537edb74e9186","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1&oldid=26710","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8517-r26710","location":"Amd/am8086/d8086-1 · revision 26710 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-436537edb74e9186","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1&oldid=26710","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8517-r26710","location":"Amd/am8086/d8086-1 · revision 26710 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-436537edb74e9186","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1&oldid=26710","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8517-r26710","location":"Amd/am8086/d8086-1 · revision 26710 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-436537edb74e9186","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1&oldid=26710","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8517-r26710","location":"Amd/am8086/d8086-1 · revision 26710 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-436537edb74e9186","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1&oldid=26710","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8517-r26710","location":"Amd/am8086/d8086-1 · revision 26710 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-436537edb74e9186","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1&oldid=26710","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8517-r26710"],"url":"https://museum.vlsi.kr/objects/cw-436537edb74e9186"},{"id":"cw-437234288467159a","name":"Kirin 710","kind":"sku","entityType":"product-model","subtype":"soc","company":"HiSilicon","series":"700","year":2018,"architecture":"Cortex-A53","process":"12 nm","aliases":["Hisilicon kirin 710"],"fields":[{"key":"Model name","value":"Kirin 710","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":710,"unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 19, 2018","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 19, 2018","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Kirin","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":700,"unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2200,"unit":"MHz","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1700,"unit":"MHz","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A73","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":6,"unit":"GiB","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","alternatives":[{"value":"6 GiB - 10 GIB","sourceId":"chipswiki-635-r1531","reason":"Hisilicon/kirin/710 · revision 1531 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Memory type","value":"LPDDR4","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G51","unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":4,"unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-635-r1531","location":"Hisilicon/kirin/710 · revision 1531 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-18. Not an independent measurement.","entityId":"cw-437234288467159a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F710&oldid=1531","sourceDate":"2021-08-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-635-r1531"],"url":"https://museum.vlsi.kr/objects/cw-437234288467159a"},{"id":"cw-43c578def002c909","name":"Celeron J3455","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"J Series","year":2016,"architecture":"Goldmont","process":"14 nm","aliases":["Intel celeron j3455"],"fields":[{"key":"Model name","value":"Celeron J3455","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J3455","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066802986102","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2Z9","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"J Series","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2300,"unit":"MHz","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Apollo Lake","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":10,"unit":"W","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-1296","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1296","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-3897-r12327","location":"Intel/celeron/j3455 · revision 12327 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-09. Not an independent measurement.","entityId":"cw-43c578def002c909","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3455&oldid=12327","sourceDate":"2019-02-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3897-r12327"],"url":"https://museum.vlsi.kr/objects/cw-43c578def002c909"},{"id":"cw-43d183769dbd78a8","name":"ThunderX2 CN9975","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","year":2018,"architecture":"Vulcan","process":"16 nm","aliases":["Cavium thunderx2 cn9975"],"fields":[{"key":"Model name","value":"ThunderX2 CN9975","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN9975","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9975-2400LG4077-Y21-G","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9975-2300LG4077-Y21-G","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9975-2200LG4077-Y21-G","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9975-2100LG4077-Y21-G","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9975-2000LG4077-Y21-G","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9975-1800LG4077-Y21-G","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / part number 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 6","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"part number 6","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 7, 2018","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 7, 2018","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"ThunderX2","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":2100,"unit":"MHz","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 4","value":2200,"unit":"MHz","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / frequency 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 4","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"Multiple clock domains; raw parameter frequency 4","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 5","value":2300,"unit":"MHz","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / frequency 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 5","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"Multiple clock domains; raw parameter frequency 5","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 6","value":2400,"unit":"MHz","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / frequency 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 6","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"Multiple clock domains; raw parameter frequency 6","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.1","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Vulcan","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":112,"unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":7,"unit":"MiB","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x256 KiB","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":28,"unit":"MiB","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-2836-r9485","location":"Cavium/thunderx2/cn9975 · revision 9485 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-43d183769dbd78a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9975&oldid=9485","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2836-r9485"],"url":"https://museum.vlsi.kr/objects/cw-43d183769dbd78a8"},{"id":"cw-43d2c6d77b5d4a16","name":"Xeon Gold 5222","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 5222"],"fields":[{"key":"Model name","value":"Xeon Gold 5222","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5222,"unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504193501","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF8V","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5200,"unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x1 MiB","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-43d2c6d77b5d4a16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5222&oldid=8442","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-2475-r8442","location":"Intel/xeon gold/5222 · revision 8442 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. 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Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"APM883832-X3","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 08, 2017","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"X-Gene","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"X-Gene 3","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylark","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.85,"unit":"V","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x256 KiB","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x32 MiB","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-4754-r15336","location":"Apm/x-gene/apm883832-x3 · revision 15336 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-43db4f7eff6c3dac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fx-gene%2Fapm883832-x3&oldid=15336","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4754-r15336"],"url":"https://museum.vlsi.kr/objects/cw-43db4f7eff6c3dac"},{"id":"cw-43e250cb751771c5","name":"Granite Rapids","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2024,"process":"7 nm","aliases":["Intel microarchitectures granite rapids"],"fields":[{"key":"Architecture name","value":"Granite Rapids","unit":"","sourceId":"chipswiki-506-r1005","location":"Intel/microarchitectures/granite rapids · revision 1005 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-43e250cb751771c5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgranite%20rapids&oldid=1005","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-506-r1005","location":"Intel/microarchitectures/granite rapids · revision 1005 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-43e250cb751771c5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgranite%20rapids&oldid=1005","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-506-r1005","location":"Intel/microarchitectures/granite rapids · revision 1005 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-43e250cb751771c5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgranite%20rapids&oldid=1005","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2024,"unit":"","sourceId":"chipswiki-506-r1005","location":"Intel/microarchitectures/granite rapids · revision 1005 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-43e250cb751771c5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgranite%20rapids&oldid=1005","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-506-r1005","location":"Intel/microarchitectures/granite rapids · revision 1005 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-43e250cb751771c5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgranite%20rapids&oldid=1005","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-506-r1005","location":"Intel/microarchitectures/granite rapids · revision 1005 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-43e250cb751771c5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgranite%20rapids&oldid=1005","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Emerald Rapids","unit":"","sourceId":"chipswiki-506-r1005","location":"Intel/microarchitectures/granite rapids · revision 1005 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-43e250cb751771c5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgranite%20rapids&oldid=1005","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Diamond Rapids","unit":"","sourceId":"chipswiki-506-r1005","location":"Intel/microarchitectures/granite rapids · revision 1005 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-43e250cb751771c5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgranite%20rapids&oldid=1005","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-506-r1005"],"url":"https://museum.vlsi.kr/objects/cw-43e250cb751771c5"},{"id":"cw-43f3b653d4bb1d78","name":"Core i7-5950HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5900","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core i7 i7-5950hq"],"fields":[{"key":"Model name","value":"Intel Core i7-5950HQ","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-5950HQ","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065802491601","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 2, 2015","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 2, 2015","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5900,"unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2BJ","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"G0","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"shared","unit":"","sourceId":"chipswiki-7857-r25357","location":"Intel/core i7/i7-5950hq · revision 25357 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5950hq&oldid=25357","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-43f3b653d4bb1d78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7857-r25357","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-43f3b653d4bb1d78"},{"id":"cw-442b39fe0d807bc6","name":"Celeron 847","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron 847"],"fields":[{"key":"Model name","value":"Celeron 847","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":847,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700852800","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR08N","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-6939-r21626","location":"Intel/celeron/847 · revision 21626 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-442b39fe0d807bc6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. 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Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. 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Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. 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Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. 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Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":23,"unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-5569-r18090","location":"Intel/core i3/i3-8320 · revision 18090 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-21. Not an independent measurement.","entityId":"cw-443238e2febb8ae2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","sourceDate":"2018-06-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5569-r18090"],"url":"https://museum.vlsi.kr/objects/cw-443238e2febb8ae2"},{"id":"cw-443f0e8c9dfe23cc","name":"Core M 5Y10c","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core m 5y10c"],"fields":[{"key":"Model name","value":"Core M 5Y10c","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5Y10c","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065802062002","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2014","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2015","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core M","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2,"unit":"GHz","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR23C","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell Y","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"3D","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"F0","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1300000000,"unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":82,"unit":"mm²","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1234","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"MiB","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7815-r25264","location":"Intel/core m/5y10c · revision 25264 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-443f0e8c9dfe23cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10c&oldid=25264","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7815-r25264"],"url":"https://museum.vlsi.kr/objects/cw-443f0e8c9dfe23cc"},{"id":"cw-44604fc178e1c78a","name":"UltraSPARC-I 182MHz","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Sun Microsystems","series":"UltraSPARC-I","year":1996,"architecture":"UltraSPARC-I","process":"0.5 µm","aliases":["Sun microsystems ultrasparc stp1030bga-182"],"fields":[{"key":"Model name","value":"UltraSPARC-I 182MHz","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Sun Microsystems","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Texas Instruments","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"UltraSPARC-I 182MHz","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"STP103OBGA-182","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 2, 1995","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 1996","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"UltraSPARC","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"UltraSPARC-I","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":182,"unit":"MHz","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SPARC V9","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"UltraSPARC-I","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.5,"unit":"µm","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":5200000,"unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":310,"unit":"mm²","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7638-r24895","location":"Sun microsystems/ultrasparc/stp1030bga-182 · revision 24895 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-512","unit":"","sourceId":"chipswiki-31351-r92104","location":"Template:Packages/sun microsystems/bga-521 · revision 92104 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fsun%20microsystems%2Fbga-521&oldid=92104","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31351-r92104","location":"Template:Packages/sun microsystems/bga-521 · revision 92104 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fsun%20microsystems%2Fbga-521&oldid=92104","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":512,"unit":"","sourceId":"chipswiki-31351-r92104","location":"Template:Packages/sun microsystems/bga-521 · revision 92104 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44604fc178e1c78a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fsun%20microsystems%2Fbga-521&oldid=92104","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7638-r24895","chipswiki-31351-r92104"],"url":"https://museum.vlsi.kr/objects/cw-44604fc178e1c78a"},{"id":"cw-446d90763f65a19d","name":"Polaris","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2016,"process":"14 nm","aliases":["Amd microarchitectures polaris"],"fields":[{"key":"Architecture name","value":"Polaris","unit":"","sourceId":"chipswiki-3077-r10273","location":"Amd/microarchitectures/polaris · revision 10273 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-17. Not an independent measurement.","entityId":"cw-446d90763f65a19d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpolaris&oldid=10273","sourceDate":"2019-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-3077-r10273","location":"Amd/microarchitectures/polaris · revision 10273 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-17. Not an independent measurement.","entityId":"cw-446d90763f65a19d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpolaris&oldid=10273","sourceDate":"2019-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3077-r10273","location":"Amd/microarchitectures/polaris · revision 10273 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-17. Not an independent measurement.","entityId":"cw-446d90763f65a19d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpolaris&oldid=10273","sourceDate":"2019-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"Q2 2016","unit":"","sourceId":"chipswiki-3077-r10273","location":"Amd/microarchitectures/polaris · revision 10273 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-17. Not an independent measurement.","entityId":"cw-446d90763f65a19d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpolaris&oldid=10273","sourceDate":"2019-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3077-r10273","location":"Amd/microarchitectures/polaris · revision 10273 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-17. Not an independent measurement.","entityId":"cw-446d90763f65a19d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpolaris&oldid=10273","sourceDate":"2019-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-3077-r10273","location":"Amd/microarchitectures/polaris · revision 10273 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2019-04-17. Not an independent measurement.","entityId":"cw-446d90763f65a19d","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpolaris&oldid=10273","sourceDate":"2019-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Volcanic Islands","unit":"","sourceId":"chipswiki-3077-r10273","location":"Amd/microarchitectures/polaris · revision 10273 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-17. Not an independent measurement.","entityId":"cw-446d90763f65a19d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fpolaris&oldid=10273","sourceDate":"2019-04-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Vega","unit":"","sourceId":"chipswiki-3077-r10273","location":"Amd/microarchitectures/polaris · revision 10273 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-17. 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Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-IIIE+/400ATZ","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-IIIE+/400ATZ","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III+","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III+ Embedded","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399,"unit":"MHz","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":3,"unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21400000,"unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9.5,"unit":"W","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-991-r2837","location":"Amd/k6-iii+/amd-k6-iiie+-400atz · revision 2837 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-44b1cac43a05ad37","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-400atz&oldid=2837","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-991-r2837"],"url":"https://museum.vlsi.kr/objects/cw-44b1cac43a05ad37"},{"id":"cw-44ec21ca019ed62c","name":"R-Car V2H","kind":"sku","entityType":"product-model","subtype":"soc","company":"Renesas","series":"2nd Gen","year":2016,"architecture":"Cortex-A15","process":"28 nm","aliases":["Renesas r-car v2h"],"fields":[{"key":"Model name","value":"R-Car V2H","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"V2H","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"R8A7792","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 28, 2014","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 2016","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"2nd Gen","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A15","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A15","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.03,"unit":"V","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR SGX531","unit":"","sourceId":"chipswiki-7642-r24902","location":"Renesas/r-car/v2h · revision 24902 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fv2h&oldid=24902","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-64","unit":"","sourceId":"chipswiki-31423-r92287","location":"Template:Packages/renesas/fcbga-64 · revision 92287 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-64&oldid=92287","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31423-r92287","location":"Template:Packages/renesas/fcbga-64 · revision 92287 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-64&oldid=92287","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":64,"unit":"","sourceId":"chipswiki-31423-r92287","location":"Template:Packages/renesas/fcbga-64 · revision 92287 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-64&oldid=92287","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.4,"unit":"mm","sourceId":"chipswiki-31423-r92287","location":"Template:Packages/renesas/fcbga-64 · revision 92287 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-64&oldid=92287","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":10,"unit":"mm","sourceId":"chipswiki-31423-r92287","location":"Template:Packages/renesas/fcbga-64 · revision 92287 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-64&oldid=92287","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":10,"unit":"mm","sourceId":"chipswiki-31423-r92287","location":"Template:Packages/renesas/fcbga-64 · revision 92287 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-44ec21ca019ed62c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-64&oldid=92287","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7642-r24902","chipswiki-31423-r92287"],"url":"https://museum.vlsi.kr/objects/cw-44ec21ca019ed62c"},{"id":"cw-44edf29e946dc102","name":"Xeon Gold 6240R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2020,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6240r"],"fields":[{"key":"Model name","value":"Xeon Gold 6240R","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6240R","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake R","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1265-r4100","location":"Intel/xeon gold/6240r · revision 4100 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-44edf29e946dc102","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240r&oldid=4100","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1265-r4100"],"url":"https://museum.vlsi.kr/objects/cw-44edf29e946dc102"},{"id":"cw-453575bb4feffd0a","name":"Athlon 300U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"300","year":2019,"architecture":"Zen","process":"14 nm","aliases":["Amd athlon 300u"],"fields":[{"key":"Model name","value":"Athlon 300U","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"300U","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM300UC4T2OFG","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":300,"unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","alternatives":[{"value":"32 GiB","sourceId":"chipswiki-1102-r3264","reason":"Amd/athlon/300u · revision 3264 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-1102-r3264","location":"Amd/athlon/300u · revision 3264 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-453575bb4feffd0a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1102-r3264"],"url":"https://museum.vlsi.kr/objects/cw-453575bb4feffd0a"},{"id":"cw-4548aa08777eaa96","name":"CN3850-600 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3850-600bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN3850-600 SCP","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3850-600 SCP","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3850-600BG1521-SCP","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x8 KiB","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8203-r25862","location":"Cavium/octeon/cn3850-600bg1521-scp · revision 25862 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-600bg1521-scp&oldid=25862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4548aa08777eaa96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8203-r25862","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-4548aa08777eaa96"},{"id":"cw-4553203eedd47e59","name":"SHAVE v3.0 (Fragrak)","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Movidius","year":2014,"process":"28 nm","aliases":["Movidius microarchitectures shave v3.0"],"fields":[{"key":"Architecture name","value":"SHAVE v3.0","unit":"","sourceId":"chipswiki-6951-r21648","location":"Movidius/microarchitectures/shave v3.0 · revision 21648 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4553203eedd47e59","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v3.0&oldid=21648","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Movidius","unit":"","sourceId":"chipswiki-6951-r21648","location":"Movidius/microarchitectures/shave v3.0 · revision 21648 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4553203eedd47e59","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v3.0&oldid=21648","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-6951-r21648","location":"Movidius/microarchitectures/shave v3.0 · revision 21648 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4553203eedd47e59","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v3.0&oldid=21648","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2014,"unit":"","sourceId":"chipswiki-6951-r21648","location":"Movidius/microarchitectures/shave v3.0 · revision 21648 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4553203eedd47e59","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v3.0&oldid=21648","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-6951-r21648","location":"Movidius/microarchitectures/shave v3.0 · revision 21648 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4553203eedd47e59","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v3.0&oldid=21648","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"VLLIW","unit":"","sourceId":"chipswiki-6951-r21648","location":"Movidius/microarchitectures/shave v3.0 · revision 21648 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4553203eedd47e59","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v3.0&oldid=21648","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SHAVE","unit":"","sourceId":"chipswiki-6951-r21648","location":"Movidius/microarchitectures/shave v3.0 · revision 21648 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4553203eedd47e59","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v3.0&oldid=21648","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6951-r21648","location":"Movidius/microarchitectures/shave v3.0 · revision 21648 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"chip","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4553203eedd47e59","scope":"chip","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v3.0&oldid=21648","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"SHAVE v2.0","unit":"","sourceId":"chipswiki-6951-r21648","location":"Movidius/microarchitectures/shave v3.0 · revision 21648 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-16. Not an independent measurement.","entityId":"cw-4553203eedd47e59","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmicroarchitectures%2Fshave%20v3.0&oldid=21648","sourceDate":"2018-03-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6951-r21648"],"url":"https://museum.vlsi.kr/objects/cw-4553203eedd47e59"},{"id":"cw-456811e77e821b3b","name":"Athlon MP 2000+","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2002,"architecture":"K7","process":"130 nm","aliases":["Amd athlon mp amsn2000dkt3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 2000+","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 2000+","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMSN2000DKT3C","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 27, 2002","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 27, 2002","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1667,"unit":"MHz","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Thoroughbred","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37200000,"unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":85,"unit":"mm²","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.65,"unit":"V","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8452-r26645","location":"Amd/athlon mp/amsn2000dkt3c · revision 26645 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2000dkt3c&oldid=26645","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-456811e77e821b3b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8452-r26645","chipswiki-31459-r92404"],"url":"https://museum.vlsi.kr/objects/cw-456811e77e821b3b"},{"id":"cw-4576201ecc8c0240","name":"Ryzen 7 4700GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 7 4700ge"],"fields":[{"key":"Model name","value":"Ryzen 7 4700GE","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4700GE","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000149","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 21, 2020","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2000,"unit":"MHz","sourceId":"chipswiki-702-r1702","location":"Amd/ryzen 7/4700ge · revision 1702 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4576201ecc8c0240","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-702-r1702"],"url":"https://museum.vlsi.kr/objects/cw-4576201ecc8c0240"},{"id":"cw-459bb8e76c2c129a","name":"AM9080A-4PC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-4pc"],"fields":[{"key":"Model name","value":"AMD AM9080A-4PC","unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-4PC","unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-4PC","unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4,"unit":"MHz","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"DIP-40","unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"DIP","unit":"","sourceId":"chipswiki-8472-r26665","location":"Amd/am9080/am9080a-4pc · revision 26665 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-459bb8e76c2c129a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4pc&oldid=26665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8472-r26665"],"url":"https://museum.vlsi.kr/objects/cw-459bb8e76c2c129a"},{"id":"cw-45b85aaf1141520b","name":"Xeon E3-1575M v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1500 v5","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1575m v5"],"fields":[{"key":"Model name","value":"Xeon E3-1575M v5","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1575M v5","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"JQ8066202193210","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2QV","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500 v5","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"N0","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7754-r25136","location":"Intel/xeon e3/e3-1575m v5 · revision 25136 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1575m%20v5&oldid=25136","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-45b85aaf1141520b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6138P","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8067303824101","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRCUG","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 16, 2018","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 16, 2018","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":195,"unit":"W","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. 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Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":27.5,"unit":"MiB","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x1.375 MiB","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-2473-r8412","location":"Intel/xeon gold/6138p · revision 8412 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-460d0a9c4e446d76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138p&oldid=8412","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2473-r8412"],"url":"https://museum.vlsi.kr/objects/cw-460d0a9c4e446d76"},{"id":"cw-460e1b23af9350f7","name":"EPYC 7702","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7702"],"fields":[{"key":"Model name","value":"EPYC 7702","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7702,"unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000038","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000038WOF","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3350,"unit":"MHz","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":64,"unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":128,"unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":200,"unit":"W","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"MiB","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64x32 KiB","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"MiB","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64x32 KiB","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"64x512 KiB","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x16 MiB","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-867-r2251","location":"Amd/epyc/7702 · revision 2251 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-460e1b23af9350f7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7702&oldid=2251","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-867-r2251"],"url":"https://museum.vlsi.kr/objects/cw-460e1b23af9350f7"},{"id":"cw-460e8d6f247f0739","name":"Alpha 21064","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"DEC","year":1992,"process":"0.75 µm","aliases":["Dec microarchitectures alpha 21064"],"fields":[{"key":"Architecture name","value":"Alpha 21064","unit":"","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"DEC","unit":"","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"DEC","unit":"","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"November 20, 1992","unit":"","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.75,"unit":"µm","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.675,"unit":"µm","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"2-way","unit":"","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Alpha","unit":"","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"0.125-16 MiB","unit":"","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"motherboard","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"motherboard","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Alpha 21164","unit":"","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Alpha 21064A","unit":"","sourceId":"chipswiki-13142-r37617","location":"Dec/microarchitectures/alpha 21064 · revision 37617 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2017-08-04. Not an independent measurement.","entityId":"cw-460e8d6f247f0739","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021064&oldid=37617","sourceDate":"2017-08-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-13142-r37617"],"url":"https://museum.vlsi.kr/objects/cw-460e8d6f247f0739"},{"id":"cw-461519bf0dea676b","name":"Alchemy Au1210-333MGF","kind":"sku","entityType":"product-model","subtype":"cpu","company":"RMI","year":2007,"architecture":"Au1","aliases":["Alchemy au1210-333mgf"],"fields":[{"key":"Model name","value":"Alchemy Au1210-333MGF","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"RMI","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1210-333MGF","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1210-333MGF","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 9, 2007","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2007","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"920 mW","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.332 GB/s","unit":"","sourceId":"chipswiki-448-r929","location":"Alchemy/au1210-333mgf · revision 929 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-461519bf0dea676b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgf&oldid=929","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-448-r929"],"url":"https://museum.vlsi.kr/objects/cw-461519bf0dea676b"},{"id":"cw-461a9ca45914f63d","name":"Snapdragon 710","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","year":2018,"architecture":"Cortex-A75","process":"10 nm","aliases":["Qualcomm snapdragon 700 710"],"fields":[{"key":"Model name","value":"Snapdragon 710","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM710","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 23, 2018","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 23, 2018","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 700","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2200,"unit":"MHz","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1700,"unit":"MHz","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A75","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 360 Gold","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 360 Silver","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 616","unit":"","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-1063-r3052","location":"Qualcomm/snapdragon 700/710 · revision 3052 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-05. Not an independent measurement.","entityId":"cw-461a9ca45914f63d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F710&oldid=3052","sourceDate":"2020-07-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1063-r3052"],"url":"https://museum.vlsi.kr/objects/cw-461a9ca45914f63d"},{"id":"cw-4620cdcc74a01410","name":"A4-9120C","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"A4-9000","year":2019,"architecture":"Excavator","process":"28 nm","aliases":["Amd a4 a4-9120c"],"fields":[{"key":"Model name","value":"A4-9120C","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A4-9120C","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM912CANN23AC","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"A4","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"A4-9000","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Excavator","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Stoney Ridge","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":96,"unit":"KiB","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x96 KiB","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1866","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon R4 Series","unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":600,"unit":"MHz","sourceId":"chipswiki-3788-r11780","location":"Amd/a4/a4-9120c · revision 11780 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-4620cdcc74a01410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3788-r11780"],"url":"https://museum.vlsi.kr/objects/cw-4620cdcc74a01410"},{"id":"cw-4620d9e298f5f788","name":"Ryzen 3 PRO 4350GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 3 pro 4350ge"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 4350GE","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 4350GE","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000154","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000154MPK","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 21, 2020","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1700,"unit":"MHz","sourceId":"chipswiki-699-r1695","location":"Amd/ryzen 3/pro 4350ge · revision 1695 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-4620d9e298f5f788","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%204350ge&oldid=1695","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-699-r1695"],"url":"https://museum.vlsi.kr/objects/cw-4620d9e298f5f788"},{"id":"cw-464bb71cb20f7e97","name":"Ryzen 5 PRO 3600","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 pro 3600"],"fields":[{"key":"Model name","value":"Ryzen 5 3600","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3600","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000029","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Matisse","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x16 MiB","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-1547-r5052","location":"Amd/ryzen 5/pro 3600 · revision 5052 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","sourceDate":"2019-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-24. Not an independent measurement.","entityId":"cw-464bb71cb20f7e97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1547-r5052","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-464bb71cb20f7e97"},{"id":"cw-464c67b968abede0","name":"Celeron N4100","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2017,"architecture":"Goldmont Plus","process":"14 nm","aliases":["Intel celeron n4100"],"fields":[{"key":"Model name","value":"Celeron N4100","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N4100","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8068003067408","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3S0","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 11, 2017","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 11, 2017","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont Plus","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Gemini Lake","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 600","unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":200,"unit":"MHz","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":700,"unit":"MHz","sourceId":"chipswiki-7505-r24401","location":"Intel/celeron/n4100 · revision 24401 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1090","unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1090,"unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-464c67b968abede0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7505-r24401","chipswiki-31338-r92075"],"url":"https://museum.vlsi.kr/objects/cw-464c67b968abede0"},{"id":"cw-4657ecdaa0ae3b35","name":"Am186EM–33VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186EM","year":1995,"architecture":"80186","aliases":["Amd am186ex am186em–33vc\\w"],"fields":[{"key":"Model name","value":"Am186EM–33VC\\W","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EM–33VC\\W","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EM–33VC\\W","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8.25 MT/s","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14651-r44712","location":"Amd/am186ex/am186em–33vc\\w · revision 44712 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4657ecdaa0ae3b35","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14651-r44712"],"url":"https://museum.vlsi.kr/objects/cw-4657ecdaa0ae3b35"},{"id":"cw-4659f125806cbaf3","name":"Core i3-8120T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-8120t"],"fields":[{"key":"Model name","value":"Core i3-8120T","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8120T","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. 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Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":23,"unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-5463-r17839","location":"Intel/core i3/i3-8120t · revision 17839 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-27. Not an independent measurement.","entityId":"cw-4659f125806cbaf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","sourceDate":"2018-06-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5463-r17839"],"url":"https://museum.vlsi.kr/objects/cw-4659f125806cbaf3"},{"id":"cw-46765225fdc73a5d","name":"Core i3-7120","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7000","year":null,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7120"],"fields":[{"key":"Model name","value":"Core i3-7120","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7120","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35D","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2017","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7000","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4000,"unit":"MHz","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7971-r25543","location":"Intel/core i3/i3-7120 · revision 25543 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46765225fdc73a5d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7120&oldid=25543","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7971-r25543"],"url":"https://museum.vlsi.kr/objects/cw-46765225fdc73a5d"},{"id":"cw-46a76da8def802c2","name":"Core i5-1035G1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-10000","year":2019,"architecture":"Ice Lake (Client)","process":"10 nm","aliases":["Intel core i5 i5-1035g1"],"fields":[{"key":"Model name","value":"Core i5-1035G1","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-1035G1","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-10000","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ice Lake (Client)","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Ice Lake","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake U","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x48 KiB","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics","unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":32,"unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-1258-r4086","location":"Intel/core i5/i5-1035g1 · revision 4086 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-46a76da8def802c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g1&oldid=4086","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1258-r4086"],"url":"https://museum.vlsi.kr/objects/cw-46a76da8def802c2"},{"id":"cw-46dc88081c5d404c","name":"EPYC 7663","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7663"],"fields":[{"key":"Model name","value":"EPYC 7663","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7663,"unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000318","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000318WOF","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":56,"unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":112,"unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":240,"unit":"W","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":3584,"unit":"KiB","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1792,"unit":"KiB","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"56 × 32 KiB","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1792,"unit":"KiB","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"56 × 32 KiB","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"56 × 512 KiB","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 32 MiB","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-737-r1758","location":"Amd/epyc/7663 · revision 1758 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-46dc88081c5d404c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-737-r1758"],"url":"https://museum.vlsi.kr/objects/cw-46dc88081c5d404c"},{"id":"cw-46df4c59b78ff6b7","name":"AMD-K6/233ACZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Mobile K6","year":1998,"architecture":"K6","process":"250 nm","aliases":["Amd k6 amd-k6 233acz"],"fields":[{"key":"Model name","value":"AMD-K6/233ACZ","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6/233ACZ","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6/233ACZ","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 1998","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 5, 1998","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Mobile K6","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":233.33,"unit":"MHz","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Little Foot","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":68,"unit":"mm²","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8290-r25978","location":"Amd/k6/amd-k6/233acz · revision 25978 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-46df4c59b78ff6b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233acz&oldid=25978","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8290-r25978"],"url":"https://museum.vlsi.kr/objects/cw-46df4c59b78ff6b7"},{"id":"cw-4723706cdf4fcc70","name":"Piton","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Princeton","year":null,"process":"32 nm","aliases":["Princeton piton"],"fields":[{"key":"Model name","value":"Piton","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Princeton","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 23, 2016","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"2,800 MT/s","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":460000000,"unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":36,"unit":"mm²","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":25,"unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":50,"unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":20000,"unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.9,"unit":"V","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"QFP-208","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"QFP","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"QFP-208","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":200,"unit":"KiB","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"25x8 KiB","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"25x64 KiB","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5445-r17727","location":"Princeton/piton · revision 17727 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-05. Not an independent measurement.","entityId":"cw-4723706cdf4fcc70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Princeton%2Fpiton&oldid=17727","sourceDate":"2018-07-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5445-r17727"],"url":"https://museum.vlsi.kr/objects/cw-4723706cdf4fcc70"},{"id":"cw-4727120a125098af","name":"Core i7-5750HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5700","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core i7 i7-5750hq"],"fields":[{"key":"Model name","value":"Intel Core i7-5750HQ","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-5750HQ","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065802491802","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 15, 2015","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 15, 2015","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5700,"unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2BL","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"shared","unit":"","sourceId":"chipswiki-7861-r25362","location":"Intel/core i7/i7-5750hq · revision 25362 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5750hq&oldid=25362","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4727120a125098af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7861-r25362","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-4727120a125098af"},{"id":"cw-47374a8069bb773b","name":"Volcanic Islands","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2014,"process":"28 nm","aliases":["Amd microarchitectures volcanic islands"],"fields":[{"key":"Architecture name","value":"Volcanic Islands","unit":"","sourceId":"chipswiki-13194-r38538","location":"Amd/microarchitectures/volcanic islands · revision 38538 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-47374a8069bb773b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvolcanic%20islands&oldid=38538","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-13194-r38538","location":"Amd/microarchitectures/volcanic islands · revision 38538 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-47374a8069bb773b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvolcanic%20islands&oldid=38538","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-13194-r38538","location":"Amd/microarchitectures/volcanic islands · revision 38538 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-47374a8069bb773b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvolcanic%20islands&oldid=38538","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2014,"unit":"","sourceId":"chipswiki-13194-r38538","location":"Amd/microarchitectures/volcanic islands · revision 38538 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-47374a8069bb773b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvolcanic%20islands&oldid=38538","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-13194-r38538","location":"Amd/microarchitectures/volcanic islands · revision 38538 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-47374a8069bb773b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvolcanic%20islands&oldid=38538","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Sea Islands","unit":"","sourceId":"chipswiki-13194-r38538","location":"Amd/microarchitectures/volcanic islands · revision 38538 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-47374a8069bb773b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvolcanic%20islands&oldid=38538","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Arctic Islands","unit":"","sourceId":"chipswiki-13194-r38538","location":"Amd/microarchitectures/volcanic islands · revision 38538 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-21. Not an independent measurement.","entityId":"cw-47374a8069bb773b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fvolcanic%20islands&oldid=38538","sourceDate":"2017-07-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-13194-r38538"],"url":"https://museum.vlsi.kr/objects/cw-47374a8069bb773b"},{"id":"cw-4758aa8fec62e638","name":"Exynos 8 Octa (8890)","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 8","year":2016,"architecture":"Mongoose 1","process":"14 nm","aliases":["Samsung exynos 8890"],"fields":[{"key":"Model name","value":"Exynos 8 Octa","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8890,"unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 12, 2015","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2016","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 8","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2300,"unit":"MHz","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1600,"unit":"MHz","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Mongoose 1","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Exynos M1","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":384,"unit":"KiB","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":128,"unit":"KiB","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-01-25. 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Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"1x256 KiB","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 2)","value":"16-way set associative","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-01-25. Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-3600","unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. 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Not an independent measurement.","entityId":"cw-4758aa8fec62e638","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F8890&oldid=1049","sourceDate":"2022-01-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-516-r1049","location":"Samsung/exynos/8890 · revision 1049 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-25. 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Not an independent measurement.","entityId":"cw-476b4be2e8f20892","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fhaswell%20(client)&oldid=97008","sourceDate":"2022-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Haswell H","unit":"","sourceId":"chipswiki-58-r97008","location":"Intel/microarchitectures/haswell (client) · revision 97008 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-12. 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Not an independent measurement.","entityId":"cw-476b4be2e8f20892","scope":"core name 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fhaswell%20(client)&oldid=97008","sourceDate":"2022-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Haswell MB","unit":"","sourceId":"chipswiki-58-r97008","location":"Intel/microarchitectures/haswell (client) · revision 97008 · {{microarchitecture}} / core name 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 6","note":"Source-reported parameter; source revision 2022-10-12. Not an independent measurement.","entityId":"cw-476b4be2e8f20892","scope":"core name 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fhaswell%20(client)&oldid=97008","sourceDate":"2022-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Haswell ULT","unit":"","sourceId":"chipswiki-58-r97008","location":"Intel/microarchitectures/haswell (client) · revision 97008 · {{microarchitecture}} / core name 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 7","note":"Source-reported parameter; source revision 2022-10-12. Not an independent measurement.","entityId":"cw-476b4be2e8f20892","scope":"core name 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fhaswell%20(client)&oldid=97008","sourceDate":"2022-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Haswell ULX","unit":"","sourceId":"chipswiki-58-r97008","location":"Intel/microarchitectures/haswell (client) · revision 97008 · {{microarchitecture}} / core name 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 8","note":"Source-reported parameter; source revision 2022-10-12. Not an independent measurement.","entityId":"cw-476b4be2e8f20892","scope":"core name 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fhaswell%20(client)&oldid=97008","sourceDate":"2022-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Ivy Bridge","unit":"","sourceId":"chipswiki-58-r97008","location":"Intel/microarchitectures/haswell (client) · revision 97008 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-12. Not an independent measurement.","entityId":"cw-476b4be2e8f20892","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fhaswell%20(client)&oldid=97008","sourceDate":"2022-10-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Broadwell","unit":"","sourceId":"chipswiki-58-r97008","location":"Intel/microarchitectures/haswell (client) · revision 97008 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-12. Not an independent measurement.","entityId":"cw-476b4be2e8f20892","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fhaswell%20(client)&oldid=97008","sourceDate":"2022-10-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-58-r97008"],"url":"https://museum.vlsi.kr/objects/cw-476b4be2e8f20892"},{"id":"cw-476d1ffc08236f6c","name":"i486DX4-75","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486DX4","year":1994,"architecture":"80486","process":"600 nm","aliases":["Intel 80486 486dx4-75"],"fields":[{"key":"Model name","value":"Intel i486DX4-75","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486DX4-75","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-75","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MA80486DX4-75","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MQ80486DX4-75","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"TQ80486DX475","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FC80486DX4-75","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FC80486DX4WB75","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / part number 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 6","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"part number 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 7, 1994","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486DX4","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":75,"unit":"MHz","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"25 MT/s","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK047","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK087","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK102","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX871","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX884","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK052","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / s-spec 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 6","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"s-spec 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SK100","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / s-spec 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 7","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"s-spec 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX870","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / s-spec 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 8","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"s-spec 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX883","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / s-spec 9","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 9","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"s-spec 9","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":600,"unit":"nm","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1600000,"unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8086-r25737","location":"Intel/80486/486dx4-75 · revision 25737 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-476d1ffc08236f6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx4-75&oldid=25737","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8086-r25737"],"url":"https://museum.vlsi.kr/objects/cw-476d1ffc08236f6c"},{"id":"cw-477680c221f35de7","name":"Am486DX4-100SV16B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX4S","year":1997,"architecture":"80486","process":"350 nm","aliases":["Amd am486 am486dx4-100sv16b"],"fields":[{"key":"Model name","value":"Am486DX4-100SV16B","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-100SV16B","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-100SV16B","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"S80486DX4-100SV16B","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 1997","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4S","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":100,"unit":"MHz","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am486DX4S","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8557-r26753","location":"Amd/am486/am486dx4-100sv16b · revision 26753 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-477680c221f35de7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8557-r26753"],"url":"https://museum.vlsi.kr/objects/cw-477680c221f35de7"},{"id":"cw-4783a75faa38621a","name":"Core i5-2450M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2450m","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2450m"],"fields":[{"key":"Model name","value":"Core i5-2450M","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2450M","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700995806","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700995606","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR06Z","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0CH","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 2012","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2012","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2450m","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. 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Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. 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Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-02-05. Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2450m&oldid=2125","sourceDate":"2021-02-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-828-r2125","location":"Intel/core i5/i5-2450m · revision 2125 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2021-02-05. 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Not an independent measurement.","entityId":"cw-4783a75faa38621a","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-02-05. 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Not an independent measurement.","entityId":"cw-47840e719c24e5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dib&oldid=26672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8479-r26672","location":"Amd/am9080/am9080a-2dib · revision 26672 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47840e719c24e5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dib&oldid=26672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8479-r26672","location":"Amd/am9080/am9080a-2dib · revision 26672 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47840e719c24e5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dib&oldid=26672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8479-r26672","location":"Amd/am9080/am9080a-2dib · revision 26672 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47840e719c24e5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dib&oldid=26672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8479-r26672","location":"Amd/am9080/am9080a-2dib · revision 26672 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47840e719c24e5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dib&oldid=26672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8479-r26672","location":"Amd/am9080/am9080a-2dib · revision 26672 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47840e719c24e5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dib&oldid=26672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8479-r26672","location":"Amd/am9080/am9080a-2dib · revision 26672 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47840e719c24e5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dib&oldid=26672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8479-r26672","location":"Amd/am9080/am9080a-2dib · revision 26672 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47840e719c24e5a0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dib&oldid=26672","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8479-r26672"],"url":"https://museum.vlsi.kr/objects/cw-47840e719c24e5a0"},{"id":"cw-47935803726ac5ba","name":"K10","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2007,"process":"65 nm","aliases":["Amd microarchitectures k10"],"fields":[{"key":"Architecture name","value":"K10","unit":"","sourceId":"chipswiki-548-r1130","location":"Amd/microarchitectures/k10 · revision 1130 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-47935803726ac5ba","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk10&oldid=1130","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-548-r1130","location":"Amd/microarchitectures/k10 · revision 1130 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-47935803726ac5ba","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk10&oldid=1130","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-548-r1130","location":"Amd/microarchitectures/k10 · revision 1130 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-47935803726ac5ba","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk10&oldid=1130","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"November 11, 2007","unit":"","sourceId":"chipswiki-548-r1130","location":"Amd/microarchitectures/k10 · revision 1130 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-47935803726ac5ba","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk10&oldid=1130","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-548-r1130","location":"Amd/microarchitectures/k10 · revision 1130 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-47935803726ac5ba","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk10&oldid=1130","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-548-r1130","location":"Amd/microarchitectures/k10 · revision 1130 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-47935803726ac5ba","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk10&oldid=1130","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-548-r1130","location":"Amd/microarchitectures/k10 · revision 1130 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-47935803726ac5ba","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk10&oldid=1130","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-548-r1130","location":"Amd/microarchitectures/k10 · revision 1130 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-47935803726ac5ba","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk10&oldid=1130","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":3,"unit":"","sourceId":"chipswiki-548-r1130","location":"Amd/microarchitectures/k10 · revision 1130 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-47935803726ac5ba","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk10&oldid=1130","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-548-r1130","location":"Amd/microarchitectures/k10 · revision 1130 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-47935803726ac5ba","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk10&oldid=1130","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"K8","unit":"","sourceId":"chipswiki-548-r1130","location":"Amd/microarchitectures/k10 · revision 1130 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-47935803726ac5ba","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk10&oldid=1130","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Bulldozer","unit":"","sourceId":"chipswiki-548-r1130","location":"Amd/microarchitectures/k10 · revision 1130 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-47935803726ac5ba","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk10&oldid=1130","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-548-r1130"],"url":"https://museum.vlsi.kr/objects/cw-47935803726ac5ba"},{"id":"cw-4797cfe9e5a84e40","name":"AMD-K6-III+/475ACZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III+ Mobile","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-iii+ amd-k6-iii+-475acz"],"fields":[{"key":"Model name","value":"AMD-K6-III+/475ACZ","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III+/475ACZ","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III+/475ACZ","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 18, 2000","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 18, 2000","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III+","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III+ Mobile","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":475,"unit":"MHz","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95 MT/s","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":3,"unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21400000,"unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8317-r26011","location":"Amd/k6-iii+/amd-k6-iii+-475acz · revision 26011 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4797cfe9e5a84e40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-475acz&oldid=26011","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8317-r26011"],"url":"https://museum.vlsi.kr/objects/cw-4797cfe9e5a84e40"},{"id":"cw-47baa5404c688046","name":"AMD-K6-233APR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Desktop K6","year":1997,"architecture":"K6","process":"350 nm","aliases":["Amd k6 amd-k6-233apr"],"fields":[{"key":"Model name","value":"AMD-K6-233APR","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-233APR","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-233APR","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1997","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1997","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Desktop K6","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":233.33,"unit":"MHz","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"6k86","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":162,"unit":"mm²","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.9,"unit":"V","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8293-r25981","location":"Amd/k6/amd-k6-233apr · revision 25981 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-47baa5404c688046","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-233apr&oldid=25981","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8293-r25981"],"url":"https://museum.vlsi.kr/objects/cw-47baa5404c688046"},{"id":"cw-47ce623bfaec6952","name":"Core i5-6200U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6200u"],"fields":[{"key":"Model name","value":"Core i5-6200U","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6200U","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066201930409","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2EY","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. 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Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. 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Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. 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Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. 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Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-02-27. 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Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. 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Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6200u&oldid=1000","sourceDate":"2022-02-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 520","unit":"","sourceId":"chipswiki-502-r1000","location":"Intel/core i5/i5-6200u · revision 1000 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. 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Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-27. Not an independent measurement.","entityId":"cw-47ce623bfaec6952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-502-r1000","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-47ce623bfaec6952"},{"id":"cw-47dff07bab657334","name":"Dimensity 1000","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","year":2020,"architecture":"Cortex-A77","process":"7 nm","aliases":["Mediatek dimensity 1000"],"fields":[{"key":"Model name","value":"Dimensity 1000","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":1000,"unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6889","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 26, 2019","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2020,"unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Dimensity","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2600,"unit":"MHz","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2-A","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A77","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A77","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":29.87,"unit":"GiB/s","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G77","unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":9,"unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-1064-r3057","location":"Mediatek/dimensity/1000 · revision 3057 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-03. Not an independent measurement.","entityId":"cw-47dff07bab657334","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F1000&oldid=3057","sourceDate":"2020-07-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1064-r3057"],"url":"https://museum.vlsi.kr/objects/cw-47dff07bab657334"},{"id":"cw-480a2f1d228e8e53","name":"Alchemy Au1210-400MGF","kind":"sku","entityType":"product-model","subtype":"cpu","company":"RMI","year":2007,"architecture":"Au1","aliases":["Alchemy au1210-400mgf"],"fields":[{"key":"Model name","value":"Alchemy Au1210-400MGF","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"RMI","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1210-400MGF","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1210-400MGF","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 9, 2007","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2007","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1000 mW","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.600 GB/s","unit":"","sourceId":"chipswiki-446-r927","location":"Alchemy/au1210-400mgf · revision 927 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-480a2f1d228e8e53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-446-r927"],"url":"https://museum.vlsi.kr/objects/cw-480a2f1d228e8e53"},{"id":"cw-4850c40448958953","name":"QorIQ P1010","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":2009,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1010"],"fields":[{"key":"Model name","value":"QorIQ P1010","unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1010","unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 16, 2008","unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2009,"unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":667,"unit":"MHz","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":800,"unit":"MHz","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4850c40448958953","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1010&oldid=25766","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":125,"unit":"°C","sourceId":"chipswiki-8107-r25766","location":"Freescale/qoriq/p1010 · revision 25766 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"shared","unit":"","sourceId":"chipswiki-7860-r25360","location":"Intel/core i7/i7-5775r · revision 25360 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5775r&oldid=25360","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-485df4be188f070d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7860-r25360","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-485df4be188f070d"},{"id":"cw-4879ad11ecd31b31","name":"Xeon E3-1235L v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1200 v5","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1235l v5"],"fields":[{"key":"Model name","value":"Xeon E3-1235L v5","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1235L v5","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201935807","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2CV","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LM","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1200 v5","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DT","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics P530","unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":400,"unit":"MHz","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7770-r25164","location":"Intel/xeon e3/e3-1235l v5 · revision 25164 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4879ad11ecd31b31","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7770-r25164"],"url":"https://museum.vlsi.kr/objects/cw-4879ad11ecd31b31"},{"id":"cw-487b2e1c57d07bb5","name":"Core i7-640LM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-600","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7 i7-640lm"],"fields":[{"key":"Model name","value":"Intel Core i7-640LM","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-640LM","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617003885AE","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2133.33,"unit":"MHz","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2933.33,"unit":"MHz","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBMK","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBSV","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":266,"unit":"MHz","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":566,"unit":"MHz","sourceId":"chipswiki-7851-r25350","location":"Intel/core i7/i7-640lm · revision 25350 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640lm&oldid=25350","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-487b2e1c57d07bb5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Acorn Computers","unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VC2588","unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VC2588","unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1985,"unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":6,"unit":"MHz","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv1","unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM1","unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MEMC","unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":24800,"unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":50,"unit":"mm²","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"","sourceId":"chipswiki-7635-r24891","location":"Vti/vl86cx/vc2588 · revision 24891 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-82","unit":"","sourceId":"chipswiki-31439-r92361","location":"Template:Packages/vti/plcc-82 · revision 92361 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-82&oldid=92361","sourceDate":"2017-07-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-31439-r92361","location":"Template:Packages/vti/plcc-82 · revision 92361 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-488d8dfa08638dba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-82&oldid=92361","sourceDate":"2017-07-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7635-r24891","chipswiki-31439-r92361"],"url":"https://museum.vlsi.kr/objects/cw-488d8dfa08638dba"},{"id":"cw-4899747c08fa73c5","name":"Xeon D-2183IT","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-2000","year":2018,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon d d-2183it"],"fields":[{"key":"Model name","value":"Xeon D-2183IT","unit":"","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2183IT","unit":"","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZQ","unit":"","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":100,"unit":"W","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7152-r22577","location":"Intel/xeon d/d-2183it · revision 22577 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-4899747c08fa73c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7920-r25459","location":"Intel/core i5/i5-6440eq · revision 25459 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6440eq&oldid=25459","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-48a5fa6b56d445b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2135","unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303533403","unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80673W2135","unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. 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Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x1 MiB","unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8.25,"unit":"MiB","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.375 MiB","unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-2530-r8687","location":"Intel/xeon w/w-2135 · revision 8687 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-14. Not an independent measurement.","entityId":"cw-48dd54ffa69be945","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2135&oldid=8687","sourceDate":"2019-05-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2530-r8687"],"url":"https://museum.vlsi.kr/objects/cw-48dd54ffa69be945"},{"id":"cw-4903ebc84ec54e1a","name":"CN5745-1000 SSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5745-1000bg1217-ssp"],"fields":[{"key":"Model name","value":"Cavium CN5745-1000 SSP","unit":"","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5745-1000 SSP","unit":"","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":160,"unit":"KiB","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x16 KiB","unit":"","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8176-r25835","location":"Cavium/octeon plus/cn5745-1000bg1217-ssp · revision 25835 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4903ebc84ec54e1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8176-r25835","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-4903ebc84ec54e1a"},{"id":"cw-490bdd31b30b2664","name":"Exynos M2","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Samsung","year":2017,"process":"10 nm","aliases":["Samsung microarchitectures m2"],"fields":[{"key":"Architecture name","value":"Mongoose 2","unit":"","sourceId":"chipswiki-3825-r12082","location":"Samsung/microarchitectures/m2 · revision 12082 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-490bdd31b30b2664","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm2&oldid=12082","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-3825-r12082","location":"Samsung/microarchitectures/m2 · revision 12082 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-490bdd31b30b2664","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm2&oldid=12082","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-3825-r12082","location":"Samsung/microarchitectures/m2 · revision 12082 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-490bdd31b30b2664","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm2&oldid=12082","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"February 23, 2017","unit":"","sourceId":"chipswiki-3825-r12082","location":"Samsung/microarchitectures/m2 · revision 12082 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-490bdd31b30b2664","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm2&oldid=12082","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-3825-r12082","location":"Samsung/microarchitectures/m2 · revision 12082 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-490bdd31b30b2664","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm2&oldid=12082","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":4,"unit":"","sourceId":"chipswiki-3825-r12082","location":"Samsung/microarchitectures/m2 · revision 12082 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-490bdd31b30b2664","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm2&oldid=12082","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":14,"unit":"","sourceId":"chipswiki-3825-r12082","location":"Samsung/microarchitectures/m2 · revision 12082 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-490bdd31b30b2664","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm2&oldid=12082","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-3825-r12082","location":"Samsung/microarchitectures/m2 · revision 12082 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-490bdd31b30b2664","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm2&oldid=12082","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-3825-r12082","location":"Samsung/microarchitectures/m2 · revision 12082 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-490bdd31b30b2664","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm2&oldid=12082","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3825-r12082","location":"Samsung/microarchitectures/m2 · revision 12082 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"cluster","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-490bdd31b30b2664","scope":"cluster","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm2&oldid=12082","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"M1","unit":"","sourceId":"chipswiki-3825-r12082","location":"Samsung/microarchitectures/m2 · revision 12082 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. Not an independent measurement.","entityId":"cw-490bdd31b30b2664","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm2&oldid=12082","sourceDate":"2019-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"M3","unit":"","sourceId":"chipswiki-3825-r12082","location":"Samsung/microarchitectures/m2 · revision 12082 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-21. 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Not an independent measurement.","entityId":"cw-4951d4e0675233c5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Fmicroarchitectures%2Ftriton&oldid=8508","sourceDate":"2019-05-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2485-r8508","location":"Marvell/microarchitectures/triton · revision 8508 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-21. Not an independent measurement.","entityId":"cw-4951d4e0675233c5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Fmicroarchitectures%2Ftriton&oldid=8508","sourceDate":"2019-05-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2019,"unit":"","sourceId":"chipswiki-2485-r8508","location":"Marvell/microarchitectures/triton · revision 8508 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-21. 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Not an independent measurement.","entityId":"cw-4951d4e0675233c5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Fmicroarchitectures%2Ftriton&oldid=8508","sourceDate":"2019-05-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-2485-r8508","location":"Marvell/microarchitectures/triton · revision 8508 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-21. 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Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-640M","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004152AE","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004152AE","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2010","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 13, 2010","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2799.99,"unit":"MHz","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3466.66,"unit":"MHz","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBTN","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBTP","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBZU","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-497b354f04395c7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-640m&oldid=25349","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7850-r25349","location":"Intel/core i7/i7-640m · revision 25349 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-49a17711559d0220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7872&oldid=21323","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6841-r21323","location":"Samsung/exynos/7872 · revision 21323 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-49a17711559d0220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7872&oldid=21323","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6841-r21323","location":"Samsung/exynos/7872 · revision 21323 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-49a17711559d0220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7872&oldid=21323","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6841-r21323","location":"Samsung/exynos/7872 · revision 21323 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-49a17711559d0220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7872&oldid=21323","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-6841-r21323","location":"Samsung/exynos/7872 · revision 21323 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-49a17711559d0220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7872&oldid=21323","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-6841-r21323","location":"Samsung/exynos/7872 · revision 21323 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-49a17711559d0220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7872&oldid=21323","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6841-r21323","location":"Samsung/exynos/7872 · revision 21323 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-49a17711559d0220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7872&oldid=21323","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6841-r21323"],"url":"https://museum.vlsi.kr/objects/cw-49a17711559d0220"},{"id":"cw-49acc2145ba1081f","name":"Alchemy Au1100-333MBI","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2002,"architecture":"Au1","process":"130 nm","aliases":["Alchemy au1100-333mbi"],"fields":[{"key":"Model name","value":"Alchemy Au1100-333MBI","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1100-333MBI","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBIBA","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBIBC","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBIBD","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBIBE","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBIBF","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2002","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BA","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BC","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BD","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BE","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"BF","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / core stepping 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 5","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"core stepping 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.22,"unit":"V","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.333 GB/s","unit":"","sourceId":"chipswiki-472-r953","location":"Alchemy/au1100-333mbi · revision 953 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-49acc2145ba1081f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-472-r953"],"url":"https://museum.vlsi.kr/objects/cw-49acc2145ba1081f"},{"id":"cw-4a0a019e573cf945","name":"z196","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2010,"process":"45 nm","aliases":["Ibm microarchitectures z196"],"fields":[{"key":"Architecture name","value":"z196","unit":"","sourceId":"chipswiki-13215-r38678","location":"Ibm/microarchitectures/z196 · revision 38678 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. 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Not an independent measurement.","entityId":"cw-4a0a019e573cf945","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz196&oldid=38678","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-13215-r38678","location":"Ibm/microarchitectures/z196 · revision 38678 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. 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Not an independent measurement.","entityId":"cw-4a0a019e573cf945","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz196&oldid=38678","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"z/Architecture","unit":"","sourceId":"chipswiki-13215-r38678","location":"Ibm/microarchitectures/z196 · revision 38678 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-4a0a019e573cf945","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz196&oldid=38678","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"z10","unit":"","sourceId":"chipswiki-13215-r38678","location":"Ibm/microarchitectures/z196 · revision 38678 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-4a0a019e573cf945","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz196&oldid=38678","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"z12","unit":"","sourceId":"chipswiki-13215-r38678","location":"Ibm/microarchitectures/z196 · revision 38678 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-4a0a019e573cf945","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz196&oldid=38678","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-13215-r38678"],"url":"https://museum.vlsi.kr/objects/cw-4a0a019e573cf945"},{"id":"cw-4a712626841c834c","name":"Core i7-5850HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5800","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core i7 i7-5850hq"],"fields":[{"key":"Model name","value":"Intel Core i7-5850HQ","unit":"","sourceId":"chipswiki-7858-r25358","location":"Intel/core i7/i7-5850hq · revision 25358 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4a712626841c834c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850hq&oldid=25358","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-5850HQ","unit":"","sourceId":"chipswiki-7858-r25358","location":"Intel/core i7/i7-5850hq · revision 25358 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4a712626841c834c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850hq&oldid=25358","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7858-r25358","location":"Intel/core i7/i7-5850hq · revision 25358 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4a712626841c834c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850hq&oldid=25358","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7858-r25358","location":"Intel/core i7/i7-5850hq · revision 25358 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4a712626841c834c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850hq&oldid=25358","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7858-r25358","location":"Intel/core i7/i7-5850hq · revision 25358 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4a712626841c834c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850hq&oldid=25358","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"shared","unit":"","sourceId":"chipswiki-7858-r25358","location":"Intel/core i7/i7-5850hq · revision 25358 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4a712626841c834c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-5850hq&oldid=25358","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4a712626841c834c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4a712626841c834c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4a712626841c834c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7858-r25358","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-4a712626841c834c"},{"id":"cw-4a78dda55ff8df05","name":"Alchemy Au1250-400MGD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"RMI","year":2007,"architecture":"Au1","aliases":["Alchemy au1250-400mgd"],"fields":[{"key":"Model name","value":"Alchemy Au1250-400MGD","unit":"","sourceId":"chipswiki-445-r926","location":"Alchemy/au1250-400mgd · revision 926 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-4a78dda55ff8df05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgd&oldid=926","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"RMI","unit":"","sourceId":"chipswiki-445-r926","location":"Alchemy/au1250-400mgd · revision 926 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-4a78dda55ff8df05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgd&oldid=926","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1250-400MGD","unit":"","sourceId":"chipswiki-445-r926","location":"Alchemy/au1250-400mgd · revision 926 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-4a78dda55ff8df05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgd&oldid=926","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-445-r926","location":"Alchemy/au1250-400mgd · revision 926 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-4a78dda55ff8df05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgd&oldid=926","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 9, 2007","unit":"","sourceId":"chipswiki-445-r926","location":"Alchemy/au1250-400mgd · revision 926 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-4a78dda55ff8df05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgd&oldid=926","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2007","unit":"","sourceId":"chipswiki-445-r926","location":"Alchemy/au1250-400mgd · revision 926 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-4a78dda55ff8df05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgd&oldid=926","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-445-r926","location":"Alchemy/au1250-400mgd · revision 926 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-4a78dda55ff8df05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgd&oldid=926","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-445-r926","location":"Alchemy/au1250-400mgd · revision 926 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-4a78dda55ff8df05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgd&oldid=926","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-445-r926","location":"Alchemy/au1250-400mgd · revision 926 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-4a78dda55ff8df05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgd&oldid=926","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.600 GB/s","unit":"","sourceId":"chipswiki-445-r926","location":"Alchemy/au1250-400mgd · revision 926 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-4a78dda55ff8df05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgd&oldid=926","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-445-r926"],"url":"https://museum.vlsi.kr/objects/cw-4a78dda55ff8df05"},{"id":"cw-4abd56d23ece64f0","name":"CN3860-400 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3860-400bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3860-400 NSP","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3860-400 NSP","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3860-400BG1521-NSP","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x8 KiB","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8201-r25860","location":"Cavium/octeon/cn3860-400bg1521-nsp · revision 25860 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-400bg1521-nsp&oldid=25860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4abd56d23ece64f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8201-r25860","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-4abd56d23ece64f0"},{"id":"cw-4ae951ce27509159","name":"Xeon E5-1680 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-1000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-1680 v4"],"fields":[{"key":"Model name","value":"Xeon E5-1680 v4","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-1680 v4","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002044401","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-1000","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2P8","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP Workstation","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":20,"unit":"MiB","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2.5 MiB","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7588-r24672","location":"Intel/xeon e5/e5-1680 v4 · revision 24672 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-4ae951ce27509159","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-1680%20v4&oldid=24672","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7588-r24672"],"url":"https://museum.vlsi.kr/objects/cw-4ae951ce27509159"},{"id":"cw-4b17910ba2bf0c22","name":"Core i5-8200Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2018,"architecture":"Amber Lake","process":"14 nm","aliases":["Intel core i5 i5-8200y"],"fields":[{"key":"Model name","value":"Core i5-8200Y","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8200Y","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702739846","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRD22","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 28, 2018","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 28, 2018","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-10-31. 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Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Amber Lake","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Amber Lake","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Amber Lake Y","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":5,"unit":"W","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 615","unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":960,"unit":"MHz","sourceId":"chipswiki-4496-r14614","location":"Intel/core i5/i5-8200y · revision 14614 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-31. Not an independent measurement.","entityId":"cw-4b17910ba2bf0c22","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8200y&oldid=14614","sourceDate":"2018-10-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4496-r14614"],"url":"https://museum.vlsi.kr/objects/cw-4b17910ba2bf0c22"},{"id":"cw-4b76323aba4a3e4d","name":"Helio G80","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio G","year":2020,"architecture":"Cortex-A75","process":"12 nm","aliases":["Mediatek helio g80"],"fields":[{"key":"Model name","value":"Helio G80","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G80","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 3, 2020","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 3, 2020","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio G","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A75","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A75","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3600","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.41,"unit":"GiB/s","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G52","unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":950,"unit":"MHz","sourceId":"chipswiki-1317-r4415","location":"Mediatek/helio/g80 · revision 4415 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-04. Not an independent measurement.","entityId":"cw-4b76323aba4a3e4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fg80&oldid=4415","sourceDate":"2020-02-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1317-r4415"],"url":"https://museum.vlsi.kr/objects/cw-4b76323aba4a3e4d"},{"id":"cw-4b77a7ceeeea6830","name":"Xeon D-1587","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1587"],"fields":[{"key":"Model name","value":"Xeon D-1587","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1587","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402570403","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2M1","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2016","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2016","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2300,"unit":"MHz","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Y0","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x256 KiB","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24,"unit":"MiB","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.5 MiB","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3668-r10994","location":"Intel/xeon d/d-1587 · revision 10994 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-4b77a7ceeeea6830","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1587&oldid=10994","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3668-r10994"],"url":"https://museum.vlsi.kr/objects/cw-4b77a7ceeeea6830"},{"id":"cw-4b8e02fa582de682","name":"Am486DX2-100","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2","year":1994,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx2-100"],"fields":[{"key":"Model name","value":"Am486DX2-100","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-100","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1994,"unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 1994","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":100,"unit":"MHz","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"50 MT/s","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8572-r26770","location":"Amd/am486/am486dx2-100 · revision 26770 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4b8e02fa582de682","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8572-r26770"],"url":"https://museum.vlsi.kr/objects/cw-4b8e02fa582de682"},{"id":"cw-4bb3ca6259173e4a","name":"Core i3-2365M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2365m"],"fields":[{"key":"Model name","value":"Core i3-2365M","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2365M","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701313000","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0U3","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2012","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 2012","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4bb3ca6259173e4a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2365m&oldid=25586","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8005-r25586","location":"Intel/core i3/i3-2365m · revision 25586 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14622-r44683","location":"Amd/am186ex/am186es–25vc\\w · revision 44683 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4bc5601f949a153a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14622-r44683"],"url":"https://museum.vlsi.kr/objects/cw-4bc5601f949a153a"},{"id":"cw-4c821f7566dd2551","name":"Core M 5Y10","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2014,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core m 5y10"],"fields":[{"key":"Model name","value":"Core M 5Y10","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5Y10","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065802062002","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 2, 2014","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core M","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2,"unit":"GHz","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR23C","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell Y","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"3D","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"E0","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1300000000,"unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":82,"unit":"mm²","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1234","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"MiB","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7817-r25266","location":"Intel/core m/5y10 · revision 25266 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c821f7566dd2551","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2F5y10&oldid=25266","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7817-r25266"],"url":"https://museum.vlsi.kr/objects/cw-4c821f7566dd2551"},{"id":"cw-4c8dfc3d3ace64b9","name":"CN5850-900 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5850-900bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5850-900 EXP","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5850-900 EXP","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5850-900BG1521-EXP","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8128-r25787","location":"Cavium/octeon plus/cn5850-900bg1521-exp · revision 25787 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-900bg1521-exp&oldid=25787","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4c8dfc3d3ace64b9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8128-r25787","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-4c8dfc3d3ace64b9"},{"id":"cw-4c9ccaeefe0b4ada","name":"Xeon Gold 6146","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6146"],"fields":[{"key":"Model name","value":"Xeon Gold 6146","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6146,"unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-4c9ccaeefe0b4ada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6146&oldid=4950","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1498-r4950","location":"Intel/xeon gold/6146 · revision 4950 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-4cb90ff07467a98c","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fvulcan&oldid=5956","sourceDate":"2019-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"XLP II","unit":"","sourceId":"chipswiki-1710-r5956","location":"Cavium/microarchitectures/vulcan · revision 5956 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-05. Not an independent measurement.","entityId":"cw-4cb90ff07467a98c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fvulcan&oldid=5956","sourceDate":"2019-10-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Triton","unit":"","sourceId":"chipswiki-1710-r5956","location":"Cavium/microarchitectures/vulcan · revision 5956 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-05. Not an independent measurement.","entityId":"cw-4cb90ff07467a98c","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fvulcan&oldid=5956","sourceDate":"2019-10-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1710-r5956"],"url":"https://museum.vlsi.kr/objects/cw-4cb90ff07467a98c"},{"id":"cw-4cbcee0d222945eb","name":"J8086-1B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"J8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 j8086-1b"],"fields":[{"key":"Model name","value":"AMD J8086-1B","unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J8086-1B","unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"J8086-1B","unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"J8086","unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":10,"unit":"MHz","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-44","unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cbcee0d222945eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8506-r26699","location":"Amd/am8086/j8086-1b · revision 26699 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1567","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402570603","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2M3","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2016","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2016","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Y0","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x256 KiB","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":18,"unit":"MiB","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.5 MiB","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3729-r11431","location":"Intel/xeon d/d-1567 · revision 11431 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-4cbe67262a417310","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3729-r11431"],"url":"https://museum.vlsi.kr/objects/cw-4cbe67262a417310"},{"id":"cw-4cd2d5397d44b9a4","name":"4040","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":1974,"process":"10 μm","aliases":["Intel mcs-40 4040"],"fields":[{"key":"Model name","value":4040,"unit":"","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4040,"unit":"","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"C4040","unit":"","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D4040","unit":"","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"P4040","unit":"","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1974,"unit":"","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MCS-40","unit":"","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":740,"unit":"kHz","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"10 μm","unit":"","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3000,"unit":"","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":4,"unit":"bit","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"KiB","sourceId":"chipswiki-7811-r25251","location":"Intel/mcs-40/4040 · revision 25251 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4cd2d5397d44b9a4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmcs-40%2F4040&oldid=25251","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7811-r25251"],"url":"https://museum.vlsi.kr/objects/cw-4cd2d5397d44b9a4"},{"id":"cw-4cdc369cd1b938d0","name":"EPYC 7713","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7713"],"fields":[{"key":"Model name","value":"EPYC 7713","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7713,"unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000344","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000344WOF","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3675,"unit":"MHz","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":64,"unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":128,"unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":225,"unit":"W","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"MiB","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64 × 32 KiB","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"MiB","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64 × 32 KiB","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"64 × 512 KiB","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 32 MiB","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-738-r1759","location":"Amd/epyc/7713 · revision 1759 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-4cdc369cd1b938d0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7713&oldid=1759","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-738-r1759"],"url":"https://museum.vlsi.kr/objects/cw-4cdc369cd1b938d0"},{"id":"cw-4d31e0a38fea6cc4","name":"VY86C710A2","kind":"sku","entityType":"product-model","subtype":"soc","company":"Arm","year":1995,"architecture":"ARM7","process":"0.5 µm","aliases":["Vti vl86cx vy86c710a2"],"fields":[{"key":"Model name","value":"VY86C710A2","unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VY86C710A2","unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C710A2","unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C710A-2","unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":28,"unit":"MHz","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv3","unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM7","unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM710","unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.5,"unit":"µm","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":570295,"unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":34,"unit":"mm²","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-7623-r24878","location":"Vti/vl86cx/vy86c710a2 · revision 24878 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-144","unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":144,"unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":20,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":20,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d31e0a38fea6cc4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7623-r24878","chipswiki-31401-r92231"],"url":"https://museum.vlsi.kr/objects/cw-4d31e0a38fea6cc4"},{"id":"cw-4d6aca16e8401d93","name":"AMD-K6-III/400ACK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III Mobile","year":1999,"architecture":"K6-III","process":"0.25 µm","aliases":["Amd k6-iii-p amd-k6-iii-400ack"],"fields":[{"key":"Model name","value":"AMD-K6-III/400ACK","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III/400ACK","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III/400ACK","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III-P","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III Mobile","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.999,"unit":"MHz","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sharptooth","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":9,"unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21300000,"unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118,"unit":"mm²","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8306-r25996","location":"Amd/k6-iii-p/amd-k6-iii-400ack · revision 25996 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4d6aca16e8401d93","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-400ack&oldid=25996","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8306-r25996"],"url":"https://museum.vlsi.kr/objects/cw-4d6aca16e8401d93"},{"id":"cw-4d8192625955f8ef","name":"Xeon Gold 6148","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6148"],"fields":[{"key":"Model name","value":"Xeon Gold 6148","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6148,"unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806736148","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303406200","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3B6","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":27.5,"unit":"MiB","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x1.375 MiB","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1495-r4947","location":"Intel/xeon gold/6148 · revision 4947 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-4d8192625955f8ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6148&oldid=4947","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1495-r4947"],"url":"https://museum.vlsi.kr/objects/cw-4d8192625955f8ef"},{"id":"cw-4d8df5b000f36235","name":"POWER9 02CY414","kind":"sku","entityType":"product-model","subtype":"cpu","company":"IBM","series":"POWER9","year":2017,"architecture":"POWER9","process":"14 nm","aliases":["Ibm power 02cy414"],"fields":[{"key":"Model name","value":"02CY414","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02CY414","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02CY414","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.25,"unit":"GHz","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":22,"unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":88,"unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":160,"unit":"W","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.375,"unit":"MiB","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":704,"unit":"KiB","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":704,"unit":"KiB","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"22x32 KiB","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5.5,"unit":"MiB","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"11x512 KiB","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":110,"unit":"MiB","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"11x10 MiB","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3944-r12584","location":"Ibm/power/02cy414 · revision 12584 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-4d8df5b000f36235","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy414&oldid=12584","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3944-r12584"],"url":"https://museum.vlsi.kr/objects/cw-4d8df5b000f36235"},{"id":"cw-4da63c88691169e8","name":"AM9080ACC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080acc"],"fields":[{"key":"Model name","value":"AMD AM9080ACC","unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080ACC","unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080ACC","unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.083,"unit":"MHz","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8471-r26664","location":"Amd/am9080/am9080acc · revision 26664 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4da63c88691169e8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8471-r26664"],"url":"https://museum.vlsi.kr/objects/cw-4da63c88691169e8"},{"id":"cw-4ddaa9bc983d1e0e","name":"Athlon MP 2000+","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2002,"architecture":"K7","process":"180 nm","aliases":["Amd athlon mp amp2000dms3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 2000+","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 2000+","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMP2000DMS3C","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 13, 2002","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 13, 2002","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1667,"unit":"MHz","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Palomino","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37500000,"unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":128,"unit":"mm²","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":66,"unit":"W","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8454-r26647","location":"Amd/athlon mp/amp2000dms3c · revision 26647 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp2000dms3c&oldid=26647","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ddaa9bc983d1e0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3840-600 NSP","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3840-600BG1521-NSP","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8213-r25872","location":"Cavium/octeon/cn3840-600bg1521-nsp · revision 25872 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4e0820ff96ea9ca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8213-r25872","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-4e0820ff96ea9ca5"},{"id":"cw-4e0bdd8d70ee7b89","name":"Ryzen Embedded V1202B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"V1000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen embedded v1202b"],"fields":[{"key":"Model name","value":"Ryzen Embedded V1202B","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"V1202B","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YE1202C4T2OFB","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"V1000","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Great Horned Owl","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-927-r2551","location":"Amd/ryzen embedded/v1202b · revision 2551 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","sourceDate":"2020-10-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-16. Not an independent measurement.","entityId":"cw-4e0bdd8d70ee7b89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-927-r2551","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-4e0bdd8d70ee7b89"},{"id":"cw-4e4f9c890beb2580","name":"Exynos 4212","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 4","year":2011,"architecture":"Cortex-A9","process":"32 nm","aliases":["Samsung exynos 4212"],"fields":[{"key":"Model name","value":"Exynos 4212","unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4212,"unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 29, 2011","unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 29, 2011","unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 4","unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A9","unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A9","unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6853-r21361","location":"Samsung/exynos/4212 · revision 21361 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-4e4f9c890beb2580","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6853-r21361"],"url":"https://museum.vlsi.kr/objects/cw-4e4f9c890beb2580"},{"id":"cw-4e62a5be04775d36","name":"Ryzen Threadripper PRO 5995WX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5900","year":2022,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen threadripper pro 5995wx"],"fields":[{"key":"Model name","value":"Ryzen Threadripper PRO 5995WX","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5995WX","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000444","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 8, 2022","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Threadripper","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5900,"unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"WRX80","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chagall","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":64,"unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":128,"unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":280,"unit":"W","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"MiB","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64 × 32 KiB","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"MiB","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64 × 32 KiB","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"64 × 512 KiB","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 32 MiB","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"204.8 GB/s","unit":"","sourceId":"chipswiki-391-r837","location":"Amd/ryzen threadripper/pro 5995wx · revision 837 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OLGA","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.87,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":75.4,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":58.5,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":6.26,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-4e62a5be04775d36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-391-r837","chipswiki-31095-r91554"],"url":"https://museum.vlsi.kr/objects/cw-4e62a5be04775d36"},{"id":"cw-4e6bbbfca0f60c0c","name":"EPYC Embedded 3401","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc embedded 3401"],"fields":[{"key":"Model name","value":"EPYC Embedded 3401","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3401,"unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC Embedded","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1850,"unit":"MHz","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Snowy Owl","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9600000000,"unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1536,"unit":"KiB","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16 × 64 KiB","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16 × 512 KiB","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 8 MiB","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"85.33 GB/s","unit":"","sourceId":"chipswiki-404-r874","location":"Amd/epyc embedded/3401 · revision 874 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SP4","unit":"","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OBGA","unit":"","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":45,"unit":"mm","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-4e6bbbfca0f60c0c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-404-r874","chipswiki-31097-r91556"],"url":"https://museum.vlsi.kr/objects/cw-4e6bbbfca0f60c0c"},{"id":"cw-4e7dc95cfd23e49f","name":"Vector Engine Type 10BE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"NEC","series":"Type 10E","year":2020,"architecture":"SX-Aurora","process":"16 nm","aliases":["Nec vector engine type 10be"],"fields":[{"key":"Model name","value":"VE Type 10BE","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"NEC","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Type 10BE","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 2019","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2020","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Vector Engine","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Type 10E","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1408,"unit":"MHz","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"SX-Aurora","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"SX-Aurora TSUBASA","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":493.68,"unit":"mm²","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":48,"unit":"GiB","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"HBM2-1800","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":6,"unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":48,"unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1,382 GB/s","unit":"","sourceId":"chipswiki-1591-r5323","location":"Nec/vector engine/type 10be · revision 5323 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-4e7dc95cfd23e49f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010be&oldid=5323","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1591-r5323"],"url":"https://museum.vlsi.kr/objects/cw-4e7dc95cfd23e49f"},{"id":"cw-4ea505f9f92b7680","name":"CN3830-500 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3830-500bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN3830-500 SCP","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3830-500 SCP","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8224-r25883","location":"Cavium/octeon/cn3830-500bg1521-scp · revision 25883 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ea505f9f92b7680","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-scp&oldid=25883","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1558L v5","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500 v5","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"N0","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Pro Graphics P555","unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-7756-r25138","location":"Intel/xeon e3/e3-1558l v5 · revision 25138 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1558l%20v5&oldid=25138","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ec6994b9638d94f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7756-r25138","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-4ec6994b9638d94f"},{"id":"cw-4ed08c8a54b1b128","name":"K6-2/380AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-380afr"],"fields":[{"key":"Model name","value":"K6-2/380AFR","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/380AFR","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/380AFR","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 1999","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":380,"unit":"MHz","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95 MT/s","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8359-r26054","location":"Amd/k6-2/k6-2-380afr · revision 26054 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4ed08c8a54b1b128","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afr&oldid=26054","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8359-r26054"],"url":"https://museum.vlsi.kr/objects/cw-4ed08c8a54b1b128"},{"id":"cw-4ef928dd333775ec","name":"Kunpeng 920-3226","kind":"sku","entityType":"product-model","subtype":"cpu","company":"HiSilicon","series":"920","year":2019,"architecture":"TaiShan v110","aliases":["Hisilicon kunpeng 920-3226"],"fields":[{"key":"Model name","value":"Kunpeng 920-3226","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"920-3226","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 26, 2019","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 26, 2019","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Hi16xx","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":920,"unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"TaiShan v110","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"TaiShan v110","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":20000000000,"unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x64 KiB","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"MiB","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x64 KiB","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x512 KiB","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"32x1 MiB","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-2911-r9697","location":"Hisilicon/kunpeng/920-3226 · revision 9697 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-06. Not an independent measurement.","entityId":"cw-4ef928dd333775ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-3226&oldid=9697","sourceDate":"2019-05-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2911-r9697"],"url":"https://museum.vlsi.kr/objects/cw-4ef928dd333775ec"},{"id":"cw-4efb8dce6c6c96bf","name":"CN3840-500 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3840-500bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3840-500 NSP","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3840-500 NSP","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3840-500BG1521-NSP","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x8 KiB","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8216-r25875","location":"Cavium/octeon/cn3840-500bg1521-nsp · revision 25875 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-nsp&oldid=25875","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4efb8dce6c6c96bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8216-r25875","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-4efb8dce6c6c96bf"},{"id":"cw-4f00adbee943e569","name":"KaiXian KX-U5580M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Zhaoxin","series":"KX-5000","year":2017,"architecture":"WuDaoKou","process":"28 nm","aliases":["Zhaoxin kaixian kx-u5580m"],"fields":[{"key":"Model name","value":"KaiXian KX-U5580M","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Zhaoxin","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"HLMC","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"KX-U5580M","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KX-U5580M","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"KaiXian","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"KX-5000","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"WuDaoKou","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2100000000,"unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":187,"unit":"mm²","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"32-way set associative","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5649-r18547","location":"Zhaoxin/kaixian/kx-u5580m · revision 18547 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-4f00adbee943e569","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5649-r18547"],"url":"https://museum.vlsi.kr/objects/cw-4f00adbee943e569"},{"id":"cw-4f4943c7f823dc92","name":"Core i5-2410M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2410m"],"fields":[{"key":"Model name","value":"Core i5-2410M","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2410M","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700845205","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700845406","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04B","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04G","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f4943c7f823dc92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2410m&oldid=25513","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7962-r25513","location":"Intel/core i5/i5-2410m · revision 25513 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":610,"unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"88AP610","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2009","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 5, 2010","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"ARMADA 600","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":600,"unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv6","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sheeva PJ4","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"ARMADA","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sheeva PJ4","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":55,"unit":"nm","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCCBGA-640","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCCBGA","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":7.942,"unit":"GiB/s","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"GC860","unit":"","sourceId":"chipswiki-7676-r24971","location":"Marvell/armada/610 · revision 24971 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-4f91ca92380cba97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F610&oldid=24971","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7676-r24971"],"url":"https://museum.vlsi.kr/objects/cw-4f91ca92380cba97"},{"id":"cw-4f960766efe04427","name":"80486","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":1989,"process":"1 µm","aliases":["Intel microarchitectures 80486"],"fields":[{"key":"Architecture name","value":80486,"unit":"","sourceId":"chipswiki-8770-r27263","location":"Intel/microarchitectures/80486 · revision 27263 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4f960766efe04427","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80486&oldid=27263","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8770-r27263","location":"Intel/microarchitectures/80486 · revision 27263 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4f960766efe04427","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80486&oldid=27263","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8770-r27263","location":"Intel/microarchitectures/80486 · revision 27263 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4f960766efe04427","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80486&oldid=27263","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8770-r27263","location":"Intel/microarchitectures/80486 · revision 27263 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4f960766efe04427","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80486&oldid=27263","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"April 10, 1989","unit":"","sourceId":"chipswiki-8770-r27263","location":"Intel/microarchitectures/80486 · revision 27263 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4f960766efe04427","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80486&oldid=27263","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-8770-r27263","location":"Intel/microarchitectures/80486 · revision 27263 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4f960766efe04427","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80486&oldid=27263","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8770-r27263","location":"Intel/microarchitectures/80486 · revision 27263 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4f960766efe04427","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80486&oldid=27263","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":600,"unit":"nm","sourceId":"chipswiki-8770-r27263","location":"Intel/microarchitectures/80486 · revision 27263 · {{microarchitecture}} / process 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 3","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4f960766efe04427","scope":"process 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80486&oldid=27263","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8770-r27263","location":"Intel/microarchitectures/80486 · revision 27263 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4f960766efe04427","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80486&oldid=27263","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":80386,"unit":"","sourceId":"chipswiki-8770-r27263","location":"Intel/microarchitectures/80486 · revision 27263 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4f960766efe04427","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80486&oldid=27263","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"P5","unit":"","sourceId":"chipswiki-8770-r27263","location":"Intel/microarchitectures/80486 · revision 27263 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4f960766efe04427","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80486&oldid=27263","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"K5","unit":"","sourceId":"chipswiki-8770-r27263","location":"Intel/microarchitectures/80486 · revision 27263 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-4f960766efe04427","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80486&oldid=27263","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8770-r27263"],"url":"https://museum.vlsi.kr/objects/cw-4f960766efe04427"},{"id":"cw-4fc5cf2a4033b532","name":"K3V1","kind":"sku","entityType":"product-model","subtype":"soc","company":"HiSilicon","year":2008,"architecture":"ARM9","process":"0.18 µm","aliases":["Hisilicon k3 k3v1"],"fields":[{"key":"Model name","value":"K3V1","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K3V1","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Hi3611","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2008","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2008","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K3","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv5","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":200000000,"unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. 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Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. 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Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR","unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-5610-r18430","location":"Hisilicon/k3/k3v1 · revision 18430 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fk3%2Fk3v1&oldid=18430","sourceDate":"2018-06-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TFBGA-460","unit":"","sourceId":"chipswiki-31403-r92244","location":"Template:Packages/hisilicon/tfbga-460 · revision 92244 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. 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Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-460&oldid=92244","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31403-r92244","location":"Template:Packages/hisilicon/tfbga-460 · revision 92244 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. Not an independent measurement.","entityId":"cw-4fc5cf2a4033b532","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fhisilicon%2Ftfbga-460&oldid=92244","sourceDate":"2017-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":14,"unit":"mm","sourceId":"chipswiki-31403-r92244","location":"Template:Packages/hisilicon/tfbga-460 · revision 92244 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-06-04. 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Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ES–25KI\\W","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ES–25KI\\W","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14623-r44684","location":"Amd/am186ex/am186es–25ki\\w · revision 44684 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-4fd2b9db63215eb4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14623-r44684"],"url":"https://museum.vlsi.kr/objects/cw-4fd2b9db63215eb4"},{"id":"cw-50029df47f20b8b0","name":"Ryzen 5 3500X","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":null,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 3500x"],"fields":[{"key":"Model name","value":"Ryzen 5 3500X","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3500X","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000158","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Matisse","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x16 MiB","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3000","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-504-r1002","location":"Amd/ryzen 5/3500x · revision 1002 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","sourceDate":"2022-02-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-22. Not an independent measurement.","entityId":"cw-50029df47f20b8b0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-504-r1002","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-50029df47f20b8b0"},{"id":"cw-501cc6c9891c540a","name":"Core i5-6300U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6300u"],"fields":[{"key":"Model name","value":"Core i5-6300U","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6300U","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066201924931","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2F0","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-501cc6c9891c540a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300u&oldid=25465","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7926-r25465","location":"Intel/core i5/i5-6300u · revision 25465 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-506061e8994e5c66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2540lm&oldid=25498","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7950-r25498","location":"Intel/core i5/i5-2540lm · revision 25498 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P8086","unit":"","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PDIP-40","unit":"","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PDIP","unit":"","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8492-r26685","location":"Amd/am8086/p8086-2b · revision 26685 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50664ace9ab37e10","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2b&oldid=26685","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8492-r26685"],"url":"https://museum.vlsi.kr/objects/cw-50664ace9ab37e10"},{"id":"cw-50a04db6ac8add7f","name":"Xeon E3-1205 v6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1200 v6","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel xeon e3 e3-1205 v6"],"fields":[{"key":"Model name","value":"Xeon E3-1205 v6","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1205 v6","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8067702871025","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR32D","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 28, 2017","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 28, 2017","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1200 v6","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake DT","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1866","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics P630","unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7773-r25171","location":"Intel/xeon e3/e3-1205 v6 · revision 25171 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-50a04db6ac8add7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1205%20v6&oldid=25171","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7773-r25171"],"url":"https://museum.vlsi.kr/objects/cw-50a04db6ac8add7f"},{"id":"cw-50b709ef9200d77d","name":"Alchemy Au1250-500MGF","kind":"sku","entityType":"product-model","subtype":"cpu","company":"RMI","year":2007,"architecture":"Au1","aliases":["Alchemy au1250-500mgf"],"fields":[{"key":"Model name","value":"Alchemy Au1250-500MGF","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"RMI","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 9, 2007","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1400 mW","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"2 GB/s","unit":"","sourceId":"chipswiki-442-r923","location":"Alchemy/au1250-500mgf · revision 923 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-50b709ef9200d77d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-442-r923"],"url":"https://museum.vlsi.kr/objects/cw-50b709ef9200d77d"},{"id":"cw-50caf251dd6beecc","name":"Core i3-7100E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7100","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7100e"],"fields":[{"key":"Model name","value":"Core i3-7100E","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7100E","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8067702999007","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR34V","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7100","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-6422-r20023","location":"Intel/core i3/i3-7100e · revision 20023 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-50caf251dd6beecc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6422-r20023","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-50caf251dd6beecc"},{"id":"cw-512f43d26c258017","name":"AMD-K6/266ADZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Mobile K6","year":1998,"architecture":"K6","process":"250 nm","aliases":["Amd k6 amd-k6 266adz"],"fields":[{"key":"Model name","value":"AMD-K6/266ADZ","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6/266ADZ","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6/266ADZ","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 1998","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 5, 1998","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Mobile K6","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266.66,"unit":"MHz","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Little Foot","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":68,"unit":"mm²","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.1,"unit":"V","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8287-r25974","location":"Amd/k6/amd-k6/266adz · revision 25974 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-512f43d26c258017","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266adz&oldid=25974","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8287-r25974"],"url":"https://museum.vlsi.kr/objects/cw-512f43d26c258017"},{"id":"cw-518c3f80cbf5c611","name":"J8086-2","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"J8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 j8086-2"],"fields":[{"key":"Model name","value":"AMD J8086-2","unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J8086-2","unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"J8086","unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-44","unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-518c3f80cbf5c611","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8505-r26698","location":"Amd/am8086/j8086-2 · revision 26698 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7167u&oldid=25540","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7968-r25540","location":"Intel/core i3/i3-7167u · revision 25540 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7167u&oldid=25540","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7968-r25540","location":"Intel/core i3/i3-7167u · revision 25540 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7167u&oldid=25540","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7167U","unit":"","sourceId":"chipswiki-7968-r25540","location":"Intel/core i3/i3-7167u · revision 25540 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7167u&oldid=25540","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR361","unit":"","sourceId":"chipswiki-7968-r25540","location":"Intel/core i3/i3-7167u · revision 25540 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7167u&oldid=25540","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7968-r25540","location":"Intel/core i3/i3-7167u · revision 25540 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7167u&oldid=25540","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7968-r25540","location":"Intel/core i3/i3-7167u · revision 25540 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7167u&oldid=25540","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7968-r25540","location":"Intel/core i3/i3-7167u · revision 25540 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7167u&oldid=25540","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7968-r25540","location":"Intel/core i3/i3-7167u · revision 25540 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7167u&oldid=25540","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7968-r25540","location":"Intel/core i3/i3-7167u · revision 25540 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7167u&oldid=25540","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7968-r25540","location":"Intel/core i3/i3-7167u · revision 25540 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7167u&oldid=25540","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7968-r25540","location":"Intel/core i3/i3-7167u · revision 25540 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7167u&oldid=25540","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7968-r25540","location":"Intel/core i3/i3-7167u · revision 25540 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51d77b5d79f86e79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7968-r25540","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-51d77b5d79f86e79"},{"id":"cw-51e9ae2093c736b6","name":"i486DX-50","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486DX","year":1991,"architecture":"80486","process":"1 µm","aliases":["Intel 80486 486dx-50"],"fields":[{"key":"Model name","value":"Intel i486DX-50","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486DX-50","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX-50","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 24, 1991","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486DX","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"50 MT/s","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX408","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX409","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX518","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX546","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX547","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX705","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / s-spec 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 6","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"s-spec 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX710","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / s-spec 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 7","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"s-spec 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SXE69","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / s-spec 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 8","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"s-spec 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8090-r25742","location":"Intel/80486/486dx-50 · revision 25742 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51e9ae2093c736b6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-50&oldid=25742","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8090-r25742"],"url":"https://museum.vlsi.kr/objects/cw-51e9ae2093c736b6"},{"id":"cw-51ea7b93f4f79cd7","name":"Core i7-2720QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2720qm"],"fields":[{"key":"Model name","value":"Core i7-2720QM","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2720QM","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700836011","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR014","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR00W","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 2011","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2011","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7877-r25381","location":"Intel/core i7/i7-2720qm · revision 25381 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2720qm&oldid=25381","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"FCBGA-1224","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"BGA","unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1224,"unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":0.65,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":58.5,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":1.347,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-51ea7b93f4f79cd7","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"TRX40","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Castle Peak","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":48,"unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":96,"unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":280,"unit":"W","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":3,"unit":"MiB","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"48x32 KiB","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"48x32 KiB","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"48x512 KiB","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":95.37,"unit":"GiB/s","sourceId":"chipswiki-1099-r3249","location":"Amd/ryzen threadripper/3980x · revision 3249 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-01. Not an independent measurement.","entityId":"cw-521249dcc0575826","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2F3980x&oldid=3249","sourceDate":"2020-06-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1099-r3249"],"url":"https://museum.vlsi.kr/objects/cw-521249dcc0575826"},{"id":"cw-522867b04d14d493","name":"Core i3-7300T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7300","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7300t"],"fields":[{"key":"Model name","value":"Core i3-7300T","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7300T","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80677I37300T","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80677I37300T","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35M","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7300","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":92,"unit":"°C","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7967-r25538","location":"Intel/core i3/i3-7300t · revision 25538 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-522867b04d14d493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7300t&oldid=25538","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7967-r25538"],"url":"https://museum.vlsi.kr/objects/cw-522867b04d14d493"},{"id":"cw-5267c7cf9f034f50","name":"AMD-X5-133SFY","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":1996,"architecture":"80486","process":"350 nm","aliases":["Amd am5x86 amd-x5-133sfy"],"fields":[{"key":"Model name","value":"AMD-X5-133SFY","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-X5-133SFY","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-X5-133SFY","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1996,"unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am5x86","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":133,"unit":"MHz","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5x","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1600000,"unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":43,"unit":"mm²","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SQFP-208","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SQFP","unit":"","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8524-r26719","location":"Amd/am5x86/amd-x5-133sfy · revision 26719 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5267c7cf9f034f50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8524-r26719"],"url":"https://museum.vlsi.kr/objects/cw-5267c7cf9f034f50"},{"id":"cw-526e039d81d1a57c","name":"Vector Engine Type 10C","kind":"sku","entityType":"product-model","subtype":"cpu","company":"NEC","series":"Type 10","year":2018,"architecture":"SX-Aurora","process":"16 nm","aliases":["Nec vector engine type 10c"],"fields":[{"key":"Model name","value":"VE Type 10C","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"NEC","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Type 10C","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Oct 26, 2017","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2018,"unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Vector Engine","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Type 10","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"SX-Aurora","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"SX-Aurora TSUBASA","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":493.68,"unit":"mm²","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":24,"unit":"GiB","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"HBM2-1000","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":6,"unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":48,"unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"768 GB/s","unit":"","sourceId":"chipswiki-1593-r5328","location":"Nec/vector engine/type 10c · revision 5328 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-526e039d81d1a57c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010c&oldid=5328","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1593-r5328"],"url":"https://museum.vlsi.kr/objects/cw-526e039d81d1a57c"},{"id":"cw-52b322b937ae0f1e","name":"Xeon Platinum 8170","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8170"],"fields":[{"key":"Model name","value":"Xeon Platinum 8170","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8170,"unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806738170","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303327601","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR37H","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":26,"unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":52,"unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.625,"unit":"MiB","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":832,"unit":"KiB","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"26x32 KiB","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":832,"unit":"KiB","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"26x32 KiB","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":26,"unit":"MiB","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"26x1 MiB","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1470-r4917","location":"Intel/xeon platinum/8170 · revision 4917 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-52b322b937ae0f1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170&oldid=4917","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1470-r4917"],"url":"https://museum.vlsi.kr/objects/cw-52b322b937ae0f1e"},{"id":"cw-52c1bb0e47ca5f97","name":"Ryzen 9 4900H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 9 4900h"],"fields":[{"key":"Model name","value":"Ryzen 9 4900H","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4900H","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 16, 2020","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 16, 2020","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 9","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1750,"unit":"MHz","sourceId":"chipswiki-687-r1681","location":"Amd/ryzen 9/4900h · revision 1681 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-52c1bb0e47ca5f97","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-687-r1681"],"url":"https://museum.vlsi.kr/objects/cw-52c1bb0e47ca5f97"},{"id":"cw-52dd191e78f48c84","name":"Duron 800 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2000,"architecture":"K7","process":"180 nm","aliases":["Amd duron d800aut1b"],"fields":[{"key":"Model name","value":"Duron 800","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 800","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D800AUT1B","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D0800AUT1B","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 17, 2000","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 17, 2000","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35.4,"unit":"W","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8433-r26141","location":"Amd/duron/d800aut1b · revision 26141 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-52dd191e78f48c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8433-r26141"],"url":"https://museum.vlsi.kr/objects/cw-52dd191e78f48c84"},{"id":"cw-52f8db8a92fba834","name":"Am186ES–40VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ES","year":1995,"architecture":"80186","aliases":["Amd am186ex am186es–40vc\\w"],"fields":[{"key":"Model name","value":"Am186ES–40VC\\W","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ES–40VC\\W","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ES–40VC\\W","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14618-r44679","location":"Amd/am186ex/am186es–40vc\\w · revision 44679 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-52f8db8a92fba834","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14618-r44679"],"url":"https://museum.vlsi.kr/objects/cw-52f8db8a92fba834"},{"id":"cw-5321020299c1aff3","name":"Am486SX2-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486SX2","year":1994,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486sx2-66"],"fields":[{"key":"Model name","value":"Am486SX2-66","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486SX2-66","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486SX2-66","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 1994","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486SX2","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":66,"unit":"MHz","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SX2","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":900000,"unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8536-r26732","location":"Amd/am486/am486sx2-66 · revision 26732 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5321020299c1aff3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8536-r26732"],"url":"https://museum.vlsi.kr/objects/cw-5321020299c1aff3"},{"id":"cw-5340ee05d517cea4","name":"K6-2/400AFQ-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-400afq-66"],"fields":[{"key":"Model name","value":"K6-2/400AFQ-66","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/400AFQ-66","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/400AFQ-66","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 1999","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8353-r26048","location":"Amd/k6-2/k6-2-400afq-66 · revision 26048 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5340ee05d517cea4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afq-66&oldid=26048","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8353-r26048"],"url":"https://museum.vlsi.kr/objects/cw-5340ee05d517cea4"},{"id":"cw-534109c10646f3ec","name":"Core M3-8100Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"M3-8000","year":2018,"architecture":"Amber Lake","process":"14 nm","aliases":["Intel core m m3-8100y"],"fields":[{"key":"Model name","value":"M3-8100Y","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"M3-8100Y","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702739859","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRD23","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 28, 2018","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 28, 2018","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core M3","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"M3-8000","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Amber Lake","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Amber Lake Y","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":5,"unit":"W","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 615","unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-4972-r16093","location":"Intel/core m/m3-8100y · revision 16093 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-534109c10646f3ec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-8100y&oldid=16093","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4972-r16093"],"url":"https://museum.vlsi.kr/objects/cw-534109c10646f3ec"},{"id":"cw-5355acda5d4fdb9a","name":"Surge S2","kind":"sku","entityType":"product-model","subtype":"soc","company":"Xiaomi","year":null,"architecture":"Cortex-A53","process":"10 nm","aliases":["Xiaomi surge s2"],"fields":[{"key":"Model name","value":"Xiaomi Surge S2","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Xiaomi","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"S2","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 28, 2017","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Surge","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AXI","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A73","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G71","unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":900,"unit":"MHz","sourceId":"chipswiki-4921-r15873","location":"Xiaomi/surge/s2 · revision 15873 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-05. Not an independent measurement.","entityId":"cw-5355acda5d4fdb9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Xiaomi%2Fsurge%2Fs2&oldid=15873","sourceDate":"2018-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4921-r15873"],"url":"https://museum.vlsi.kr/objects/cw-5355acda5d4fdb9a"},{"id":"cw-535e32f018936adc","name":"P5","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":1993,"process":"600 nm","aliases":["Intel microarchitectures p5"],"fields":[{"key":"Architecture name","value":"P5","unit":"","sourceId":"chipswiki-8769-r27261","location":"Intel/microarchitectures/p5 · revision 27261 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-535e32f018936adc","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp5&oldid=27261","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8769-r27261","location":"Intel/microarchitectures/p5 · revision 27261 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-535e32f018936adc","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp5&oldid=27261","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8769-r27261","location":"Intel/microarchitectures/p5 · revision 27261 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-535e32f018936adc","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp5&oldid=27261","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"April, 1993","unit":"","sourceId":"chipswiki-8769-r27261","location":"Intel/microarchitectures/p5 · revision 27261 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-535e32f018936adc","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp5&oldid=27261","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":600,"unit":"nm","sourceId":"chipswiki-8769-r27261","location":"Intel/microarchitectures/p5 · revision 27261 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-535e32f018936adc","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp5&oldid=27261","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8769-r27261","location":"Intel/microarchitectures/p5 · revision 27261 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-535e32f018936adc","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp5&oldid=27261","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":80486,"unit":"","sourceId":"chipswiki-8769-r27261","location":"Intel/microarchitectures/p5 · revision 27261 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-535e32f018936adc","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp5&oldid=27261","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"P6","unit":"","sourceId":"chipswiki-8769-r27261","location":"Intel/microarchitectures/p5 · revision 27261 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-535e32f018936adc","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp5&oldid=27261","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8769-r27261"],"url":"https://museum.vlsi.kr/objects/cw-535e32f018936adc"},{"id":"cw-536a15eef2570d38","name":"EPYC 7313P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7313p"],"fields":[{"key":"Model name","value":"EPYC 7313P","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7313P","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000339","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000339WOF","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. 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Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. 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Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16 × 512 KiB","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 32 MiB","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-753-r1795","location":"Amd/epyc/7313p · revision 1795 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-18. Not an independent measurement.","entityId":"cw-536a15eef2570d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","sourceDate":"2021-05-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-753-r1795"],"url":"https://museum.vlsi.kr/objects/cw-536a15eef2570d38"},{"id":"cw-5380cf08d9241c38","name":"Duron 700 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2000,"architecture":"K7","process":"180 nm","aliases":["Amd duron d700avs1b"],"fields":[{"key":"Model name","value":"Duron 700","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 700","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D700AVS1B","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 17, 2000","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 17, 2000","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":700,"unit":"MHz","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.4,"unit":"V","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":21.3,"unit":"W","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8436-r26144","location":"Amd/duron/d700avs1b · revision 26144 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5380cf08d9241c38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8436-r26144"],"url":"https://museum.vlsi.kr/objects/cw-5380cf08d9241c38"},{"id":"cw-5387c7d21c244723","name":"AMD-K5-PR166ABR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5k86","year":1997,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr166abr"],"fields":[{"key":"Model name","value":"AMD-K5-PR166ABR","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR166ABR","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR166ABR","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 1997","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 1997","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"5k86","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":116.66,"unit":"MHz","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5k86","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":2,"unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":181,"unit":"mm²","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8396-r26092","location":"Amd/k5/amd-k5-pr166abr · revision 26092 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5387c7d21c244723","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr166abr&oldid=26092","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8396-r26092"],"url":"https://museum.vlsi.kr/objects/cw-5387c7d21c244723"},{"id":"cw-539f8ed269b9a7b5","name":"Core i7-10510U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":null,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-10510u"],"fields":[{"key":"Model name","value":"Core i7-10510U","unit":"","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-10510U","unit":"","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4900,"unit":"MHz","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Comet Lake","unit":"","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-1055-r3004","location":"Intel/core i7/i7-10510u · revision 3004 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-09. Not an independent measurement.","entityId":"cw-539f8ed269b9a7b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-10510u&oldid=3004","sourceDate":"2020-07-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1055-r3004"],"url":"https://museum.vlsi.kr/objects/cw-539f8ed269b9a7b5"},{"id":"cw-53ca3796316b0f9b","name":"Alchemy Au1500-500MBD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2001,"architecture":"Au1","process":"180 nm","aliases":["Alchemy au1500-500mbd"],"fields":[{"key":"Model name","value":"Alchemy Au1500-500MBD","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1500-500MBD","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1500-500MBD","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 11, 2001","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 2001","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AB","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AC","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AD","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.500 GB/s","unit":"","sourceId":"chipswiki-477-r961","location":"Alchemy/au1500-500mbd · revision 961 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-53ca3796316b0f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-477-r961"],"url":"https://museum.vlsi.kr/objects/cw-53ca3796316b0f9b"},{"id":"cw-53f838f07a16cdba","name":"Athlon MP 1800+","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd athlon mp amp1800dms3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 1800+","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 1800+","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMP1800DMS3C","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 15, 2001","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 2001","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1533,"unit":"MHz","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Palomino","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37500000,"unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":128,"unit":"mm²","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":66,"unit":"W","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8456-r26649","location":"Amd/athlon mp/amp1800dms3c · revision 26649 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1800dms3c&oldid=26649","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-53f838f07a16cdba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5416759d2663ff9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20corner&oldid=19327","sourceDate":"2018-05-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":57,"unit":"","sourceId":"chipswiki-6264-r19327","location":"Intel/microarchitectures/knights corner · revision 19327 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-20. 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Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x16 KiB","unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8192-r25851","location":"Cavium/octeon plus/cn5734-1000bg1217-ssp · revision 25851 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-541c2ace85de7d75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8192-r25851","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-541c2ace85de7d75"},{"id":"cw-54352df09b6d25c9","name":"Knights Landing","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":null,"process":"14 nm","aliases":["Intel microarchitectures knights landing"],"fields":[{"key":"Architecture name","value":"Knights Landing","unit":"","sourceId":"chipswiki-5113-r16677","location":"Intel/microarchitectures/knights landing · revision 16677 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-06. 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Not an independent measurement.","entityId":"cw-54352df09b6d25c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20landing&oldid=16677","sourceDate":"2018-08-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5113-r16677","location":"Intel/microarchitectures/knights landing · revision 16677 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-06. Not an independent measurement.","entityId":"cw-54352df09b6d25c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20landing&oldid=16677","sourceDate":"2018-08-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":64,"unit":"","sourceId":"chipswiki-5113-r16677","location":"Intel/microarchitectures/knights landing · revision 16677 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-06. Not an independent measurement.","entityId":"cw-54352df09b6d25c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20landing&oldid=16677","sourceDate":"2018-08-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-5113-r16677","location":"Intel/microarchitectures/knights landing · revision 16677 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-06. 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Not an independent measurement.","entityId":"cw-54352df09b6d25c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20landing&oldid=16677","sourceDate":"2018-08-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5113-r16677","location":"Intel/microarchitectures/knights landing · revision 16677 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"shared between cores within tile","note":"Source-reported parameter; source revision 2018-08-06. Not an independent measurement.","entityId":"cw-54352df09b6d25c9","scope":"shared between cores within tile","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20landing&oldid=16677","sourceDate":"2018-08-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silvermont","unit":"","sourceId":"chipswiki-5113-r16677","location":"Intel/microarchitectures/knights landing · revision 16677 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-06. Not an independent measurement.","entityId":"cw-54352df09b6d25c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20landing&oldid=16677","sourceDate":"2018-08-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Knights Corner","unit":"","sourceId":"chipswiki-5113-r16677","location":"Intel/microarchitectures/knights landing · revision 16677 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-06. Not an independent measurement.","entityId":"cw-54352df09b6d25c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20landing&oldid=16677","sourceDate":"2018-08-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Knights Hill","unit":"","sourceId":"chipswiki-5113-r16677","location":"Intel/microarchitectures/knights landing · revision 16677 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-06. Not an independent measurement.","entityId":"cw-54352df09b6d25c9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20landing&oldid=16677","sourceDate":"2018-08-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5113-r16677"],"url":"https://museum.vlsi.kr/objects/cw-54352df09b6d25c9"},{"id":"cw-543d2ab29c36b817","name":"Duron 1300 (Camaro)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2002,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhm1300alq1b"],"fields":[{"key":"Model name","value":"Duron 1300","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 1300","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHM1300ALQ1B","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2002","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 30, 2002","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8408-r26116","location":"Amd/duron/dhm1300alq1b · revision 26116 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-543d2ab29c36b817","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8408-r26116"],"url":"https://museum.vlsi.kr/objects/cw-543d2ab29c36b817"},{"id":"cw-543fe2e3ad6219a8","name":"Core i3-2308M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i3 i3-2308m"],"fields":[{"key":"Model name","value":"Core i3-2308M","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. 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Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2308M","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. 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Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. 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Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. 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Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. 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Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-1622-r5502","location":"Intel/core i3/i3-2308m · revision 5502 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2308m&oldid=5502","sourceDate":"2019-11-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-11-11. Not an independent measurement.","entityId":"cw-543fe2e3ad6219a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1622-r5502","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-543fe2e3ad6219a8"},{"id":"cw-54644b717e8c4a2f","name":"K6-2/500ADK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-500adk"],"fields":[{"key":"Model name","value":"K6-2/500ADK","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/500ADK","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/500ADK","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":499.99,"unit":"MHz","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.1,"unit":"V","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8337-r26032","location":"Amd/k6-2/k6-2-500adk · revision 26032 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54644b717e8c4a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-500adk&oldid=26032","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8337-r26032"],"url":"https://museum.vlsi.kr/objects/cw-54644b717e8c4a2f"},{"id":"cw-54913dde041c934c","name":"MD8086","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"M8086","year":null,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 md8086"],"fields":[{"key":"Model name","value":"AMD MD8086","unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MD8086","unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MD8086","unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Military","unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"M8086","unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":5,"unit":"MHz","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8502-r26695","location":"Amd/am8086/md8086 · revision 26695 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-54913dde041c934c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8502-r26695"],"url":"https://museum.vlsi.kr/objects/cw-54913dde041c934c"},{"id":"cw-5494dcbede5b9c59","name":"Xeon Gold 6142F","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6142f"],"fields":[{"key":"Model name","value":"Xeon Gold 6142F","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6142F","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303593700","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3KH","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":160,"unit":"W","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1502-r4954","location":"Intel/xeon gold/6142f · revision 4954 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5494dcbede5b9c59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6142f&oldid=4954","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1502-r4954"],"url":"https://museum.vlsi.kr/objects/cw-5494dcbede5b9c59"},{"id":"cw-55033b68c1d643f5","name":"Xeon Platinum 8124M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8124m"],"fields":[{"key":"Model name","value":"Xeon Platinum 8124M","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8124M","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2017,"unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":240,"unit":"W","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-620-r1453","location":"Intel/xeon platinum/8124m · revision 1453 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-07. Not an independent measurement.","entityId":"cw-55033b68c1d643f5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124m&oldid=1453","sourceDate":"2021-09-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-620-r1453"],"url":"https://museum.vlsi.kr/objects/cw-55033b68c1d643f5"},{"id":"cw-5513b66a0f735075","name":"Baikal-T1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Baikal Electronics","series":"Baikal","year":2016,"architecture":"P5600","process":"28 nm","aliases":["Baikal baikal-t1"],"fields":[{"key":"Model name","value":"Baikal-T1","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Baikal Electronics","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Baikal-T1","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 1, 2015","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2016","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Baikal","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AXI","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"P5600","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"P5600","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":5,"unit":"W","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-576","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-576","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8282-r25943","location":"Baikal/baikal-t1 · revision 25943 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5513b66a0f735075","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-t1&oldid=25943","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8282-r25943"],"url":"https://museum.vlsi.kr/objects/cw-5513b66a0f735075"},{"id":"cw-55185a741014ed0d","name":"Am186ES–20KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ES","year":1995,"architecture":"80186","aliases":["Amd am186ex am186es–20kc\\w"],"fields":[{"key":"Model name","value":"Am186ES–20KC\\W","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ES–20KC\\W","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ES–20KC\\W","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14627-r44688","location":"Amd/am186ex/am186es–20kc\\w · revision 44688 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-55185a741014ed0d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14627-r44688"],"url":"https://museum.vlsi.kr/objects/cw-55185a741014ed0d"},{"id":"cw-551cdb079d25335f","name":"Core i7-9850H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-9000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i7 i7-9850h"],"fields":[{"key":"Model name","value":"Core i7-9850H","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-9850H","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-9000","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4600,"unit":"MHz","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake HR","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-1833-r6170","location":"Intel/core i7/i7-9850h · revision 6170 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9850h&oldid=6170","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-551cdb079d25335f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1833-r6170","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-551cdb079d25335f"},{"id":"cw-55248337108a96cd","name":"CN3120-300 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-300bg868-exp"],"fields":[{"key":"Model name","value":"Cavium CN3120-300 EXP","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-300 EXP","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3120-300BG868-EXP","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":300,"unit":"MHz","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8252-r25912","location":"Cavium/octeon/cn3120-300bg868-exp · revision 25912 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-300bg868-exp&oldid=25912","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-55248337108a96cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8252-r25912","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-55248337108a96cd"},{"id":"cw-5536d64cc9355849","name":"Core i5-480M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-400","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i5 i5-480m"],"fields":[{"key":"Model name","value":"Intel Core i5-480M","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-480M","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617005487AC","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617005487AC","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 11, 2011","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 11, 2011","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-400","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2666.66,"unit":"MHz","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2933.33,"unit":"MHz","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC27","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC26","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-480m&oldid=6250","sourceDate":"2019-09-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-1846-r6250","location":"Intel/core i5/i5-480m · revision 6250 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-15. 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Not an independent measurement.","entityId":"cw-5536d64cc9355849","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2019-09-15. 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Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1456-r4903","location":"Intel/xeon platinum/8276m · revision 4903 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5577f7491bce6348","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8276m&oldid=4903","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1456-r4903"],"url":"https://museum.vlsi.kr/objects/cw-5577f7491bce6348"},{"id":"cw-5580ffcddd59b339","name":"K6-2/300AFR-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1998,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-300afr-66"],"fields":[{"key":"Model name","value":"K6-2/300AFR-66","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/300AFR-66","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/300AFR-66","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 4, 1998","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8381-r26076","location":"Amd/k6-2/k6-2-300afr-66 · revision 26076 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5580ffcddd59b339","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr-66&oldid=26076","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8381-r26076"],"url":"https://museum.vlsi.kr/objects/cw-5580ffcddd59b339"},{"id":"cw-55ab7379a59fcede","name":"Exynos 9110","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 9","year":2018,"architecture":"Cortex-A53","process":"10 nm","aliases":["Samsung exynos 9110"],"fields":[{"key":"Model name","value":"Exynos 9110","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":9110,"unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 9, 2018","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 9, 2018","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 9","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"GiB","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T720","unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":1,"unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1,"unit":"","sourceId":"chipswiki-983-r2788","location":"Samsung/exynos/9110 · revision 2788 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-08-14. Not an independent measurement.","entityId":"cw-55ab7379a59fcede","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","sourceDate":"2020-08-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-983-r2788"],"url":"https://museum.vlsi.kr/objects/cw-55ab7379a59fcede"},{"id":"cw-55bd991198c6cd94","name":"Alpha 21164","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"DEC","year":1995,"process":"0.5 µm","aliases":["Dec microarchitectures alpha 21164"],"fields":[{"key":"Architecture name","value":"Alpha 21164","unit":"","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"DEC","unit":"","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"DEC","unit":"","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"January, 1995","unit":"","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.5,"unit":"µm","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Alpha","unit":"","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":96,"unit":"KiB","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":"1-64 MiB","unit":"","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"motherboard","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"motherboard","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Alpha 21064","unit":"","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Alpha 21264","unit":"","sourceId":"chipswiki-901-r2386","location":"Dec/microarchitectures/alpha 21164 · revision 2386 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-27. Not an independent measurement.","entityId":"cw-55bd991198c6cd94","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021164&oldid=2386","sourceDate":"2020-11-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-901-r2386"],"url":"https://museum.vlsi.kr/objects/cw-55bd991198c6cd94"},{"id":"cw-55d2c479ac1ff98d","name":"Ryzen 5 PRO 2500U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000U","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 5 pro 2500u"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 2500U","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 2500U","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 8, 2018","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 8, 2018","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"2000U","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-6282-r19481","location":"Amd/ryzen 5/pro 2500u · revision 19481 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-55d2c479ac1ff98d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6282-r19481","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-55d2c479ac1ff98d"},{"id":"cw-55d7366a537afd59","name":"Alchemy Au1550-400MBC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2004,"architecture":"Au1","aliases":["Alchemy au1550-400mbc"],"fields":[{"key":"Model name","value":"Alchemy Au1550-400MBC","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1550-400MBC","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1550-400MBCAA","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2004","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2004","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AA","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1460 mW","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-166","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.600 GB/s","unit":"","sourceId":"chipswiki-463-r944","location":"Alchemy/au1550-400mbc · revision 944 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-55d7366a537afd59","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-463-r944"],"url":"https://museum.vlsi.kr/objects/cw-55d7366a537afd59"},{"id":"cw-55d9b9d507b25e78","name":"Exynos 4210","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 4","year":2011,"architecture":"Cortex-A9","process":"45 nm","aliases":["Samsung exynos 4210"],"fields":[{"key":"Model name","value":"Exynos 4210","unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4210,"unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 14, 2011","unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 17, 2011","unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 4","unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A9","unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A9","unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6854-r21369","location":"Samsung/exynos/4210 · revision 21369 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-28. Not an independent measurement.","entityId":"cw-55d9b9d507b25e78","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","sourceDate":"2018-03-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6854-r21369"],"url":"https://museum.vlsi.kr/objects/cw-55d9b9d507b25e78"},{"id":"cw-55dde97ab0be61d3","name":"Core i5-8259U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-8259u"],"fields":[{"key":"Model name","value":"Core i5-8259U","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8259U","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8068403419522","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRCKB","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake U","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D0","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics 655","unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-5285-r17291","location":"Intel/core i5/i5-8259u · revision 17291 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8259u&oldid=17291","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1528","unit":"","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-55dde97ab0be61d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":46,"unit":"mm","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-9400H","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. 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Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. 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Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-23. 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Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. 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Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake HR","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-04-23. 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Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. 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Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-3035-r10120","location":"Intel/core i5/i5-9400h · revision 10120 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. Not an independent measurement.","entityId":"cw-563b5abcd2d3ba69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-9400h&oldid=10120","sourceDate":"2019-04-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-23. 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Not an independent measurement.","entityId":"cw-564dab56357b7425","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-564dab56357b7425","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-564dab56357b7425","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-564dab56357b7425","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8168-r25827","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-564dab56357b7425"},{"id":"cw-5664df0102a98d81","name":"CN3850-400 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3850-400bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3850-400 NSP","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3850-400 NSP","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8210-r25869","location":"Cavium/octeon/cn3850-400bg1521-nsp · revision 25869 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-400bg1521-nsp&oldid=25869","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5664df0102a98d81","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8210-r25869","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-5664df0102a98d81"},{"id":"cw-56658d22abe4f223","name":"Duron 1000 (Camaro)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhm1000avs1b"],"fields":[{"key":"Model name","value":"Duron 1000","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 1000","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHM1000AVS1B","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 17, 2001","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 17, 2001","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.4,"unit":"V","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8411-r26119","location":"Amd/duron/dhm1000avs1b · revision 26119 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56658d22abe4f223","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8411-r26119"],"url":"https://museum.vlsi.kr/objects/cw-56658d22abe4f223"},{"id":"cw-56cb10d2cda64cec","name":"Xeon D-1520","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1520"],"fields":[{"key":"Model name","value":"Xeon D-1520","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1520","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067401741800","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR29B","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 9, 2015","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 9, 2015","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3730-r11433","location":"Intel/xeon d/d-1520 · revision 11433 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-56cb10d2cda64cec","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3730-r11433"],"url":"https://museum.vlsi.kr/objects/cw-56cb10d2cda64cec"},{"id":"cw-56e91f02598a3078","name":"CN5745-800 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5745-800bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5745-800 SP","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5745-800 SP","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5745-800BG1217-SP","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":160,"unit":"KiB","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x16 KiB","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-800bg1217-sp&oldid=25832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8173-r25832","location":"Cavium/octeon plus/cn5745-800bg1217-sp · revision 25832 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-56e91f02598a3078","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8173-r25832","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-56e91f02598a3078"},{"id":"cw-57863b9abb662d7d","name":"MSM6300","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2002,"architecture":"ARM9","process":"90 nm","aliases":["Qualcomm msm6xxx msm6300"],"fields":[{"key":"Model name","value":"Qualcomm MSM6300","unit":"","sourceId":"chipswiki-7659-r24921","location":"Qualcomm/msm6xxx/msm6300 · revision 24921 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57863b9abb662d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6300&oldid=24921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7659-r24921","location":"Qualcomm/msm6xxx/msm6300 · revision 24921 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57863b9abb662d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6300&oldid=24921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7659-r24921","location":"Qualcomm/msm6xxx/msm6300 · revision 24921 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57863b9abb662d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6300&oldid=24921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-7659-r24921","location":"Qualcomm/msm6xxx/msm6300 · revision 24921 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57863b9abb662d7d","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6300&oldid=24921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6300","unit":"","sourceId":"chipswiki-7659-r24921","location":"Qualcomm/msm6xxx/msm6300 · revision 24921 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57863b9abb662d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6300&oldid=24921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7659-r24921","location":"Qualcomm/msm6xxx/msm6300 · revision 24921 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57863b9abb662d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6300&oldid=24921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 20, 2001","unit":"","sourceId":"chipswiki-7659-r24921","location":"Qualcomm/msm6xxx/msm6300 · revision 24921 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57863b9abb662d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6300&oldid=24921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 30, 2002","unit":"","sourceId":"chipswiki-7659-r24921","location":"Qualcomm/msm6xxx/msm6300 · revision 24921 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57863b9abb662d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6300&oldid=24921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7659-r24921","location":"Qualcomm/msm6xxx/msm6300 · revision 24921 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57863b9abb662d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6300&oldid=24921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-7659-r24921","location":"Qualcomm/msm6xxx/msm6300 · revision 24921 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57863b9abb662d7d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6300&oldid=24921","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-7659-r24921","location":"Qualcomm/msm6xxx/msm6300 · revision 24921 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-57b9219cab6da2ee","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021464&oldid=11642","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.13,"unit":"µm","sourceId":"chipswiki-3745-r11642","location":"Compaq/microarchitectures/alpha 21464 · revision 11642 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-57b9219cab6da2ee","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021464&oldid=11642","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-3745-r11642","location":"Compaq/microarchitectures/alpha 21464 · revision 11642 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-57b9219cab6da2ee","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021464&oldid=11642","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-3745-r11642","location":"Compaq/microarchitectures/alpha 21464 · revision 11642 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-57b9219cab6da2ee","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021464&oldid=11642","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":8,"unit":"","sourceId":"chipswiki-3745-r11642","location":"Compaq/microarchitectures/alpha 21464 · revision 11642 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-57b9219cab6da2ee","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021464&oldid=11642","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"8-way","unit":"","sourceId":"chipswiki-3745-r11642","location":"Compaq/microarchitectures/alpha 21464 · revision 11642 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-57b9219cab6da2ee","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021464&oldid=11642","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Alpha","unit":"","sourceId":"chipswiki-3745-r11642","location":"Compaq/microarchitectures/alpha 21464 · revision 11642 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-57b9219cab6da2ee","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021464&oldid=11642","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-3745-r11642","location":"Compaq/microarchitectures/alpha 21464 · revision 11642 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-57b9219cab6da2ee","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021464&oldid=11642","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Alpha 21364","unit":"","sourceId":"chipswiki-3745-r11642","location":"Compaq/microarchitectures/alpha 21464 · revision 11642 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-31. Not an independent measurement.","entityId":"cw-57b9219cab6da2ee","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Compaq%2Fmicroarchitectures%2Falpha%2021464&oldid=11642","sourceDate":"2019-03-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3745-r11642"],"url":"https://museum.vlsi.kr/objects/cw-57b9219cab6da2ee"},{"id":"cw-57b94d2853f3d27b","name":"MC14500B","kind":"sku","entityType":"product-model","subtype":"sku","company":"Motorola","year":1976,"aliases":["Motorola mc14500 mc14500b"],"fields":[{"key":"Model name","value":"Motorola MC14500B","unit":"","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Motorola","unit":"","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Motorola","unit":"","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MC14500B","unit":"","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MC14500BCL","unit":"","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MC14500BAL","unit":"","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MC14500BCP","unit":"","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Industrial","unit":"","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1976,"unit":"","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1976,"unit":"","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MC14500","unit":"","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1,"unit":"MHz","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":1,"unit":"bit","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-7674-r24951","location":"Motorola/mc14500/mc14500b · revision 24951 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57b94d2853f3d27b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Motorola%2Fmc14500%2Fmc14500b&oldid=24951","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7674-r24951"],"url":"https://museum.vlsi.kr/objects/cw-57b94d2853f3d27b"},{"id":"cw-57c504bea5c0cba3","name":"Atom C3808","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3808"],"fields":[{"key":"Model name","value":"Atom C3808","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3808","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502639702","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR38C","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":672,"unit":"KiB","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":288,"unit":"KiB","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x24 KiB","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-1867-r6403","location":"Intel/atom/c3808 · revision 6403 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-57c504bea5c0cba3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1867-r6403","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-57c504bea5c0cba3"},{"id":"cw-57c594353bc1cf3e","name":"Mobile Duron 650 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dm650avs1b"],"fields":[{"key":"Model name","value":"Duron 650","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 650","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DM650AVS1B","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 15, 2001","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 15, 2001","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":650,"unit":"MHz","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.4,"unit":"V","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57c594353bc1cf3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8406-r26114","location":"Amd/duron/dm650avs1b · revision 26114 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6650U","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066202499212","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KA","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K1","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Graphics 540","unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7842-r25339","location":"Intel/core i7/i7-6650u · revision 25339 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6650u&oldid=25339","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-57cd71873191c53b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7842-r25339","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-57cd71873191c53b"},{"id":"cw-582999323170e92d","name":"Am2024","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Ambric","series":"Gen 1","year":2007,"architecture":"Ambric","process":"130 nm","aliases":["Ambric am2000 am2024"],"fields":[{"key":"Model name","value":"Am2024","unit":"","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Ambric","unit":"","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am2024","unit":"","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am2024","unit":"","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 10, 2006","unit":"","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2007","unit":"","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am2000","unit":"","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Gen 1","unit":"","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ambric","unit":"","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":192,"unit":"","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-582999323170e92d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8666-r26865","location":"Ambric/am2000/am2024 · revision 26865 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2276M","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFCK","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4700,"unit":"MHz","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake HR","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149.6,"unit":"mm²","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2403-r8029","location":"Intel/xeon e/e-2276m · revision 8029 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-583a448b5df2bd57","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2403-r8029"],"url":"https://museum.vlsi.kr/objects/cw-583a448b5df2bd57"},{"id":"cw-583ddd155ef58b5e","name":"Core i5-8265U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2018,"architecture":"Whiskey Lake","process":"14 nm","aliases":["Intel core i5 i5-8265u"],"fields":[{"key":"Model name","value":"Core i5-8265U","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8265U","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8068404064604","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SREJQ","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 28, 2018","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 28, 2018","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Whiskey Lake","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Whiskey Lake U","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"W0","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","alternatives":[{"value":"64 GiB","sourceId":"chipswiki-758-r1842","reason":"Intel/core i5/i5-8265u · revision 1842 · {{memory controller}} / max mem. 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Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 620","unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-758-r1842","location":"Intel/core i5/i5-8265u · revision 1842 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-583ddd155ef58b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8265u&oldid=1842","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-758-r1842"],"url":"https://museum.vlsi.kr/objects/cw-583ddd155ef58b5e"},{"id":"cw-58447157b7456f44","name":"PEZY-SC2","kind":"sku","entityType":"product-model","subtype":"cpu","company":"PEZY","year":2017,"process":"16 nm","aliases":["Pezy pezy-scx pezy-sc2"],"fields":[{"key":"Model name","value":"PEZY-SC2","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"PEZY","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PEZY-SC2","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Supercomputer","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2015,"unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2017,"unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"PEZY-SCx","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":620,"unit":"mm²","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2048,"unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16384,"unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.8,"unit":"V","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":768,"unit":"KiB","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":384,"unit":"KiB","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"6x64 KiB","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":384,"unit":"KiB","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"6x64 KiB","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 1)","value":"8-way set associative","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":2,"unit":"MiB","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"1x2 MiB","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity — Cache (section 1)","value":"8-way set associative","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":12,"unit":"MiB","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":8,"unit":"MiB","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":4,"unit":"MiB","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":12,"unit":"MiB","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache — Cache (section 2)","value":40,"unit":"MiB","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization — Cache (section 2)","value":"1x40 MiB","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity — Cache (section 2)","value":"shared LLC","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 1)","value":"DDR4-3200","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 1)","value":123,"unit":"GiB","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 1)","value":4,"unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 1)","value":4,"unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 1)","value":95.37,"unit":"GiB/s","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":4,"unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":"1.863 TiB/s","unit":"","sourceId":"chipswiki-4784-r15453","location":"Pezy/pezy-scx/pezy-sc2 · revision 15453 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2018-09-22. Not an independent measurement.","entityId":"cw-58447157b7456f44","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-scx%2Fpezy-sc2&oldid=15453","sourceDate":"2018-09-22","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4784-r15453"],"url":"https://museum.vlsi.kr/objects/cw-58447157b7456f44"},{"id":"cw-587888c7cde9bcbb","name":"Core i3-7102E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7100","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7102e"],"fields":[{"key":"Model name","value":"Core i3-7102E","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7102E","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8067702999106","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR34W","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-7100","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-6420-r20021","location":"Intel/core i3/i3-7102e · revision 20021 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-587888c7cde9bcbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7102e&oldid=20021","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":997,"unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701084801","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701084800","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701147501","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0V5","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR08F","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0F9","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2012","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 2012","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-589dc804fbac4220","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F997&oldid=25230","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7792-r25230","location":"Intel/pentium (2009)/997 · revision 25230 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":7.5,"unit":"W","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. 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Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. 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Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. 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Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. 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Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-999-r2850","location":"Amd/k6-2+/k6-2e+-350auz · revision 2850 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350auz&oldid=2850","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. 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Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":321,"unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":2.54,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. 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Not an independent measurement.","entityId":"cw-58a42546277affe9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.3,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. 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Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2019,"unit":"","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.375,"unit":"MiB","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake X","unit":"","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake AP","unit":"","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Skylake (server)","unit":"","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cooper Lake","unit":"","sourceId":"chipswiki-79-r97035","location":"Intel/microarchitectures/cascade lake · revision 97035 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-09. Not an independent measurement.","entityId":"cw-58e5638d02e56278","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fcascade%20lake&oldid=97035","sourceDate":"2022-10-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-79-r97035"],"url":"https://museum.vlsi.kr/objects/cw-58e5638d02e56278"},{"id":"cw-58ebd2af4f7254b7","name":"EPYC 7501","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7501"],"fields":[{"key":"Model name","value":"EPYC 7501","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7501,"unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS7501BEVIHAF","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. 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Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":3,"unit":"MiB","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x64 KiB","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x512 KiB","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x8 MiB","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-4355-r14056","location":"Amd/epyc/7501 · revision 14056 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","sourceDate":"2018-11-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-27. Not an independent measurement.","entityId":"cw-58ebd2af4f7254b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4355-r14056","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-58ebd2af4f7254b7"},{"id":"cw-5909ba2f6d59dbc1","name":"Xeon E5-2697A v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2697a v4"],"fields":[{"key":"Model name","value":"Xeon E5-2697A v4","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2697A v4","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002645900","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2K1","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7200000000,"unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":456.12,"unit":"mm²","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":145,"unit":"W","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x256 KiB","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":40,"unit":"MiB","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5909ba2f6d59dbc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2697a%20v4&oldid=25093","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x2.5 MiB","unit":"","sourceId":"chipswiki-7719-r25093","location":"Intel/xeon e5/e5-2697a v4 · revision 25093 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/233AMZ","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/233AMZ","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":233.33,"unit":"MHz","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.9,"unit":"V","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-590a276f7fd9a706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-233amz&oldid=26083","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8388-r26083","location":"Amd/k6-2/k6-2-233amz · revision 26083 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-59232a374bc0b2fa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsapphire%20rapids&oldid=96954","sourceDate":"2022-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-26-r96954","location":"Intel/microarchitectures/sapphire rapids · revision 96954 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-13. 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Not an independent measurement.","entityId":"cw-59232a374bc0b2fa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsapphire%20rapids&oldid=96954","sourceDate":"2022-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"Intel 7","unit":"","sourceId":"chipswiki-26-r96954","location":"Intel/microarchitectures/sapphire rapids · revision 96954 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-13. Not an independent measurement.","entityId":"cw-59232a374bc0b2fa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsapphire%20rapids&oldid=96954","sourceDate":"2022-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-26-r96954","location":"Intel/microarchitectures/sapphire rapids · revision 96954 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-13. Not an independent measurement.","entityId":"cw-59232a374bc0b2fa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsapphire%20rapids&oldid=96954","sourceDate":"2022-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Ice Lake (server)","unit":"","sourceId":"chipswiki-26-r96954","location":"Intel/microarchitectures/sapphire rapids · revision 96954 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-13. Not an independent measurement.","entityId":"cw-59232a374bc0b2fa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsapphire%20rapids&oldid=96954","sourceDate":"2022-11-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Emerald Rapids","unit":"","sourceId":"chipswiki-26-r96954","location":"Intel/microarchitectures/sapphire rapids · revision 96954 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-13. Not an independent measurement.","entityId":"cw-59232a374bc0b2fa","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsapphire%20rapids&oldid=96954","sourceDate":"2022-11-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-26-r96954"],"url":"https://museum.vlsi.kr/objects/cw-59232a374bc0b2fa"},{"id":"cw-592a16686688319e","name":"Xeon E5-2603 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2603 v4"],"fields":[{"key":"Model name","value":"Xeon E5-2603 v4","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2603 v4","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002032805","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2P0","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":15,"unit":"MiB","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2.5 MiB","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7748-r25125","location":"Intel/xeon e5/e5-2603 v4 · revision 25125 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-592a16686688319e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2603%20v4&oldid=25125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7748-r25125"],"url":"https://museum.vlsi.kr/objects/cw-592a16686688319e"},{"id":"cw-5943e209e60c000c","name":"Helio P90 (MT6779)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio P","year":2018,"architecture":"Cortex-A75","process":"12 nm","aliases":["Mediatek helio mt6779"],"fields":[{"key":"Model name","value":"Helio P90","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P90","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 13, 2018","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 13, 2018","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio P","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2200,"unit":"MHz","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A75","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A75","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3732","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR GM 9446","unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":970,"unit":"MHz","sourceId":"chipswiki-50-r96997","location":"Mediatek/helio/mt6779 · revision 96997 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-21. Not an independent measurement.","entityId":"cw-5943e209e60c000c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6779&oldid=96997","sourceDate":"2022-10-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-50-r96997"],"url":"https://museum.vlsi.kr/objects/cw-5943e209e60c000c"},{"id":"cw-59ac5b89ed292559","name":"Celeron 4205U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2019,"architecture":"Whiskey Lake","process":"14 nm","aliases":["Intel celeron 4205u"],"fields":[{"key":"Model name","value":"Celeron 4205U","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4205U","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8068404080807","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFG2","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Q1, 2019","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"Q1, 2019","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Whiskey Lake","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Whiskey Lake","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Whiskey Lake U","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"W0","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 610","unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-3013-r10021","location":"Intel/celeron/4205u · revision 10021 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-27. Not an independent measurement.","entityId":"cw-59ac5b89ed292559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","sourceDate":"2019-04-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3013-r10021"],"url":"https://museum.vlsi.kr/objects/cw-59ac5b89ed292559"},{"id":"cw-59cb242d119daf02","name":"CN3830-500 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3830-500bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3830-500 EXP","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3830-500 EXP","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3830-500BG1521-EXP","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8226-r25885","location":"Cavium/octeon/cn3830-500bg1521-exp · revision 25885 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-500bg1521-exp&oldid=25885","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59cb242d119daf02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8226-r25885","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-59cb242d119daf02"},{"id":"cw-59deb5d03df94448","name":"AMD-K5-PR200ABX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5k86","year":1997,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr200abx"],"fields":[{"key":"Model name","value":"AMD-K5-PR200ABX","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR200ABX","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR200ABX","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 1997","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 1997","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"5k86","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":133.33,"unit":"MHz","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5k86","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":181,"unit":"mm²","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8394-r26090","location":"Amd/k5/amd-k5-pr200abx · revision 26090 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-59deb5d03df94448","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr200abx&oldid=26090","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8394-r26090"],"url":"https://museum.vlsi.kr/objects/cw-59deb5d03df94448"},{"id":"cw-59e4ae350841b9fb","name":"Cortex-A9","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2007,"process":"40 nm","aliases":["Arm holdings microarchitectures cortex-a9"],"fields":[{"key":"Architecture name","value":"Cortex-A9","unit":"","sourceId":"chipswiki-2144-r7148","location":"Arm holdings/microarchitectures/cortex-a9 · revision 7148 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-28. Not an independent measurement.","entityId":"cw-59e4ae350841b9fb","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a9&oldid=7148","sourceDate":"2019-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-2144-r7148","location":"Arm holdings/microarchitectures/cortex-a9 · revision 7148 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-28. Not an independent measurement.","entityId":"cw-59e4ae350841b9fb","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a9&oldid=7148","sourceDate":"2019-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2144-r7148","location":"Arm holdings/microarchitectures/cortex-a9 · revision 7148 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-28. Not an independent measurement.","entityId":"cw-59e4ae350841b9fb","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a9&oldid=7148","sourceDate":"2019-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October 3, 2007","unit":"","sourceId":"chipswiki-2144-r7148","location":"Arm holdings/microarchitectures/cortex-a9 · revision 7148 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-28. Not an independent measurement.","entityId":"cw-59e4ae350841b9fb","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a9&oldid=7148","sourceDate":"2019-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-2144-r7148","location":"Arm holdings/microarchitectures/cortex-a9 · revision 7148 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-28. Not an independent measurement.","entityId":"cw-59e4ae350841b9fb","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a9&oldid=7148","sourceDate":"2019-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-2144-r7148","location":"Arm holdings/microarchitectures/cortex-a9 · revision 7148 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-28. Not an independent measurement.","entityId":"cw-59e4ae350841b9fb","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a9&oldid=7148","sourceDate":"2019-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A8","unit":"","sourceId":"chipswiki-2144-r7148","location":"Arm holdings/microarchitectures/cortex-a9 · revision 7148 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-28. Not an independent measurement.","entityId":"cw-59e4ae350841b9fb","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a9&oldid=7148","sourceDate":"2019-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A15","unit":"","sourceId":"chipswiki-2144-r7148","location":"Arm holdings/microarchitectures/cortex-a9 · revision 7148 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-07-28. Not an independent measurement.","entityId":"cw-59e4ae350841b9fb","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a9&oldid=7148","sourceDate":"2019-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A7","unit":"","sourceId":"chipswiki-2144-r7148","location":"Arm holdings/microarchitectures/cortex-a9 · revision 7148 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2019-07-28. Not an independent measurement.","entityId":"cw-59e4ae350841b9fb","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a9&oldid=7148","sourceDate":"2019-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A12","unit":"","sourceId":"chipswiki-2144-r7148","location":"Arm holdings/microarchitectures/cortex-a9 · revision 7148 · {{microarchitecture}} / successor 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 3","note":"Source-reported parameter; source revision 2019-07-28. Not an independent measurement.","entityId":"cw-59e4ae350841b9fb","scope":"successor 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a9&oldid=7148","sourceDate":"2019-07-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-A5","unit":"","sourceId":"chipswiki-2144-r7148","location":"Arm holdings/microarchitectures/cortex-a9 · revision 7148 · {{microarchitecture}} / successor 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 4","note":"Source-reported parameter; source revision 2019-07-28. Not an independent measurement.","entityId":"cw-59e4ae350841b9fb","scope":"successor 4","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a9&oldid=7148","sourceDate":"2019-07-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2144-r7148"],"url":"https://museum.vlsi.kr/objects/cw-59e4ae350841b9fb"},{"id":"cw-59e6c41e7586d2d8","name":"Ryzen 7 5800U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 7 5800u"],"fields":[{"key":"Model name","value":"Ryzen 7 5800U","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5800U","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000285","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2000,"unit":"MHz","sourceId":"chipswiki-720-r1730","location":"Amd/ryzen 7/5800u · revision 1730 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-59e6c41e7586d2d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-720-r1730"],"url":"https://museum.vlsi.kr/objects/cw-59e6c41e7586d2d8"},{"id":"cw-5a0845be2758e5c3","name":"Am186ER–40KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1996,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–40ki\\w"],"fields":[{"key":"Model name","value":"Am186ER–40KI\\W","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–40KI\\W","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–40KI\\W","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 1996","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1996","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14639-r44700","location":"Amd/am186ex/am186er–40ki\\w · revision 44700 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5a0845be2758e5c3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14639-r44700"],"url":"https://museum.vlsi.kr/objects/cw-5a0845be2758e5c3"},{"id":"cw-5a1584e91504a0a8","name":"K6-2/400AHX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-400ahx"],"fields":[{"key":"Model name","value":"K6-2/400AHX","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/400AHX","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/400AHX","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 1999","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.4,"unit":"V","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8350-r26045","location":"Amd/k6-2/k6-2-400ahx · revision 26045 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5a1584e91504a0a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ahx&oldid=26045","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8350-r26045"],"url":"https://museum.vlsi.kr/objects/cw-5a1584e91504a0a8"},{"id":"cw-5a39f7474dc930c8","name":"Xeon W-2140B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-2000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon w w-2140b"],"fields":[{"key":"Model name","value":"Xeon W-2140B","unit":"","sourceId":"chipswiki-546-r1125","location":"Intel/xeon w/w-2140b · revision 1125 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. 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Not an independent measurement.","entityId":"cw-5a39f7474dc930c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2140b&oldid=1125","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-546-r1125","location":"Intel/xeon w/w-2140b · revision 1125 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-5a39f7474dc930c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2140b&oldid=1125","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-546-r1125","location":"Intel/xeon w/w-2140b · revision 1125 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-5a39f7474dc930c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2140b&oldid=1125","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-546-r1125","location":"Intel/xeon w/w-2140b · revision 1125 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-5a39f7474dc930c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2140b&oldid=1125","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-546-r1125","location":"Intel/xeon w/w-2140b · revision 1125 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-5a39f7474dc930c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2140b&oldid=1125","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-546-r1125","location":"Intel/xeon w/w-2140b · revision 1125 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-5a39f7474dc930c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2140b&oldid=1125","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-546-r1125","location":"Intel/xeon w/w-2140b · revision 1125 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-05. Not an independent measurement.","entityId":"cw-5a39f7474dc930c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2140b&oldid=1125","sourceDate":"2022-01-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-546-r1125"],"url":"https://museum.vlsi.kr/objects/cw-5a39f7474dc930c8"},{"id":"cw-5ab131d1ca594435","name":"AMD-K6-III+/400ACZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III+ Mobile","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-iii+ amd-k6-iii+-450acz"],"fields":[{"key":"Model name","value":"AMD-K6-III+/400ACZ","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III+/400ACZ","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III+/400ACZ","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 18, 2000","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 18, 2000","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III+","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III+ Mobile","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":449.99,"unit":"MHz","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":3,"unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21400000,"unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4504-r14639","location":"Amd/k6-iii+/amd-k6-iii+-450acz · revision 14639 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-26. Not an independent measurement.","entityId":"cw-5ab131d1ca594435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-450acz&oldid=14639","sourceDate":"2018-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4504-r14639"],"url":"https://museum.vlsi.kr/objects/cw-5ab131d1ca594435"},{"id":"cw-5ad3297e9276b837","name":"Core i5-540UM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-500","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i5 i5-540um"],"fields":[{"key":"Model name","value":"Intel Core i5-540UM","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-540UM","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617006042AD","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 24, 2010","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 24, 2010","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-500","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1199.99,"unit":"MHz","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1999.99,"unit":"MHz","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBUJ","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-7934-r25478","location":"Intel/core i5/i5-540um · revision 25478 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-540um&oldid=25478","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ad3297e9276b837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7934-r25478","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-5ad3297e9276b837"},{"id":"cw-5afe20b17c82e183","name":"i486SX-16","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486SX","year":1991,"architecture":"80486","process":"1 µm","aliases":["Intel 80486 486sx-16"],"fields":[{"key":"Model name","value":"Intel i486SX-16","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486SX-16","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486SX-16","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KU80486SX-16","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 22, 1991","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486SX","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":16,"unit":"MHz","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"16 MT/s","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX431","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX540","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX545","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX548","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX677","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX671","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / s-spec 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 6","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"s-spec 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486SX","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1185000,"unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8081-r25732","location":"Intel/80486/486sx-16 · revision 25732 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5afe20b17c82e183","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486sx-16&oldid=25732","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8081-r25732"],"url":"https://museum.vlsi.kr/objects/cw-5afe20b17c82e183"},{"id":"cw-5b0cf8578e1b24cd","name":"i486GX-33","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486GX","year":null,"architecture":"80486","process":"800 nm","aliases":["Intel 80486 486gx-33"],"fields":[{"key":"Model name","value":"Intel i486GX-33","unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486GX-33","unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FA80486GX33","unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486GX","unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486GX","unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8085-r25736","location":"Intel/80486/486gx-33 · revision 25736 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b0cf8578e1b24cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486gx-33&oldid=25736","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8085-r25736"],"url":"https://museum.vlsi.kr/objects/cw-5b0cf8578e1b24cd"},{"id":"cw-5b10af40b6bbc3a5","name":"Am186ER–40VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1996,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–40vc\\w"],"fields":[{"key":"Model name","value":"Am186ER–40VC\\W","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–40VC\\W","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–40VC\\W","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 1996","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1996","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14638-r44699","location":"Amd/am186ex/am186er–40vc\\w · revision 44699 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-5b10af40b6bbc3a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14638-r44699"],"url":"https://museum.vlsi.kr/objects/cw-5b10af40b6bbc3a5"},{"id":"cw-5b35c016c4f79005","name":"Core i5-2560M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2560m"],"fields":[{"key":"Model name","value":"Core i5-2560M","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2560M","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700839505","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR047","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October, 2011","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 2011","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7945-r25493","location":"Intel/core i5/i5-2560m · revision 25493 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2560m&oldid=25493","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b35c016c4f79005","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7945-r25493","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-5b35c016c4f79005"},{"id":"cw-5b55d0a4a41e6eae","name":"ARM1","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Acorn","year":1985,"process":"3 µm","aliases":["Acorn microarchitectures arm1"],"fields":[{"key":"Architecture name","value":"ARM1","unit":"","sourceId":"chipswiki-840-r2209","location":"Acorn/microarchitectures/arm1 · revision 2209 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-14. 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Not an independent measurement.","entityId":"cw-5b55d0a4a41e6eae","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm1&oldid=2209","sourceDate":"2021-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-840-r2209","location":"Acorn/microarchitectures/arm1 · revision 2209 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-14. Not an independent measurement.","entityId":"cw-5b55d0a4a41e6eae","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm1&oldid=2209","sourceDate":"2021-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":1985,"unit":"","sourceId":"chipswiki-840-r2209","location":"Acorn/microarchitectures/arm1 · revision 2209 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-14. Not an independent measurement.","entityId":"cw-5b55d0a4a41e6eae","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm1&oldid=2209","sourceDate":"2021-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-840-r2209","location":"Acorn/microarchitectures/arm1 · revision 2209 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-14. Not an independent measurement.","entityId":"cw-5b55d0a4a41e6eae","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm1&oldid=2209","sourceDate":"2021-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-840-r2209","location":"Acorn/microarchitectures/arm1 · revision 2209 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-14. Not an independent measurement.","entityId":"cw-5b55d0a4a41e6eae","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm1&oldid=2209","sourceDate":"2021-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Scalar","unit":"","sourceId":"chipswiki-840-r2209","location":"Acorn/microarchitectures/arm1 · revision 2209 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-14. 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Not an independent measurement.","entityId":"cw-5b55d0a4a41e6eae","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm1&oldid=2209","sourceDate":"2021-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":3,"unit":"","sourceId":"chipswiki-840-r2209","location":"Acorn/microarchitectures/arm1 · revision 2209 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-14. Not an independent measurement.","entityId":"cw-5b55d0a4a41e6eae","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm1&oldid=2209","sourceDate":"2021-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"1-way","unit":"","sourceId":"chipswiki-840-r2209","location":"Acorn/microarchitectures/arm1 · revision 2209 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-14. Not an independent measurement.","entityId":"cw-5b55d0a4a41e6eae","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm1&oldid=2209","sourceDate":"2021-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv1","unit":"","sourceId":"chipswiki-840-r2209","location":"Acorn/microarchitectures/arm1 · revision 2209 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-14. Not an independent measurement.","entityId":"cw-5b55d0a4a41e6eae","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm1&oldid=2209","sourceDate":"2021-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"ARM2","unit":"","sourceId":"chipswiki-840-r2209","location":"Acorn/microarchitectures/arm1 · revision 2209 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-14. 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Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3758","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502639402","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR389","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":448,"unit":"KiB","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x24 KiB","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-204-r418","location":"Intel/atom/c3758 · revision 418 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3758&oldid=418","sourceDate":"2022-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-10. Not an independent measurement.","entityId":"cw-5b7fab4a3805f5f1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-204-r418","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-5b7fab4a3805f5f1"},{"id":"cw-5b8cab730304b695","name":"Xeon E3-1284L v3","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2014,"architecture":"Haswell","process":"22 nm","aliases":["Intel xeon e3 e3-1284l v3"],"fields":[{"key":"Model name","value":"Intel Xeon E3-1284L v3","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1284L v3","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8064701637600","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Mar 1, 2014","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1, 2014","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR1U0","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7762-r25150","location":"Intel/xeon e3/e3-1284l v3 · revision 25150 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5b8cab730304b695","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7762-r25150","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-5b8cab730304b695"},{"id":"cw-5b97456f388b6b36","name":"ETANN","kind":"sku","entityType":"product-model","subtype":"sku","company":"Intel","year":1989,"process":"1 µm","aliases":["Intel etann"],"fields":[{"key":"Model name","value":"ETANN","unit":"","sourceId":"chipswiki-7129-r22498","location":"Intel/etann · revision 22498 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-5b97456f388b6b36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fetann&oldid=22498","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7129-r22498","location":"Intel/etann · revision 22498 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-5b97456f388b6b36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fetann&oldid=22498","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7129-r22498","location":"Intel/etann · revision 22498 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-5b97456f388b6b36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fetann&oldid=22498","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"80170NX","unit":"","sourceId":"chipswiki-7129-r22498","location":"Intel/etann · revision 22498 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-5b97456f388b6b36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fetann&oldid=22498","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"80170NX","unit":"","sourceId":"chipswiki-7129-r22498","location":"Intel/etann · revision 22498 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-5b97456f388b6b36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fetann&oldid=22498","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Artificial Intelligence","unit":"","sourceId":"chipswiki-7129-r22498","location":"Intel/etann · revision 22498 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-5b97456f388b6b36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fetann&oldid=22498","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1989,"unit":"","sourceId":"chipswiki-7129-r22498","location":"Intel/etann · revision 22498 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-5b97456f388b6b36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fetann&oldid=22498","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1989,"unit":"","sourceId":"chipswiki-7129-r22498","location":"Intel/etann · revision 22498 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-5b97456f388b6b36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fetann&oldid=22498","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-7129-r22498","location":"Intel/etann · revision 22498 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-5b97456f388b6b36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fetann&oldid=22498","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"FGMOS","unit":"","sourceId":"chipswiki-7129-r22498","location":"Intel/etann · revision 22498 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-5b97456f388b6b36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fetann&oldid=22498","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":93.15,"unit":"mm²","sourceId":"chipswiki-7129-r22498","location":"Intel/etann · revision 22498 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-5b97456f388b6b36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fetann&oldid=22498","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-7129-r22498","location":"Intel/etann · revision 22498 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-11. Not an independent measurement.","entityId":"cw-5b97456f388b6b36","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fetann&oldid=22498","sourceDate":"2018-02-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7129-r22498"],"url":"https://museum.vlsi.kr/objects/cw-5b97456f388b6b36"},{"id":"cw-5bc4594c8d8da101","name":"Ryzen 5 4500U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 4500u"],"fields":[{"key":"Model name","value":"Ryzen 5 4500U","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4500U","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000084","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":2,"unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1500,"unit":"MHz","sourceId":"chipswiki-542-r1114","location":"Amd/ryzen 5/4500u · revision 1114 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-11. Not an independent measurement.","entityId":"cw-5bc4594c8d8da101","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","sourceDate":"2022-01-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-542-r1114"],"url":"https://museum.vlsi.kr/objects/cw-5bc4594c8d8da101"},{"id":"cw-5bd848446bd5b49d","name":"Duron 1600 (Applebred)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2003,"architecture":"K7","process":"130 nm","aliases":["Amd duron dhd1600dlv1c"],"fields":[{"key":"Model name","value":"Duron 1600","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 1600","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHD1600DLV1C","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2003","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2003","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266.66 MT/s","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Applebred","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37200000,"unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":80.89,"unit":"mm²","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":57,"unit":"W","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8423-r26131","location":"Amd/duron/dhd1600dlv1c · revision 26131 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5bd848446bd5b49d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8423-r26131"],"url":"https://museum.vlsi.kr/objects/cw-5bd848446bd5b49d"},{"id":"cw-5c07ee3188df5a18","name":"Myriad 1 MA1135","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Movidius","series":"1","year":2011,"architecture":"LEON3","process":"65 nm","aliases":["Movidius myriad ma1135"],"fields":[{"key":"Model name","value":"Myriad 1 MA1135","unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Movidius","unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MA1135","unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2011,"unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2011,"unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Myriad","unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":1,"unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":180,"unit":"MHz","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SPARC V8","unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"LEON3","unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"TSMC","unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":9,"unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":9,"unit":"","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-6967-r21745","location":"Movidius/myriad/ma1135 · revision 21745 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-5c07ee3188df5a18","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1135&oldid=21745","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6967-r21745"],"url":"https://museum.vlsi.kr/objects/cw-5c07ee3188df5a18"},{"id":"cw-5c0ff0cee2398559","name":"CN3120-500 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-500bg868-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3120-500 NSP","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-500 NSP","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3120-500BG868-NSP","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8243-r25903","location":"Cavium/octeon/cn3120-500bg868-nsp · revision 25903 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-500bg868-nsp&oldid=25903","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c0ff0cee2398559","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8243-r25903","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-5c0ff0cee2398559"},{"id":"cw-5c5543dfe598a8ab","name":"K6-2E/350AMZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-350amz"],"fields":[{"key":"Model name","value":"K6-2E/350AMZ","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/350AMZ","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/350AMZ","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 1999","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 1999","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":349.99,"unit":"MHz","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.9,"unit":"V","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5c5543dfe598a8ab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350amz&oldid=26013","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8318-r26013","location":"Amd/k6-2/k6-2e-350amz · revision 26013 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5c8ee2153b4c1082","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8173m&oldid=96960","sourceDate":"2022-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-31-r96960","location":"Intel/xeon platinum/8173m · revision 96960 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-07. Not an independent measurement.","entityId":"cw-5c8ee2153b4c1082","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8173m&oldid=96960","sourceDate":"2022-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-31-r96960","location":"Intel/xeon platinum/8173m · revision 96960 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-07. Not an independent measurement.","entityId":"cw-5c8ee2153b4c1082","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8173m&oldid=96960","sourceDate":"2022-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-31-r96960","location":"Intel/xeon platinum/8173m · revision 96960 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-07. Not an independent measurement.","entityId":"cw-5c8ee2153b4c1082","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8173m&oldid=96960","sourceDate":"2022-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-31-r96960","location":"Intel/xeon platinum/8173m · revision 96960 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-07. Not an independent measurement.","entityId":"cw-5c8ee2153b4c1082","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8173m&oldid=96960","sourceDate":"2022-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-31-r96960","location":"Intel/xeon platinum/8173m · revision 96960 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-07. Not an independent measurement.","entityId":"cw-5c8ee2153b4c1082","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8173m&oldid=96960","sourceDate":"2022-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-31-r96960","location":"Intel/xeon platinum/8173m · revision 96960 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-07. Not an independent measurement.","entityId":"cw-5c8ee2153b4c1082","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8173m&oldid=96960","sourceDate":"2022-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-31-r96960","location":"Intel/xeon platinum/8173m · revision 96960 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-07. Not an independent measurement.","entityId":"cw-5c8ee2153b4c1082","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8173m&oldid=96960","sourceDate":"2022-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-31-r96960","location":"Intel/xeon platinum/8173m · revision 96960 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-07. Not an independent measurement.","entityId":"cw-5c8ee2153b4c1082","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8173m&oldid=96960","sourceDate":"2022-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-31-r96960","location":"Intel/xeon platinum/8173m · revision 96960 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-07. Not an independent measurement.","entityId":"cw-5c8ee2153b4c1082","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8173m&oldid=96960","sourceDate":"2022-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-31-r96960","location":"Intel/xeon platinum/8173m · revision 96960 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-07. Not an independent measurement.","entityId":"cw-5c8ee2153b4c1082","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8173m&oldid=96960","sourceDate":"2022-11-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-31-r96960","location":"Intel/xeon platinum/8173m · revision 96960 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-07. Not an independent measurement.","entityId":"cw-5c8ee2153b4c1082","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8173m&oldid=96960","sourceDate":"2022-11-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-31-r96960"],"url":"https://museum.vlsi.kr/objects/cw-5c8ee2153b4c1082"},{"id":"cw-5ca334f735cb0710","name":"Ryzen 3 3250U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2020,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 3 3250u"],"fields":[{"key":"Model name","value":"Ryzen 3 3250U","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3250U","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM3250C4T2OFG","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Dali","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-328-r653","location":"Amd/ryzen 3/3250u · revision 653 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-28. Not an independent measurement.","entityId":"cw-5ca334f735cb0710","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3250u&oldid=653","sourceDate":"2022-06-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-328-r653"],"url":"https://museum.vlsi.kr/objects/cw-5ca334f735cb0710"},{"id":"cw-5cb60867d7dec2db","name":"AM9080A-1PCB","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-1pcb"],"fields":[{"key":"Model name","value":"AMD AM9080A-1PCB","unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-1PCB","unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-1PCB","unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3.125,"unit":"MHz","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"DIP-40","unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"DIP","unit":"","sourceId":"chipswiki-8484-r26677","location":"Amd/am9080/am9080a-1pcb · revision 26677 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cb60867d7dec2db","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1pcb&oldid=26677","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8484-r26677"],"url":"https://museum.vlsi.kr/objects/cw-5cb60867d7dec2db"},{"id":"cw-5cc95296f9e75a2b","name":"Mobile Pentium II 400","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":1999,"architecture":"P6","process":"250 nm","aliases":["Intel mobile pentium ii 400"],"fields":[{"key":"Model name","value":"Mobile Pentium II 400","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":400,"unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KP80524TX400256","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PMG40002002AA","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1999,"unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Mobile Pentium II","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL3BW","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL3EM","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL3JW","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"P6","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Dixon","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mqpA1","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mqbA1","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdxA0","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":27400000,"unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":180,"unit":"mm²","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.55,"unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":13.1,"unit":"W","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"240-pin connector","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7801-r25240","location":"Intel/mobile pentium ii/400 · revision 25240 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5cc95296f9e75a2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7801-r25240"],"url":"https://museum.vlsi.kr/objects/cw-5cc95296f9e75a2b"},{"id":"cw-5ce83e64454fb287","name":"CN5734-800 SSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5734-800bg1217-ssp"],"fields":[{"key":"Model name","value":"Cavium CN5734-800 SSP","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5734-800 SSP","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5734-800BG1217-SSP","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":288,"unit":"KiB","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x16 KiB","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8188-r25847","location":"Cavium/octeon plus/cn5734-800bg1217-ssp · revision 25847 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-800bg1217-ssp&oldid=25847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ce83e64454fb287","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8188-r25847","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-5ce83e64454fb287"},{"id":"cw-5cea2ffdc093ad68","name":"Xeon Platinum 8124","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8124"],"fields":[{"key":"Model name","value":"Xeon Platinum 8124","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8124,"unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2017,"unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. 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Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":240,"unit":"W","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. 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Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-615-r1446","location":"Intel/xeon platinum/8124 · revision 1446 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-5cea2ffdc093ad68","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-615-r1446"],"url":"https://museum.vlsi.kr/objects/cw-5cea2ffdc093ad68"},{"id":"cw-5d2748d2b792d6ed","name":"Core i7-3960X Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Core i7-3900","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7ee i7-3960x"],"fields":[{"key":"Model name","value":"Core i7-3960X Extreme Edition","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-3960X","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8061907184018","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8061907184017","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80619I73960X","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 14, 2011","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 14, 2011","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Core i7-3900","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0GW","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0KF","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"6 Series Chipset","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge E","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C1","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2270000000,"unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":434.72,"unit":"mm²","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA2011","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1536,"unit":"KiB","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. 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Not an independent measurement.","entityId":"cw-5d2748d2b792d6ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3960x&oldid=6169","sourceDate":"2019-09-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":15,"unit":"MiB","sourceId":"chipswiki-1832-r6169","location":"Intel/core i7ee/i7-3960x · revision 6169 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-09-23. 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Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-7700HQ","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR32Q","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-7700","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-760-r1851","location":"Intel/core i7/i7-7700hq · revision 1851 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-5d27d81c2a4a8ed3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7700hq&oldid=1851","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DF","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"V2","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3731-r11435","location":"Intel/xeon d/d-1521 · revision 11435 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-5d3f50df04232dc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3731-r11435"],"url":"https://museum.vlsi.kr/objects/cw-5d3f50df04232dc2"},{"id":"cw-5de96164718c65bd","name":"Alchemy Au1200-333MGF","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2005,"architecture":"Au1","aliases":["Alchemy au1200-333mgf"],"fields":[{"key":"Model name","value":"Alchemy Au1200-333MGF","unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1200-333MGF","unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1200-333MGF","unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2005","unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1500 mW","unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-5de96164718c65bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgf&oldid=937","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-456-r937","location":"Alchemy/au1200-333mgf · revision 937 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 1999","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.66,"unit":"MHz","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95.33 MT/s","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8323-r26018","location":"Amd/k6-2/k6-2e-333afr · revision 26018 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e48ec8820291528","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333afr&oldid=26018","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8323-r26018"],"url":"https://museum.vlsi.kr/objects/cw-5e48ec8820291528"},{"id":"cw-5e497f546ada1d38","name":"Xeon E5-2673 v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2673 v4"],"fields":[{"key":"Model name","value":"Xeon E5-2673 v4","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2673 v4","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","alternatives":[{"value":"3600 MHz","sourceId":"chipswiki-1666-r5832","reason":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / turbo frequency1. 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Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":9.6,"unit":"GT/s","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KE","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7200000000,"unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":456.12,"unit":"mm²","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":135,"unit":"W","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5,"unit":"MiB","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x256 KiB","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":50,"unit":"MiB","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x2.5 MiB","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-1666-r5832","location":"Intel/xeon e5/e5-2673 v4 · revision 5832 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-15. Not an independent measurement.","entityId":"cw-5e497f546ada1d38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2673%20v4&oldid=5832","sourceDate":"2019-10-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1666-r5832"],"url":"https://museum.vlsi.kr/objects/cw-5e497f546ada1d38"},{"id":"cw-5e61e8b6ce0bf2bf","name":"NNP-T 1400","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"NNP-T","year":2019,"architecture":"Spring Crest","process":"16 nm","aliases":["Nervana nnp nnp-t 1400"],"fields":[{"key":"Model name","value":"NNP-T 1400","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"NNP-T 1400","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 12, 2019","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 12, 2019","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"NNP","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"NNP-T","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Spring Crest","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":27000000000,"unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":680,"unit":"mm²","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":375,"unit":"W","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"HBM2-2400","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":32,"unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.2288 TB/s","unit":"","sourceId":"chipswiki-1363-r4499","location":"Nervana/nnp/nnp-t 1400 · revision 4499 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-5e61e8b6ce0bf2bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-t%201400&oldid=4499","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1363-r4499"],"url":"https://museum.vlsi.kr/objects/cw-5e61e8b6ce0bf2bf"},{"id":"cw-5e72022fa566fa55","name":"Duron 1200 (Camaro)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2002,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhm1200aqq1b"],"fields":[{"key":"Model name","value":"Duron 1200","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 1200","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHM1200AQQ1B","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2002","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 30, 2002","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.45,"unit":"V","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8409-r26117","location":"Amd/duron/dhm1200aqq1b · revision 26117 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e72022fa566fa55","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8409-r26117"],"url":"https://museum.vlsi.kr/objects/cw-5e72022fa566fa55"},{"id":"cw-5e72ac8456517417","name":"Xeon Platinum 8168","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8168"],"fields":[{"key":"Model name","value":"Xeon Platinum 8168","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8168,"unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303327701","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR37J","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":33,"unit":"MiB","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x1.375 MiB","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e72ac8456517417","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8168&oldid=4918","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1471-r4918","location":"Intel/xeon platinum/8168 · revision 4918 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5215L","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504214202","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFBD","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5200,"unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L0","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L1","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4.5 TiB","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":10,"unit":"MiB","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x1 MiB","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":13.75,"unit":"MiB","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x1.375 MiB","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1529-r4983","location":"Intel/xeon gold/5215l · revision 4983 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e74934256018d8d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215l&oldid=4983","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1529-r4983"],"url":"https://museum.vlsi.kr/objects/cw-5e74934256018d8d"},{"id":"cw-5e78f4d71decd9fd","name":"Xeon Platinum 8260","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 8260"],"fields":[{"key":"Model name","value":"Xeon Platinum 8260","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8260,"unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504201101","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF9H","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8200,"unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-5e78f4d71decd9fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8260&oldid=4907","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1460-r4907","location":"Intel/xeon platinum/8260 · revision 4907 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-5960X","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80648I75960X","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80648I75960X","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 29, 2014","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 29, 2014","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-5900","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR20Q","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"X99","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Haswell E","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R2","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":355.52,"unit":"mm²","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA2011-3","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":20,"unit":"MiB","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2.5 MiB","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7822-r25280","location":"Intel/core i7ee/i7-5960x · revision 25280 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5e8a9145f524e69a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-5960x&oldid=25280","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7822-r25280"],"url":"https://museum.vlsi.kr/objects/cw-5e8a9145f524e69a"},{"id":"cw-5e9959e273d3e6af","name":"POWER7+","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2012,"process":"32 nm","aliases":["Ibm microarchitectures power7+"],"fields":[{"key":"Architecture name","value":"POWER7+","unit":"","sourceId":"chipswiki-9918-r31537","location":"Ibm/microarchitectures/power7+ · revision 31537 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-5e9959e273d3e6af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7%2B&oldid=31537","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-9918-r31537","location":"Ibm/microarchitectures/power7+ · revision 31537 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-5e9959e273d3e6af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7%2B&oldid=31537","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-9918-r31537","location":"Ibm/microarchitectures/power7+ · revision 31537 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-5e9959e273d3e6af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7%2B&oldid=31537","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2012,"unit":"","sourceId":"chipswiki-9918-r31537","location":"Ibm/microarchitectures/power7+ · revision 31537 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-5e9959e273d3e6af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7%2B&oldid=31537","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-9918-r31537","location":"Ibm/microarchitectures/power7+ · revision 31537 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-5e9959e273d3e6af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7%2B&oldid=31537","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-9918-r31537","location":"Ibm/microarchitectures/power7+ · revision 31537 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-5e9959e273d3e6af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7%2B&oldid=31537","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"POWER7","unit":"","sourceId":"chipswiki-9918-r31537","location":"Ibm/microarchitectures/power7+ · revision 31537 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-5e9959e273d3e6af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7%2B&oldid=31537","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"POWER8","unit":"","sourceId":"chipswiki-9918-r31537","location":"Ibm/microarchitectures/power7+ · revision 31537 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-09-03. Not an independent measurement.","entityId":"cw-5e9959e273d3e6af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower7%2B&oldid=31537","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-9918-r31537"],"url":"https://museum.vlsi.kr/objects/cw-5e9959e273d3e6af"},{"id":"cw-5eaabdebbdfeb6ea","name":"EPYC 7451","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7000","year":2017,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc 7451"],"fields":[{"key":"Model name","value":"EPYC 7451","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7451,"unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PS7451BDVHCAF","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2017","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7000,"unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Naples","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":19200000000,"unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":180,"unit":"W","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2.25,"unit":"MiB","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x64 KiB","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x512 KiB","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x8 MiB","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-5075-r16548","location":"Amd/epyc/7451 · revision 16548 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","sourceDate":"2018-08-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-4094","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket SP3","unit":"","sourceId":"chipswiki-31468-r92417","location":"Template:Packages/amd/socket sp3 · revision 92417 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-11. Not an independent measurement.","entityId":"cw-5eaabdebbdfeb6ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","sourceDate":"2017-06-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5075-r16548","chipswiki-31468-r92417"],"url":"https://museum.vlsi.kr/objects/cw-5eaabdebbdfeb6ea"},{"id":"cw-5ec9ab0a2bbd19ef","name":"QorIQ P1014","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":2011,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1014"],"fields":[{"key":"Model name","value":"QorIQ P1014","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1014","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2010,"unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2011,"unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":125,"unit":"°C","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":1.49,"unit":"GiB/s","sourceId":"chipswiki-8103-r25762","location":"Freescale/qoriq/p1014 · revision 25762 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1014&oldid=25762","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"TE-PBGA-II-689","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"TE-PBGA-II","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":689,"unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"TE-PBGA-425","unit":"","sourceId":"chipswiki-31375-r92169","location":"Template:Packages/freescale/te-pbga-425 · revision 92169 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-425&oldid=92169","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"TE-PBGA","unit":"","sourceId":"chipswiki-31375-r92169","location":"Template:Packages/freescale/te-pbga-425 · revision 92169 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-425&oldid=92169","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":425,"unit":"","sourceId":"chipswiki-31375-r92169","location":"Template:Packages/freescale/te-pbga-425 · revision 92169 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-425&oldid=92169","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":0.8,"unit":"mm","sourceId":"chipswiki-31375-r92169","location":"Template:Packages/freescale/te-pbga-425 · revision 92169 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-425&oldid=92169","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":19,"unit":"mm","sourceId":"chipswiki-31375-r92169","location":"Template:Packages/freescale/te-pbga-425 · revision 92169 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-425&oldid=92169","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":19,"unit":"mm","sourceId":"chipswiki-31375-r92169","location":"Template:Packages/freescale/te-pbga-425 · revision 92169 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ec9ab0a2bbd19ef","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-425&oldid=92169","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8103-r25762","chipswiki-31374-r92168","chipswiki-31375-r92169"],"url":"https://museum.vlsi.kr/objects/cw-5ec9ab0a2bbd19ef"},{"id":"cw-5f260d908ce80a09","name":"Am486DX4-100V16B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX4V","year":1997,"architecture":"80486","process":"350 nm","aliases":["Amd am486 am486dx4-100v16b"],"fields":[{"key":"Model name","value":"Am486DX4-100V16B","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-100V16B","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am486DX4-100V16BHC","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am486DX4-100V16BGC","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am486DX4-100V16BHI","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am486DX4-100V16BGI","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 1997","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4V","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":100,"unit":"MHz","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4V","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8555-r26751","location":"Amd/am486/am486dx4-100v16b · revision 26751 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f260d908ce80a09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8555-r26751"],"url":"https://museum.vlsi.kr/objects/cw-5f260d908ce80a09"},{"id":"cw-5f40751c2366c55c","name":"Core i3-8020","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-8000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-8020"],"fields":[{"key":"Model name","value":"Core i3-8020","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8020","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":23,"unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6426-r20064","location":"Intel/core i3/i3-8020 · revision 20064 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-5f40751c2366c55c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8020&oldid=20064","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6426-r20064"],"url":"https://museum.vlsi.kr/objects/cw-5f40751c2366c55c"},{"id":"cw-5f714584e0c13b70","name":"Xeon E-2226G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2200","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2226g"],"fields":[{"key":"Model name","value":"Xeon E-2226G","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2226G","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068404174503","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF7F","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4700,"unit":"MHz","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149.6,"unit":"mm²","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":80,"unit":"W","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-5f714584e0c13b70","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2411-r8052","location":"Intel/xeon e/e-2226g · revision 8052 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701047703","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-8006-r25587","location":"Intel/core i3/i3-2357m · revision 25587 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2357m&oldid=25587","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5f855406fe795d72","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8006-r25587","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-5f855406fe795d72"},{"id":"cw-5f89d5302f57ed83","name":"Alchemy Au1100-333MBD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2002,"architecture":"Au1","process":"130 nm","aliases":["Alchemy au1100-333mbd"],"fields":[{"key":"Model name","value":"Alchemy Au1100-333MBD","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1100-333MBD","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBDBC","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1100-333MBDBD","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2002","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.333 GB/s","unit":"","sourceId":"chipswiki-474-r955","location":"Alchemy/au1100-333mbd · revision 955 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-5f89d5302f57ed83","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-474-r955"],"url":"https://museum.vlsi.kr/objects/cw-5f89d5302f57ed83"},{"id":"cw-5f967c07d9c2bfad","name":"Exynos 7904","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 7","year":2019,"architecture":"Cortex-A73","process":"14 nm","aliases":["Samsung exynos 7904"],"fields":[{"key":"Model name","value":"Exynos 7904","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7904,"unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 21, 2019","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 21, 2019","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 7","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":1600,"unit":"MHz","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A73","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A73","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-808-r2056","location":"Samsung/exynos/7904 · revision 2056 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-02. Not an independent measurement.","entityId":"cw-5f967c07d9c2bfad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7904&oldid=2056","sourceDate":"2021-03-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-808-r2056"],"url":"https://museum.vlsi.kr/objects/cw-5f967c07d9c2bfad"},{"id":"cw-5fd3dc8f5faa821a","name":"AMD-K6-200ALYD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Desktop K6","year":1997,"architecture":"K6","process":"350 nm","aliases":["Amd k6 amd-k6-200alyd"],"fields":[{"key":"Model name","value":"AMD-K6-200ALYD","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-200ALYD","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-200ALYD","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1997","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1997","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Desktop K6","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":199.99,"unit":"MHz","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"6k86","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":162,"unit":"mm²","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.9,"unit":"V","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8296-r25984","location":"Amd/k6/amd-k6-200alyd · revision 25984 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5fd3dc8f5faa821a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alyd&oldid=25984","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8296-r25984"],"url":"https://museum.vlsi.kr/objects/cw-5fd3dc8f5faa821a"},{"id":"cw-5ff06d052d44b3ec","name":"Gen5","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2008,"process":"45 nm","aliases":["Intel microarchitectures gen5"],"fields":[{"key":"Architecture name","value":"Gen5","unit":"","sourceId":"chipswiki-15956-r52673","location":"Intel/microarchitectures/gen5 · revision 52673 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-5ff06d052d44b3ec","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5&oldid=52673","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-15956-r52673","location":"Intel/microarchitectures/gen5 · revision 52673 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-5ff06d052d44b3ec","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5&oldid=52673","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-15956-r52673","location":"Intel/microarchitectures/gen5 · revision 52673 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-5ff06d052d44b3ec","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5&oldid=52673","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"June 3, 2008","unit":"","sourceId":"chipswiki-15956-r52673","location":"Intel/microarchitectures/gen5 · revision 52673 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-5ff06d052d44b3ec","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5&oldid=52673","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-15956-r52673","location":"Intel/microarchitectures/gen5 · revision 52673 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-5ff06d052d44b3ec","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5&oldid=52673","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen4","unit":"","sourceId":"chipswiki-15956-r52673","location":"Intel/microarchitectures/gen5 · revision 52673 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-5ff06d052d44b3ec","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5&oldid=52673","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Gen5.75","unit":"","sourceId":"chipswiki-15956-r52673","location":"Intel/microarchitectures/gen5 · revision 52673 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-01-29. Not an independent measurement.","entityId":"cw-5ff06d052d44b3ec","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen5&oldid=52673","sourceDate":"2017-01-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15956-r52673"],"url":"https://museum.vlsi.kr/objects/cw-5ff06d052d44b3ec"},{"id":"cw-5ff6bedf26867cf4","name":"Xeon E5-4628L v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-4000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-4628l v4"],"fields":[{"key":"Model name","value":"Xeon E5-4628L v4","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-4628L v4","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002061000","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-4000","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2SB","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 4S","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":75,"unit":"W","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3.5,"unit":"MiB","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x256 KiB","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35,"unit":"MiB","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x2.5 MiB","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7713-r25085","location":"Intel/xeon e5/e5-4628l v4 · revision 25085 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-5ff6bedf26867cf4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-4628l%20v4&oldid=25085","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7713-r25085"],"url":"https://museum.vlsi.kr/objects/cw-5ff6bedf26867cf4"},{"id":"cw-600dfcf6d007633c","name":"Atom C3850","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3850"],"fields":[{"key":"Model name","value":"Atom C3850","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3850","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076502639201","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR387","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":672,"unit":"KiB","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":288,"unit":"KiB","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x24 KiB","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-1871-r6407","location":"Intel/atom/c3850 · revision 6407 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3850&oldid=6407","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. 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Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-600dfcf6d007633c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. 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Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6234,"unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1488-r4939","location":"Intel/xeon gold/6234 · revision 4939 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-603ae6678d88567f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1488-r4939"],"url":"https://museum.vlsi.kr/objects/cw-603ae6678d88567f"},{"id":"cw-60772189a2df8d1a","name":"CN5840-1000 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5840-1000bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5840-1000 EXP","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5840-1000 EXP","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5840-1000BG1521-EXP","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8149-r25808","location":"Cavium/octeon plus/cn5840-1000bg1521-exp · revision 25808 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-1000bg1521-exp&oldid=25808","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-60772189a2df8d1a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8149-r25808","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-60772189a2df8d1a"},{"id":"cw-6081b5226bb12cb8","name":"Am186CC-50KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CC","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186cc-50kc\\w"],"fields":[{"key":"Model name","value":"Am186CC-50KC\\W","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CC-50KC\\W","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CC-50KC\\W","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CC","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"12.5 MT/s","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14687-r44748","location":"Amd/am186cx/am186cc-50kc\\w · revision 44748 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6081b5226bb12cb8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14687-r44748"],"url":"https://museum.vlsi.kr/objects/cw-6081b5226bb12cb8"},{"id":"cw-609374473851dd21","name":"Pentium 4405Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel pentium (2009) 4405y"],"fields":[{"key":"Model name","value":"Pentium 4405Y","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4405Y","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8066201931229","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2ER","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 3, 2015","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake Y","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":5,"unit":"°C","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 515","unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-4984-r16106","location":"Intel/pentium (2009)/4405y · revision 16106 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-609374473851dd21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F4405y&oldid=16106","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4984-r16106"],"url":"https://museum.vlsi.kr/objects/cw-609374473851dd21"},{"id":"cw-60accd09a7303b8f","name":"Alchemy Au1200-400MGC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2005,"architecture":"Au1","aliases":["Alchemy au1200-400mgc"],"fields":[{"key":"Model name","value":"Alchemy Au1200-400MGC","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1200-400MGC","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1200-400MGC","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2005","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2005","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-60accd09a7303b8f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-400mgc&oldid=935","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.600 GB/s","unit":"","sourceId":"chipswiki-454-r935","location":"Alchemy/au1200-400mgc · revision 935 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. 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Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8180,"unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303314400","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR377","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1466-r4913","location":"Intel/xeon platinum/8180 · revision 4913 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-60b8ebd919c15f06","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8180&oldid=4913","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1466-r4913"],"url":"https://museum.vlsi.kr/objects/cw-60b8ebd919c15f06"},{"id":"cw-61350c443829e79a","name":"KaiXian KX-5640","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Zhaoxin","series":"KX-5000","year":2017,"architecture":"WuDaoKou","process":"28 nm","aliases":["Zhaoxin kaixian kx-5640"],"fields":[{"key":"Model name","value":"KaiXian KX-5640","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Zhaoxin","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"HLMC","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"KX-5640","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KX-5640","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"KaiXian","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"KX-5000","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"WuDaoKou","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2100000000,"unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":187,"unit":"mm²","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"32-way set associative","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5651-r18549","location":"Zhaoxin/kaixian/kx-5640 · revision 18549 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-61350c443829e79a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5651-r18549"],"url":"https://museum.vlsi.kr/objects/cw-61350c443829e79a"},{"id":"cw-614c6a025109a6f6","name":"CN3110-550 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-550bg868-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3110-550 NSP","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-550 NSP","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-550BG868-NSP","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":550,"unit":"MHz","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8255-r25915","location":"Cavium/octeon/cn3110-550bg868-nsp · revision 25915 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-550bg868-nsp&oldid=25915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-614c6a025109a6f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8255-r25915","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-614c6a025109a6f6"},{"id":"cw-619171f49bb8d8c7","name":"Am486DXL2-80","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2","year":1993,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486dxl2-80"],"fields":[{"key":"Model name","value":"Am486DXL2-80","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DXL2-80","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A8048DXL2-80","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 1993","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":80,"unit":"MHz","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"40 MT/s","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DXL2","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-619171f49bb8d8c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8543-r26739","location":"Amd/am486/am486dxl2-80 · revision 26739 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2610UE","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700849607","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR079","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":850,"unit":"MHz","sourceId":"chipswiki-7900-r25404","location":"Intel/core i7/i7-2610ue · revision 25404 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2610ue&oldid=25404","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61af009fd2b33515","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7900-r25404","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-61af009fd2b33515"},{"id":"cw-61bcdf8b665aafeb","name":"Helio P25 (MT6757CD)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio P","year":2017,"architecture":"Cortex-A53","process":"16 nm","aliases":["Mediatek helio mt6757cd"],"fields":[{"key":"Model name","value":"Helio P25","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P25","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6757CD","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 22, 2016","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 8, 2017","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio P","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":6,"unit":"GiB","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3200","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T880","unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-795-r1994","location":"Mediatek/helio/mt6757cd · revision 1994 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-30. Not an independent measurement.","entityId":"cw-61bcdf8b665aafeb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757cd&oldid=1994","sourceDate":"2021-03-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-795-r1994"],"url":"https://museum.vlsi.kr/objects/cw-61bcdf8b665aafeb"},{"id":"cw-61c0aac1431ddbbb","name":"Core i7-2840QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2840qm"],"fields":[{"key":"Model name","value":"Core i7-2840QM","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2840QM","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700835001","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR00V","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1600","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2840qm&oldid=25377","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7873-r25377","location":"Intel/core i7/i7-2840qm · revision 25377 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":1224,"unit":"","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":58.5,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":51,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":1.347,"unit":"mm","sourceId":"chipswiki-31408-r92251","location":"Template:Packages/intel/fcbga-1224 · revision 92251 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1224&oldid=92251","sourceDate":"2017-09-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c0aac1431ddbbb","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":9.5,"unit":"W","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":"-40 °C","unit":"","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":110,"unit":"°C","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-1296","unit":"","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1296","unit":"","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8045-r25680","location":"Intel/atom x5/x5-e3940 · revision 25680 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-61c3ed057ef0e8d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8045-r25680"],"url":"https://museum.vlsi.kr/objects/cw-61c3ed057ef0e8d8"},{"id":"cw-61f3c9e127f27c0f","name":"A12Z Bionic","kind":"sku","entityType":"product-model","subtype":"soc","company":"Apple","year":2020,"process":"7 nm","aliases":["Apple ax a12z"],"fields":[{"key":"Model name","value":"A12Z Bionic","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Apple","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A12Z Bionic","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"TBD","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 18, 2020","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 25, 2020","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ax","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.3","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Vortex","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Tempest","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":"10,000,000,000+","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":"122 mm²+","unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-888-r2320","location":"Apple/ax/a12z · revision 2320 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-21. Not an independent measurement.","entityId":"cw-61f3c9e127f27c0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","sourceDate":"2020-12-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-888-r2320"],"url":"https://museum.vlsi.kr/objects/cw-61f3c9e127f27c0f"},{"id":"cw-620dcaf130379711","name":"CN3840-600 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3840-600bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3840-600 EXP","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3840-600 EXP","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3840-600BG1521-EXP","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x8 KiB","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8214-r25873","location":"Cavium/octeon/cn3840-600bg1521-exp · revision 25873 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-exp&oldid=25873","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-620dcaf130379711","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8214-r25873","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-620dcaf130379711"},{"id":"cw-6227faadceea9f48","name":"Core i7-7560U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-7500","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-7560u"],"fields":[{"key":"Model name","value":"Core i7-7560U","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-7560U","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR366","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-7500","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7830-r25318","location":"Intel/core i7/i7-7560u · revision 25318 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6227faadceea9f48","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-4960-r16053","location":"Intel/core i7/i7-8670t · revision 16053 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-622f5c049f9902c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8670t&oldid=16053","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4960-r16053"],"url":"https://museum.vlsi.kr/objects/cw-622f5c049f9902c7"},{"id":"cw-62cc61dc80f5f0a5","name":"Kirin 990 4G","kind":"sku","entityType":"product-model","subtype":"soc","company":"HiSilicon","series":"900","year":2019,"architecture":"Cortex-A76","process":"7 nm","aliases":[],"fields":[{"key":"Model name","value":"Kirin 990 4G","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"990 4G","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 6, 2019","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 6, 2019","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Kirin","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2860,"unit":"MHz","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2088,"unit":"MHz","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":1860,"unit":"MHz","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A76","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A76","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":90,"unit":"mm²","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":512,"unit":"KiB","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":2,"unit":"MiB","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"4x512 KiB","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":512,"unit":"KiB","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"4x128 KiB","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-4266","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G76","unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":16,"unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":600,"unit":"MHz","sourceId":"chipswiki-585-r1343","location":"Kirin 990 4G · revision 1343 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-62cc61dc80f5f0a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Kirin%20990%204G&oldid=1343","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-585-r1343"],"url":"https://museum.vlsi.kr/objects/cw-62cc61dc80f5f0a5"},{"id":"cw-62d04072b10b9cf6","name":"QorIQ P2020","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P2","year":2009,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p2020"],"fields":[{"key":"Model name","value":"P2020","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P2020","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 16, 2008","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2009,"unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P2","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":800,"unit":"MHz","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1200,"unit":"MHz","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":1333,"unit":"MHz","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":125,"unit":"°C","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":5.96,"unit":"GiB/s","sourceId":"chipswiki-1216-r3803","location":"Freescale/qoriq/p2020 · revision 3803 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp2020&oldid=3803","sourceDate":"2020-04-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-II-689","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TE-PBGA-II","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":689,"unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-05. Not an independent measurement.","entityId":"cw-62d04072b10b9cf6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1216-r3803","chipswiki-31374-r92168"],"url":"https://museum.vlsi.kr/objects/cw-62d04072b10b9cf6"},{"id":"cw-62d65e4de2398208","name":"AMD-K6/233ADZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Mobile K6","year":1998,"architecture":"K6","process":"250 nm","aliases":["Amd k6 amd-k6 233adz"],"fields":[{"key":"Model name","value":"AMD-K6/233ADZ","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6/233ADZ","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6/233ADZ","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 1998","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 5, 1998","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Mobile K6","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":233.33,"unit":"MHz","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Little Foot","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":68,"unit":"mm²","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.1,"unit":"V","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8289-r25977","location":"Amd/k6/amd-k6/233adz · revision 25977 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-62d65e4de2398208","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F233adz&oldid=25977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8289-r25977"],"url":"https://museum.vlsi.kr/objects/cw-62d65e4de2398208"},{"id":"cw-62d991b85bc11c4d","name":"Am186EM–20KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186EM","year":1995,"architecture":"80186","aliases":["Amd am186ex am186em–20kc\\w"],"fields":[{"key":"Model name","value":"Am186EM–20KC\\W","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EM–20KC\\W","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EM–20KC\\W","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14658-r44719","location":"Amd/am186ex/am186em–20kc\\w · revision 44719 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-62d991b85bc11c4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14658-r44719"],"url":"https://museum.vlsi.kr/objects/cw-62d991b85bc11c4d"},{"id":"cw-62da2b5976eb7952","name":"Xeon W-3223","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-3200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon w w-3223"],"fields":[{"key":"Model name","value":"Xeon W-3223","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-3223","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504248402","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFFG","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-3200","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":160,"unit":"W","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1645-r5689","location":"Intel/xeon w/w-3223 · revision 5689 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-30. Not an independent measurement.","entityId":"cw-62da2b5976eb7952","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3223&oldid=5689","sourceDate":"2019-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1645-r5689"],"url":"https://museum.vlsi.kr/objects/cw-62da2b5976eb7952"},{"id":"cw-6309a22d4bb2cb9d","name":"K6-2/366AFK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-366afk"],"fields":[{"key":"Model name","value":"K6-2/366AFK","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/366AFK","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/366AFK","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":366.66,"unit":"MHz","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8363-r26058","location":"Amd/k6-2/k6-2-366afk · revision 26058 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6309a22d4bb2cb9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afk&oldid=26058","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8363-r26058"],"url":"https://museum.vlsi.kr/objects/cw-6309a22d4bb2cb9d"},{"id":"cw-63224665fdef0345","name":"CN5860-600 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5860-600bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN5860-600 NSP","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5860-600 NSP","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5860-600BG1521-NSP","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x16 KiB","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8121-r25780","location":"Cavium/octeon plus/cn5860-600bg1521-nsp · revision 25780 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-600bg1521-nsp&oldid=25780","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-63224665fdef0345","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8121-r25780","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-63224665fdef0345"},{"id":"cw-634376043bd9aa0e","name":"Core i7-2920XM Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7ee i7-2920xm"],"fields":[{"key":"Model name","value":"Core i7-2920XM Extreme","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2920XM","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700834406","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR02E","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 9, 2011","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 9, 2011","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-634376043bd9aa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-2920xm&oldid=25289","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7827-r25289","location":"Intel/core i7ee/i7-2920xm · revision 25289 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-634c0c72db099fd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2397m&oldid=25576","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701048003","unit":"","sourceId":"chipswiki-7995-r25576","location":"Intel/core i3/i3-2397m · revision 25576 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-63a674c5e2b47944","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsouthern%20islands&oldid=13597","sourceDate":"2018-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2012,"unit":"","sourceId":"chipswiki-4228-r13597","location":"Amd/microarchitectures/southern islands · revision 13597 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-21. Not an independent measurement.","entityId":"cw-63a674c5e2b47944","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsouthern%20islands&oldid=13597","sourceDate":"2018-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-4228-r13597","location":"Amd/microarchitectures/southern islands · revision 13597 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-21. Not an independent measurement.","entityId":"cw-63a674c5e2b47944","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsouthern%20islands&oldid=13597","sourceDate":"2018-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Sea Islands","unit":"","sourceId":"chipswiki-4228-r13597","location":"Amd/microarchitectures/southern islands · revision 13597 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-21. Not an independent measurement.","entityId":"cw-63a674c5e2b47944","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fsouthern%20islands&oldid=13597","sourceDate":"2018-12-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4228-r13597"],"url":"https://museum.vlsi.kr/objects/cw-63a674c5e2b47944"},{"id":"cw-63c0d7b638c7bd75","name":"Am186ED–20KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186ed–20kc\\w"],"fields":[{"key":"Model name","value":"Am186ED–20KC\\W","unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ED–20KC\\W","unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ED–20KC\\W","unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-63c0d7b638c7bd75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14672-r44733","location":"Amd/am186ex/am186ed–20kc\\w · revision 44733 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-2104","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. 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Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3LH","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 29, 2017","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-2000","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Basin Falls","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake W","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. 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Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x1 MiB","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8.25,"unit":"MiB","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.375 MiB","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":71.53,"unit":"GiB/s","sourceId":"chipswiki-4517-r14681","location":"Intel/xeon w/w-2104 · revision 14681 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-24. Not an independent measurement.","entityId":"cw-63cdaa3b6df681b3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2104&oldid=14681","sourceDate":"2018-10-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4517-r14681"],"url":"https://museum.vlsi.kr/objects/cw-63cdaa3b6df681b3"},{"id":"cw-640d0a4555ff95b8","name":"Cortex-M55","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2020,"process":"55 nm","aliases":["Arm holdings microarchitectures cortex-m55"],"fields":[{"key":"Architecture name","value":"Cortex-M55","unit":"","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"February 10, 2020","unit":"","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":55,"unit":"nm","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / process 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 3","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"process 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / process 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 4","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"process 4","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / process 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 5","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"process 5","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / process 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 6","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"process 6","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / process 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 7","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"process 7","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Scalar","unit":"","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"1-2-way","unit":"","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.1-M","unit":"","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-M4","unit":"","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-M7","unit":"","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / predecessor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"predecessor 2","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"predecessor 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / process 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 8","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"process 8","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":5,"unit":"nm","sourceId":"chipswiki-850-r2224","location":"Arm holdings/microarchitectures/cortex-m55 · revision 2224 · {{microarchitecture}} / process 9","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 9","note":"Source-reported parameter; source revision 2021-01-12. Not an independent measurement.","entityId":"cw-640d0a4555ff95b8","scope":"process 9","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","sourceDate":"2021-01-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-850-r2224"],"url":"https://museum.vlsi.kr/objects/cw-640d0a4555ff95b8"},{"id":"cw-642bdbc1e223a529","name":"AMD-K6-III/380AFK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III Mobile","year":1999,"architecture":"K6-III","process":"0.25 µm","aliases":["Amd k6-iii-p amd-k6-iii-380afk"],"fields":[{"key":"Model name","value":"AMD-K6-III/380AFK","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III/380AFK","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III/380AFK","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 31, 1999","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 31, 1999","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III-P","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III Mobile","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":380,"unit":"MHz","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95 MT/s","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sharptooth","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":9,"unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21300000,"unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118,"unit":"mm²","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-642bdbc1e223a529","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii-p%2Famd-k6-iii-380afk&oldid=25997","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8307-r25997","location":"Amd/k6-iii-p/amd-k6-iii-380afk · revision 25997 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6456aab297e839d3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Falder%20lake&oldid=97011","sourceDate":"2022-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Gracemont","unit":"","sourceId":"chipswiki-61-r97011","location":"Intel/microarchitectures/alder lake · revision 97011 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-10-11. 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Not an independent measurement.","entityId":"cw-6456aab297e839d3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Falder%20lake&oldid=97011","sourceDate":"2022-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Rocket Lake","unit":"","sourceId":"chipswiki-61-r97011","location":"Intel/microarchitectures/alder lake · revision 97011 · {{microarchitecture}} / predecessor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"predecessor 2","note":"Source-reported parameter; source revision 2022-10-11. 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Not an independent measurement.","entityId":"cw-6456aab297e839d3","scope":"predecessor 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Falder%20lake&oldid=97011","sourceDate":"2022-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Raptor Lake","unit":"","sourceId":"chipswiki-61-r97011","location":"Intel/microarchitectures/alder lake · revision 97011 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-11. Not an independent measurement.","entityId":"cw-6456aab297e839d3","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Falder%20lake&oldid=97011","sourceDate":"2022-10-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Meteor Lake","unit":"","sourceId":"chipswiki-61-r97011","location":"Intel/microarchitectures/alder lake · revision 97011 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2022-10-11. Not an independent measurement.","entityId":"cw-6456aab297e839d3","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Falder%20lake&oldid=97011","sourceDate":"2022-10-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-61-r97011"],"url":"https://museum.vlsi.kr/objects/cw-6456aab297e839d3"},{"id":"cw-646fcdb0ceea2641","name":"NNP-I 1100","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"NNP-I","year":2019,"architecture":"Spring Hill","process":"10 nm","aliases":["Nervana nnp nnp-i 1100"],"fields":[{"key":"Model name","value":"NNP-I 1100","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"NNP-I 1100","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 12, 2019","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 12, 2019","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"NNP","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"NNP-I","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Spring Hill","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8500000000,"unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":239,"unit":"mm²","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":12,"unit":"W","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-4200","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"67.2 GB/s","unit":"","sourceId":"chipswiki-1355-r4484","location":"Nervana/nnp/nnp-i 1100 · revision 4484 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-646fcdb0ceea2641","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201100&oldid=4484","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1355-r4484"],"url":"https://museum.vlsi.kr/objects/cw-646fcdb0ceea2641"},{"id":"cw-648367343c58f456","name":"Xeon D-2166NT","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-2000","year":2018,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon d d-2166nt"],"fields":[{"key":"Model name","value":"Xeon D-2166NT","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2166NT","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8067303784301","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZX","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DE","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M1","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7149-r22568","location":"Intel/xeon d/d-2166nt · revision 22568 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-648367343c58f456","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701022601","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 16, 2012","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 16, 2012","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7794-r25232","location":"Intel/pentium (2009)/977 · revision 25232 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F977&oldid=25232","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64cc012914589f67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7794-r25232","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-64cc012914589f67"},{"id":"cw-64d1fe39d9d8640c","name":"K6-2E/233AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-233afr"],"fields":[{"key":"Model name","value":"K6-2E/233AFR","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/233AFR","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/233AFR","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1999","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":233.33,"unit":"MHz","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8331-r26026","location":"Amd/k6-2/k6-2e-233afr · revision 26026 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64d1fe39d9d8640c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-233afr&oldid=26026","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8331-r26026"],"url":"https://museum.vlsi.kr/objects/cw-64d1fe39d9d8640c"},{"id":"cw-64e51ed1c451ebc9","name":"AM9080APC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080apc"],"fields":[{"key":"Model name","value":"AMD AM9080APC","unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080APC","unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080APC","unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.083,"unit":"MHz","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"DIP-40","unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"DIP","unit":"","sourceId":"chipswiki-8464-r26657","location":"Amd/am9080/am9080apc · revision 26657 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64e51ed1c451ebc9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8464-r26657"],"url":"https://museum.vlsi.kr/objects/cw-64e51ed1c451ebc9"},{"id":"cw-64eab0f37912f5d6","name":"CN5734-900 SSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5734-900bg1217-ssp"],"fields":[{"key":"Model name","value":"Cavium CN5734-900 SSP","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5734-900 SSP","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5734-900BG1217-SSP","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":288,"unit":"KiB","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x16 KiB","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8186-r25845","location":"Cavium/octeon plus/cn5734-900bg1217-ssp · revision 25845 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-64eab0f37912f5d6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8186-r25845","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-64eab0f37912f5d6"},{"id":"cw-64ecf7ea69750fce","name":"Isaiah","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"VIA Technologies","year":null,"process":"65 nm","aliases":["Via technologies microarchitectures isaiah"],"fields":[{"key":"Architecture name","value":"Isaiah","unit":"","sourceId":"chipswiki-7370-r23828","location":"Via technologies/microarchitectures/isaiah · revision 23828 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-16. Not an independent measurement.","entityId":"cw-64ecf7ea69750fce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah&oldid=23828","sourceDate":"2018-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"VIA Technologies","unit":"","sourceId":"chipswiki-7370-r23828","location":"Via technologies/microarchitectures/isaiah · revision 23828 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-16. Not an independent measurement.","entityId":"cw-64ecf7ea69750fce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah&oldid=23828","sourceDate":"2018-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Fujitsu","unit":"","sourceId":"chipswiki-7370-r23828","location":"Via technologies/microarchitectures/isaiah · revision 23828 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-16. Not an independent measurement.","entityId":"cw-64ecf7ea69750fce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah&oldid=23828","sourceDate":"2018-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7370-r23828","location":"Via technologies/microarchitectures/isaiah · revision 23828 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2018-01-16. Not an independent measurement.","entityId":"cw-64ecf7ea69750fce","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah&oldid=23828","sourceDate":"2018-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-7370-r23828","location":"Via technologies/microarchitectures/isaiah · revision 23828 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-16. Not an independent measurement.","entityId":"cw-64ecf7ea69750fce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah&oldid=23828","sourceDate":"2018-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-7370-r23828","location":"Via technologies/microarchitectures/isaiah · revision 23828 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2018-01-16. Not an independent measurement.","entityId":"cw-64ecf7ea69750fce","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah&oldid=23828","sourceDate":"2018-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-7370-r23828","location":"Via technologies/microarchitectures/isaiah · revision 23828 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-16. Not an independent measurement.","entityId":"cw-64ecf7ea69750fce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah&oldid=23828","sourceDate":"2018-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7370-r23828","location":"Via technologies/microarchitectures/isaiah · revision 23828 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-16. Not an independent measurement.","entityId":"cw-64ecf7ea69750fce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah&oldid=23828","sourceDate":"2018-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Esther","unit":"","sourceId":"chipswiki-7370-r23828","location":"Via technologies/microarchitectures/isaiah · revision 23828 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-16. Not an independent measurement.","entityId":"cw-64ecf7ea69750fce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah&oldid=23828","sourceDate":"2018-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Isaiah II","unit":"","sourceId":"chipswiki-7370-r23828","location":"Via technologies/microarchitectures/isaiah · revision 23828 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-16. Not an independent measurement.","entityId":"cw-64ecf7ea69750fce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fisaiah&oldid=23828","sourceDate":"2018-01-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7370-r23828"],"url":"https://museum.vlsi.kr/objects/cw-64ecf7ea69750fce"},{"id":"cw-6526d4e44ea6098d","name":"Xeon Platinum 8158","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8158"],"fields":[{"key":"Model name","value":"Xeon Platinum 8158","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":8158,"unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303406500","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3B7","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. 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Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-2561-r8829","location":"Intel/xeon platinum/8158 · revision 8829 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6526d4e44ea6098d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8158&oldid=8829","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2561-r8829"],"url":"https://museum.vlsi.kr/objects/cw-6526d4e44ea6098d"},{"id":"cw-654289b2e7d78894","name":"EPYC 7552","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7552"],"fields":[{"key":"Model name","value":"EPYC 7552","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7552,"unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000076","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000076WOF","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3350,"unit":"MHz","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":48,"unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":96,"unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":200,"unit":"W","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":3,"unit":"MiB","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"48x32 KiB","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"48x32 KiB","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"48x512 KiB","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":192,"unit":"MiB","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x16 MiB","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-865-r2249","location":"Amd/epyc/7552 · revision 2249 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-654289b2e7d78894","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-865-r2249"],"url":"https://museum.vlsi.kr/objects/cw-654289b2e7d78894"},{"id":"cw-654aa62f3666256f","name":"Core i7-4770R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2013,"architecture":"Haswell","process":"22 nm","aliases":["Intel core i7 i7-4770r"],"fields":[{"key":"Model name","value":"Intel Core i7-4770R","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-4770R","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8064701508001","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 2, 2013","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 4, 2013","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR18K","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Shark Bay","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7869-r25372","location":"Intel/core i7/i7-4770r · revision 25372 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4770r&oldid=25372","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-654aa62f3666256f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMSN2600DUT4C","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 6, 2003","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 6, 2003","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Barton","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":10,"unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":54300000,"unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":101,"unit":"mm²","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":60,"unit":"W","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8446-r26639","location":"Amd/athlon mp/amsn2600dut4c · revision 26639 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2600dut4c&oldid=26639","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-658681a71fd7b0ac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8446-r26639","chipswiki-31459-r92404"],"url":"https://museum.vlsi.kr/objects/cw-658681a71fd7b0ac"},{"id":"cw-6588e18da1aa273c","name":"Xeon E5-2628L v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2628l v4"],"fields":[{"key":"Model name","value":"Xeon E5-2628L v4","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2628L v4","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002044903","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2NC","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":75,"unit":"W","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x256 KiB","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":30,"unit":"MiB","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x2.5 MiB","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7742-r25119","location":"Intel/xeon e5/e5-2628l v4 · revision 25119 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6588e18da1aa273c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2628l%20v4&oldid=25119","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7742-r25119"],"url":"https://museum.vlsi.kr/objects/cw-6588e18da1aa273c"},{"id":"cw-659683a834239ff5","name":"X704-500","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Exponential Technology","year":null,"architecture":"X704","process":"500 nm","aliases":["Exponential technology x704 500"],"fields":[{"key":"Model name","value":"X704-500","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Exponential Technology","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Hitachi","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 1997","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"60x bus","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"X704","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"CHRP","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2700000,"unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"BiCMOS","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":150,"unit":"mm²","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.6,"unit":"V","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-359","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CBGA","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-359","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"KiB","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x2 KiB","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"direct mapped","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"KiB","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x2 KiB","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"direct mapped","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"KiB","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8110-r25769","location":"Exponential technology/x704/500 · revision 25769 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-659683a834239ff5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F500&oldid=25769","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8110-r25769"],"url":"https://museum.vlsi.kr/objects/cw-659683a834239ff5"},{"id":"cw-65ccd0f889bcaa15","name":"Athlon PRO 200GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"PRO 200","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd athlon pro 200ge"],"fields":[{"key":"Model name","value":"Athlon PRO 200GE","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 200GE","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD200BC6M2OFB","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 6, 2018","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 6, 2018","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"PRO 200","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-1816-r6087","location":"Amd/athlon/pro 200ge · revision 6087 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20200ge&oldid=6087","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-65ccd0f889bcaa15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1816-r6087","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-65ccd0f889bcaa15"},{"id":"cw-65dc43897d6a6ae7","name":"K6-2/533AFX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-533afx"],"fields":[{"key":"Model name","value":"K6-2/533AFX","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/533AFX","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/533AFX","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 26, 1999","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 11, 1999","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":533.33,"unit":"MHz","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"96.99 MT/s","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8334-r26029","location":"Amd/k6-2/k6-2-533afx · revision 26029 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-65dc43897d6a6ae7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-533afx&oldid=26029","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8334-r26029"],"url":"https://museum.vlsi.kr/objects/cw-65dc43897d6a6ae7"},{"id":"cw-6618e97641427c94","name":"Xeon E7-8867L","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-8800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-8867l"],"fields":[{"key":"Model name","value":"Xeon E7-8867L","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-8867L","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615007002AB","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-8800","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2133.33,"unit":"MHz","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2533.33,"unit":"MHz","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3P","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Boxboro","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6618e97641427c94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8867l&oldid=25062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7692-r25062","location":"Intel/xeon e7/e7-8867l · revision 25062 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 25, 2020","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"R1000","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2600,"unit":"MHz","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","alternatives":[{"value":"16 GiB","sourceId":"chipswiki-925-r2549","reason":"Amd/ryzen embedded/r1102g · revision 2549 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2 × 64 KiB","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2 × 32 KiB","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2 × 512 KiB","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1 × 4 MiB","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":17.88,"unit":"GiB/s","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-925-r2549","location":"Amd/ryzen embedded/r1102g · revision 2549 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-662ac8edb6259e62","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1102g&oldid=2549","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-925-r2549"],"url":"https://museum.vlsi.kr/objects/cw-662ac8edb6259e62"},{"id":"cw-66433de29a965a60","name":"Pentium Gold 4415Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel pentium gold 4415y"],"fields":[{"key":"Model name","value":"Pentium Gold 4415Y","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4415Y","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702740018","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3GA","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 4, 2017","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 4, 2017","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake Y","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 615","unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":850,"unit":"MHz","sourceId":"chipswiki-4973-r16095","location":"Intel/pentium gold/4415y · revision 16095 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-66433de29a965a60","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F4415y&oldid=16095","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4973-r16095"],"url":"https://museum.vlsi.kr/objects/cw-66433de29a965a60"},{"id":"cw-664b66446a0d1d5c","name":"PEZY-1","kind":"sku","entityType":"product-model","subtype":"cpu","company":"PEZY","year":2012,"process":"40 nm","aliases":["Pezy pezy-1"],"fields":[{"key":"Model name","value":"PEZY-1","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"PEZY","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PEZY-1","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Industrial","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2011,"unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":533.33,"unit":"MHz","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":335,"unit":"mm²","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":512,"unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-1517","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1517","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4656-r14921","location":"Pezy/pezy-1 · revision 14921 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-20. Not an independent measurement.","entityId":"cw-664b66446a0d1d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Pezy%2Fpezy-1&oldid=14921","sourceDate":"2018-10-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4656-r14921"],"url":"https://museum.vlsi.kr/objects/cw-664b66446a0d1d5c"},{"id":"cw-665362d2f9cb4faf","name":"Atom Z530","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z500","year":2008,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z530"],"fields":[{"key":"Model name","value":"Atom Z530","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z530","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AC80566UE025DW","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLB6P","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z500","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1599.99,"unit":"MHz","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"533.33 MT/s","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Menlow","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Poulsbo","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":28,"unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":24.18,"unit":"mm²","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2.2,"unit":"W","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8064-r25700","location":"Intel/atom/z530 · revision 25700 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530&oldid=25700","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-441","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":441,"unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":14,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-665362d2f9cb4faf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8064-r25700","chipswiki-31513-r92656"],"url":"https://museum.vlsi.kr/objects/cw-665362d2f9cb4faf"},{"id":"cw-66624b7f872e67ce","name":"Am186ER–33VI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1996,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–33vi\\w"],"fields":[{"key":"Model name","value":"Am186ER–33VI\\W","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–33VI\\W","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–33VI\\W","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 1996","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1996","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8.25 MT/s","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14641-r44702","location":"Amd/am186ex/am186er–33vi\\w · revision 44702 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-66624b7f872e67ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14641-r44702"],"url":"https://museum.vlsi.kr/objects/cw-66624b7f872e67ce"},{"id":"cw-66668ab11887282b","name":"Xeon Gold 5215M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 5215m"],"fields":[{"key":"Model name","value":"Xeon Gold 5215M","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5215M","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504214102","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFBD","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5200,"unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L0","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L1","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":10,"unit":"MiB","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x1 MiB","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":13.75,"unit":"MiB","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x1.375 MiB","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1528-r4982","location":"Intel/xeon gold/5215m · revision 4982 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-66668ab11887282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5215m&oldid=4982","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1528-r4982"],"url":"https://museum.vlsi.kr/objects/cw-66668ab11887282b"},{"id":"cw-668452621ca67de6","name":"Ryzen 7 5700U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 7 5700u"],"fields":[{"key":"Model name","value":"Ryzen 7 5700U","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5700U","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000371","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lucienne","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":104,"unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1900,"unit":"MHz","sourceId":"chipswiki-87-r97044","location":"Amd/ryzen 7/5700u · revision 97044 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-06. Not an independent measurement.","entityId":"cw-668452621ca67de6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","sourceDate":"2022-10-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-87-r97044"],"url":"https://museum.vlsi.kr/objects/cw-668452621ca67de6"},{"id":"cw-668e5f0ca3aebada","name":"Atom C3955","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom c3955"],"fields":[{"key":"Model name","value":"Atom C3955","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"C3955","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HW8076503528301","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3F3","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2017","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2400,"unit":"MHz","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Denverton","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":95,"unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":256,"unit":"GiB","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":32,"unit":"W","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":896,"unit":"KiB","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x24 KiB","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-1869-r6405","location":"Intel/atom/c3955 · revision 6405 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","sourceDate":"2019-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1310","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1310,"unit":"","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31416-r92275","location":"Template:Packages/intel/fcbga-1310 · revision 92275 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-08-15. Not an independent measurement.","entityId":"cw-668e5f0ca3aebada","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1310&oldid=92275","sourceDate":"2017-08-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1869-r6405","chipswiki-31416-r92275"],"url":"https://museum.vlsi.kr/objects/cw-668e5f0ca3aebada"},{"id":"cw-6699f033c29ee493","name":"Core i7-4940MX Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-4000","year":2014,"architecture":"Haswell","process":"22 nm","aliases":["Intel core i7ee i7-4940mx"],"fields":[{"key":"Model name","value":"Core i7-4940MX Extreme Edition","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-4940MX","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CW8064701474604","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 19, 2014","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 19, 2014","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-4000","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR1PP","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Shark Bay","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Haswell","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":57,"unit":"W","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket G3","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7823-r25282","location":"Intel/core i7ee/i7-4940mx · revision 25282 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6699f033c29ee493","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4940mx&oldid=25282","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7823-r25282"],"url":"https://museum.vlsi.kr/objects/cw-6699f033c29ee493"},{"id":"cw-66b1f345916975bd","name":"EPYC 7232P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7232p"],"fields":[{"key":"Model name","value":"EPYC 7232P","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7232P","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000081","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000081WOF","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x8 MiB","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-221-r452","location":"Amd/epyc/7232p · revision 452 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-19. Not an independent measurement.","entityId":"cw-66b1f345916975bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","sourceDate":"2022-08-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-221-r452"],"url":"https://museum.vlsi.kr/objects/cw-66b1f345916975bd"},{"id":"cw-66c0af5cfb45f507","name":"AM9080ADIB","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080adib"],"fields":[{"key":"Model name","value":"AMD AM9080ADIB","unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080ADIB","unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080ADIB","unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Industrial","unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.083,"unit":"MHz","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8466-r26659","location":"Amd/am9080/am9080adib · revision 26659 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-66c0af5cfb45f507","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8466-r26659"],"url":"https://museum.vlsi.kr/objects/cw-66c0af5cfb45f507"},{"id":"cw-66ed8b7e26162e19","name":"Snapdragon 632","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","series":"600","year":2018,"architecture":"Cortex-A73","process":"14 nm","aliases":["Qualcomm snapdragon 600 632"],"fields":[{"key":"Model name","value":"Snapdragon 632","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM632","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 26, 2018","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 26, 2018","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 600","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":600,"unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A73","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 250 Gold","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 250 Silver","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 506","unit":"","sourceId":"chipswiki-793-r1990","location":"Qualcomm/snapdragon 600/632 · revision 1990 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-04-02. Not an independent measurement.","entityId":"cw-66ed8b7e26162e19","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F632&oldid=1990","sourceDate":"2021-04-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-793-r1990"],"url":"https://museum.vlsi.kr/objects/cw-66ed8b7e26162e19"},{"id":"cw-6709088c9c436206","name":"Snapdragon 730","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","year":2019,"architecture":"Cortex-A76","process":"8 nm","aliases":["Qualcomm snapdragon 700 730"],"fields":[{"key":"Model name","value":"Snapdragon 730","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM730","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 9, 2019","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 9, 2019","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 700","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2200,"unit":"MHz","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1800,"unit":"MHz","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A76","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 470 Gold","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 470 Silver","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":8,"unit":"nm","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 618","unit":"","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-616-r1447","location":"Qualcomm/snapdragon 700/730 · revision 1447 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-10. Not an independent measurement.","entityId":"cw-6709088c9c436206","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F730&oldid=1447","sourceDate":"2021-09-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-616-r1447"],"url":"https://museum.vlsi.kr/objects/cw-6709088c9c436206"},{"id":"cw-671269a7dc20a5b6","name":"Diamond Rapids","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2025,"process":"7 nm","aliases":["Intel microarchitectures diamond rapids"],"fields":[{"key":"Architecture name","value":"Diamond Rapids","unit":"","sourceId":"chipswiki-505-r1004","location":"Intel/microarchitectures/diamond rapids · revision 1004 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-671269a7dc20a5b6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fdiamond%20rapids&oldid=1004","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-505-r1004","location":"Intel/microarchitectures/diamond rapids · revision 1004 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. 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Not an independent measurement.","entityId":"cw-671269a7dc20a5b6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fdiamond%20rapids&oldid=1004","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2025,"unit":"","sourceId":"chipswiki-505-r1004","location":"Intel/microarchitectures/diamond rapids · revision 1004 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-671269a7dc20a5b6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fdiamond%20rapids&oldid=1004","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-505-r1004","location":"Intel/microarchitectures/diamond rapids · revision 1004 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-671269a7dc20a5b6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fdiamond%20rapids&oldid=1004","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-505-r1004","location":"Intel/microarchitectures/diamond rapids · revision 1004 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-671269a7dc20a5b6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fdiamond%20rapids&oldid=1004","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Granite Rapids","unit":"","sourceId":"chipswiki-505-r1004","location":"Intel/microarchitectures/diamond rapids · revision 1004 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-21. Not an independent measurement.","entityId":"cw-671269a7dc20a5b6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fdiamond%20rapids&oldid=1004","sourceDate":"2022-02-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-505-r1004"],"url":"https://museum.vlsi.kr/objects/cw-671269a7dc20a5b6"},{"id":"cw-6712bbb8715925fa","name":"Core i3-7350K","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-7300","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i3 i3-7350k"],"fields":[{"key":"Model name","value":"Core i3-7350K","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-7350K","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80677I37350K","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80677I37350K","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-24. 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Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35B","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. 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Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. 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Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. 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Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. 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Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. 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Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":60,"unit":"W","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7587-r24647","location":"Intel/core i3/i3-7350k · revision 24647 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-24. Not an independent measurement.","entityId":"cw-6712bbb8715925fa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7350k&oldid=24647","sourceDate":"2017-12-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7587-r24647"],"url":"https://museum.vlsi.kr/objects/cw-6712bbb8715925fa"},{"id":"cw-672dc565b4276591","name":"Pentium Gold 5405U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2019,"architecture":"Whiskey Lake","process":"14 nm","aliases":["Intel pentium gold 5405u"],"fields":[{"key":"Model name","value":"Pentium Gold 5405U","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5405U","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8068404080703","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRESL","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Q1, 2019","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"Q1, 2019","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Whiskey Lake","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Whiskey Lake","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Whiskey Lake U","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"W0","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-04-19. 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Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. Not an independent measurement.","entityId":"cw-672dc565b4276591","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2F5405u&oldid=10186","sourceDate":"2019-04-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 610","unit":"","sourceId":"chipswiki-3042-r10186","location":"Intel/pentium gold/5405u · revision 10186 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-19. 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Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701079802","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701345700","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR07H","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0EF","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0PX","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0VM","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-6943-r21630","location":"Intel/celeron/817 · revision 21630 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-672ddce8c15f28c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–33KI\\W","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–33KI\\W","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 1996","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1996","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8.25 MT/s","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14643-r44704","location":"Amd/am186ex/am186er–33ki\\w · revision 44704 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6783b9a83292a36d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14643-r44704"],"url":"https://museum.vlsi.kr/objects/cw-6783b9a83292a36d"},{"id":"cw-678650c078a2c241","name":"z900","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2000,"process":"0.18 µm","aliases":["Ibm microarchitectures z900"],"fields":[{"key":"Architecture name","value":"z900","unit":"","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October 3, 2000","unit":"","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":12,"unit":"","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Scalar","unit":"","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":7,"unit":"","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"z/Architecture","unit":"","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"8-16 MiB","unit":"","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"cluster","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"cluster","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"ESA/390 G6","unit":"","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"z990","unit":"","sourceId":"chipswiki-13218-r38691","location":"Ibm/microarchitectures/z900 · revision 38691 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-19. Not an independent measurement.","entityId":"cw-678650c078a2c241","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz900&oldid=38691","sourceDate":"2017-07-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-13218-r38691"],"url":"https://museum.vlsi.kr/objects/cw-678650c078a2c241"},{"id":"cw-67b16e07dbee17b2","name":"CN5840-900 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5840-900bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5840-900 SCP","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5840-900 SCP","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5840-900BG1521-SCP","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8138-r25797","location":"Cavium/octeon plus/cn5840-900bg1521-scp · revision 25797 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-scp&oldid=25797","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67b16e07dbee17b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8138-r25797","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-67b16e07dbee17b2"},{"id":"cw-67d2d2351eca88c5","name":"A6-9220C","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"A6-9000","year":2019,"architecture":"Excavator","process":"28 nm","aliases":["Amd a6 a6-9220c"],"fields":[{"key":"Model name","value":"A6-9220C","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A6-9220C","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM922CANN23AC","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"A6","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"A6-9000","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Excavator","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Bristol Ridge","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":96,"unit":"KiB","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x96 KiB","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1866","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon R5 Series","unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":720,"unit":"MHz","sourceId":"chipswiki-4039-r12917","location":"Amd/a6/a6-9220c · revision 12917 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-07. Not an independent measurement.","entityId":"cw-67d2d2351eca88c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","sourceDate":"2019-01-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4039-r12917"],"url":"https://museum.vlsi.kr/objects/cw-67d2d2351eca88c5"},{"id":"cw-67ddc4f26770d0cc","name":"K6-2/300AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1998,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-300afr"],"fields":[{"key":"Model name","value":"K6-2/300AFR","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/300AFR","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/300AFR","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 4, 1998","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8382-r26077","location":"Amd/k6-2/k6-2-300afr · revision 26077 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67ddc4f26770d0cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300afr&oldid=26077","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8382-r26077"],"url":"https://museum.vlsi.kr/objects/cw-67ddc4f26770d0cc"},{"id":"cw-67ee7cce2f733d70","name":"POWER9","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2017,"process":"14 nm","aliases":["Ibm microarchitectures power9"],"fields":[{"key":"Architecture name","value":"POWER9","unit":"","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"August, 2017","unit":"","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":4,"unit":"","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core duplex","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"core duplex","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":10,"unit":"MiB","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core duplex","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"core duplex","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Monza","unit":"","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"LaGrange","unit":"","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"POWER8+","unit":"","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"POWER10","unit":"","sourceId":"chipswiki-1124-r3339","location":"Ibm/microarchitectures/power9 · revision 3339 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-23. Not an independent measurement.","entityId":"cw-67ee7cce2f733d70","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","sourceDate":"2020-05-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1124-r3339"],"url":"https://museum.vlsi.kr/objects/cw-67ee7cce2f733d70"},{"id":"cw-67f23bd67ee82630","name":"Godson-2E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Loongson","series":"Godson 2","year":2006,"architecture":"GS464","process":"90 nm","aliases":["Loongson godson 2 2e"],"fields":[{"key":"Model name","value":"Godson-2E","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Loongson","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"STMicroelectronics","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2E","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CZ70","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2006,"unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 18, 2006","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Godson 2","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Godson 2","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"SysAD","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"GS464","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"GS464","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47000000,"unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":36,"unit":"mm²","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-333","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":4.967,"unit":"GiB/s","sourceId":"chipswiki-7680-r24975","location":"Loongson/godson 2/2e · revision 24975 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-67f23bd67ee82630","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2e&oldid=24975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7680-r24975"],"url":"https://museum.vlsi.kr/objects/cw-67f23bd67ee82630"},{"id":"cw-6809ab38d4088301","name":"Am186EDLV–25KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186edlv–25kc\\w"],"fields":[{"key":"Model name","value":"Am186EDLV–25KC\\W","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EDLV–25KC\\W","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EDLV–25KC\\W","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14674-r44735","location":"Amd/am186ex/am186edlv–25kc\\w · revision 44735 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-6809ab38d4088301","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14674-r44735"],"url":"https://museum.vlsi.kr/objects/cw-6809ab38d4088301"},{"id":"cw-6817a84e389c0737","name":"AMD-X5-133SDW","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":1996,"architecture":"80486","process":"350 nm","aliases":["Amd am5x86 amd-x5-133sdw"],"fields":[{"key":"Model name","value":"AMD-X5-133SDW","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-X5-133SDW","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-X5-133SDW","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1996,"unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am5x86","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":133,"unit":"MHz","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5x","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1600000,"unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":43,"unit":"mm²","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.45,"unit":"V","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SQFP-208","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SQFP","unit":"","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8528-r26723","location":"Amd/am5x86/amd-x5-133sdw · revision 26723 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6817a84e389c0737","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8528-r26723"],"url":"https://museum.vlsi.kr/objects/cw-6817a84e389c0737"},{"id":"cw-684db51604a81236","name":"Duron 850 (Camaro)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhm0850als1b"],"fields":[{"key":"Model name","value":"Duron 850","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 850","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHM0850ALS1B","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 14, 2001","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 14, 2001","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":850,"unit":"MHz","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8416-r26124","location":"Amd/duron/dhm0850als1b · revision 26124 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-684db51604a81236","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8416-r26124"],"url":"https://museum.vlsi.kr/objects/cw-684db51604a81236"},{"id":"cw-68521bd7e30ef116","name":"Duron 800 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron d800avs1b"],"fields":[{"key":"Model name","value":"Duron 800","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 800","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D800AVS1B","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2001","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2001","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":33.2,"unit":"W","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8432-r26140","location":"Amd/duron/d800avs1b · revision 26140 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68521bd7e30ef116","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8432-r26140"],"url":"https://museum.vlsi.kr/objects/cw-68521bd7e30ef116"},{"id":"cw-6856c0de68155d15","name":"Celeron P4500","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P4000","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel celeron p4500"],"fields":[{"key":"Model name","value":"Intel Celeron P4500","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P4500","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004803AA","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 28, 2010","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 28, 2010","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P4000","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1866.66,"unit":"MHz","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBNL","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":667,"unit":"MHz","sourceId":"chipswiki-8026-r25608","location":"Intel/celeron/p4500 · revision 25608 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA-988A","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"rPGA","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":36,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":35,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.12,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6856c0de68155d15","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8026-r25608","chipswiki-31578-r92969"],"url":"https://museum.vlsi.kr/objects/cw-6856c0de68155d15"},{"id":"cw-687a195cd1af9346","name":"Xeon Gold 6262V","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6262v"],"fields":[{"key":"Model name","value":"Xeon Gold 6262V","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6262,"unit":"V","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":135,"unit":"W","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":33,"unit":"MiB","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"24x1.375 MiB","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1475-r4923","location":"Intel/xeon gold/6262v · revision 4923 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-687a195cd1af9346","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6262v&oldid=4923","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1475-r4923"],"url":"https://museum.vlsi.kr/objects/cw-687a195cd1af9346"},{"id":"cw-688121255660a13d","name":"Duron 700 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2000,"architecture":"K7","process":"180 nm","aliases":["Amd duron d700aut1b"],"fields":[{"key":"Model name","value":"Duron 700","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 700","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D700AUT1B","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D0700AUT1B","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2000","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 19, 2000","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":700,"unit":"MHz","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":31.4,"unit":"W","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8437-r26145","location":"Amd/duron/d700aut1b · revision 26145 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-688121255660a13d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8437-r26145"],"url":"https://museum.vlsi.kr/objects/cw-688121255660a13d"},{"id":"cw-68814e50b03a5fdd","name":"Xeon D-2145NT","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-2000","year":2018,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon d d-2145nt"],"fields":[{"key":"Model name","value":"Xeon D-2145NT","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2145NT","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8067303782801","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZT","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DE","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M1","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-7151-r22574","location":"Intel/xeon d/d-2145nt · revision 22574 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-68814e50b03a5fdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":52.5,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-689fe2c5402ca263","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhayes&oldid=620","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-306-r620","location":"Arm holdings/microarchitectures/hayes · revision 620 · {{microarchitecture}} / manufacturer 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 3","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-689fe2c5402ca263","scope":"manufacturer 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhayes&oldid=620","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"SMIC","unit":"","sourceId":"chipswiki-306-r620","location":"Arm holdings/microarchitectures/hayes · revision 620 · {{microarchitecture}} / manufacturer 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 4","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-689fe2c5402ca263","scope":"manufacturer 4","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhayes&oldid=620","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2023,"unit":"","sourceId":"chipswiki-306-r620","location":"Arm holdings/microarchitectures/hayes · revision 620 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-689fe2c5402ca263","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhayes&oldid=620","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-A510","unit":"","sourceId":"chipswiki-306-r620","location":"Arm holdings/microarchitectures/hayes · revision 620 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. 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Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2377M","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701048004","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0CW","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2012","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8000-r25581","location":"Intel/core i3/i3-2377m · revision 25581 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2377m&oldid=25581","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-68c3096529365143","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 9","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4700,"unit":"MHz","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Vermeer","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":33,"unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x512 KiB","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x32 MiB","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-724-r1738","location":"Amd/ryzen 9/5900 · revision 1738 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-28. Not an independent measurement.","entityId":"cw-68fddabd835ab262","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","sourceDate":"2021-05-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-724-r1738"],"url":"https://museum.vlsi.kr/objects/cw-68fddabd835ab262"},{"id":"cw-691060800a8b2d63","name":"VY86C710","kind":"sku","entityType":"product-model","subtype":"soc","company":"Arm","year":1994,"architecture":"ARM7","process":"0.5 µm","aliases":["Vti vl86cx vy86c710"],"fields":[{"key":"Model name","value":"VY86C710","unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"VY86C710","unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"VY86C710","unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 23, 1994","unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"VL86Cx","unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv3","unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM7","unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM710","unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.5,"unit":"µm","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":570295,"unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":34,"unit":"mm²","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-7625-r24880","location":"Vti/vl86cx/vy86c710 · revision 24880 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710&oldid=24880","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-144","unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":144,"unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":20,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":20,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-691060800a8b2d63","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7625-r24880","chipswiki-31401-r92231"],"url":"https://museum.vlsi.kr/objects/cw-691060800a8b2d63"},{"id":"cw-69266c60fd402276","name":"Zen+","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2018,"process":"12 nm","aliases":["Amd microarchitectures zen+"],"fields":[{"key":"Architecture name","value":"Zen+","unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"April 13, 2018","unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":19,"unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Colfax","unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Pinnacle Ridge","unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Zen","unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Zen 2","unit":"","sourceId":"chipswiki-626-r1478","location":"Amd/microarchitectures/zen+ · revision 1478 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-25. Not an independent measurement.","entityId":"cw-69266c60fd402276","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fzen%2B&oldid=1478","sourceDate":"2021-08-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-626-r1478"],"url":"https://museum.vlsi.kr/objects/cw-69266c60fd402276"},{"id":"cw-6963a6f3c63e7da1","name":"Ryzen Threadripper PRO 3955WX","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3900","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen threadripper pro 3955wx"],"fields":[{"key":"Model name","value":"Ryzen Threadripper PRO 3955WX","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3955WX","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000167","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000167WOF","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 14, 2020","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Threadripper","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3900,"unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3900,"unit":"MHz","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"WRX80","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Castle Peak","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":15940000000,"unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":280,"unit":"W","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16 × 512 KiB","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 16 MiB","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"204.8 GB/s","unit":"","sourceId":"chipswiki-386-r831","location":"Amd/ryzen threadripper/pro 3955wx · revision 831 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%203955wx&oldid=831","sourceDate":"2022-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OLGA","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.87,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":75.4,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":58.5,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":6.26,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-15. Not an independent measurement.","entityId":"cw-6963a6f3c63e7da1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-386-r831","chipswiki-31095-r91554"],"url":"https://museum.vlsi.kr/objects/cw-6963a6f3c63e7da1"},{"id":"cw-6985554e7f39a4f4","name":"Ryzen 5 PRO 3400G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 5 pro 3400g"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 3400G","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 3400G","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD340BC5M4MFH","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933 Mhz","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon RX Vega 11","unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":11,"unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1400,"unit":"MHz","sourceId":"chipswiki-349-r737","location":"Amd/ryzen 5/pro 3400g · revision 737 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-05-23. Not an independent measurement.","entityId":"cw-6985554e7f39a4f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","sourceDate":"2022-05-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-349-r737"],"url":"https://museum.vlsi.kr/objects/cw-6985554e7f39a4f4"},{"id":"cw-69963881e4282470","name":"Xeon Gold 6246","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6246"],"fields":[{"key":"Model name","value":"Xeon Gold 6246","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6246,"unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1480-r4928","location":"Intel/xeon gold/6246 · revision 4928 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-69963881e4282470","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1480-r4928"],"url":"https://museum.vlsi.kr/objects/cw-69963881e4282470"},{"id":"cw-69a0c72886c86aea","name":"ID8086","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"ID8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 id8086"],"fields":[{"key":"Model name","value":"AMD ID8086","unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"ID8086","unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"ID8086","unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"ID8086","unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":5,"unit":"MHz","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8512-r26705","location":"Amd/am8086/id8086 · revision 26705 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a0c72886c86aea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8512-r26705"],"url":"https://museum.vlsi.kr/objects/cw-69a0c72886c86aea"},{"id":"cw-69a22f3bcc07d83d","name":"Am486DX4-120","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX4","year":1995,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx4-120"],"fields":[{"key":"Model name","value":"Am486DX4-120","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-120","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-120","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 1995","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":120,"unit":"MHz","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"40 MT/s","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX4","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8553-r26749","location":"Amd/am486/am486dx4-120 · revision 26749 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-69a22f3bcc07d83d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8553-r26749"],"url":"https://museum.vlsi.kr/objects/cw-69a22f3bcc07d83d"},{"id":"cw-69f2e7a6b73d4413","name":"Xeon Gold 6240M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6240m"],"fields":[{"key":"Model name","value":"Xeon Gold 6240M","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6240M","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. 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Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. 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Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-589-r1362","location":"Intel/xeon gold/6240m · revision 1362 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-10. Not an independent measurement.","entityId":"cw-69f2e7a6b73d4413","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","sourceDate":"2021-10-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-589-r1362"],"url":"https://museum.vlsi.kr/objects/cw-69f2e7a6b73d4413"},{"id":"cw-6a01fe40e0d78161","name":"Core i5-2490M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2490m"],"fields":[{"key":"Model name","value":"Core i5-2490M","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2490M","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701071200","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0GA","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October, 2011","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 2011","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7956-r25504","location":"Intel/core i5/i5-2490m · revision 25504 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2490m&oldid=25504","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a01fe40e0d78161","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7956-r25504","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-6a01fe40e0d78161"},{"id":"cw-6a336533f101d099","name":"A9","kind":"sku","entityType":"product-model","subtype":"soc","company":"Apple","year":2015,"architecture":"Twister","process":"16 nm (TSMC)","aliases":["Apple ax a9"],"fields":[{"key":"Model name","value":"A9","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Apple","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 9, 2015","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2015","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ax","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1850,"unit":"MHz","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Twister","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Twister","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"16 nm (TSMC)","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"14 nm (Samsung)","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":"104.5 mm² (TSMC)","unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-897-r2364","location":"Apple/ax/a9 · revision 2364 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-07. Not an independent measurement.","entityId":"cw-6a336533f101d099","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","sourceDate":"2020-12-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-897-r2364"],"url":"https://museum.vlsi.kr/objects/cw-6a336533f101d099"},{"id":"cw-6a399e298af63c84","name":"CN5860-800 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5860-800bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5860-800 SCP","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5860-800 SCP","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5860-800BG1521-SCP","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x16 KiB","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8117-r25776","location":"Cavium/octeon plus/cn5860-800bg1521-scp · revision 25776 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-scp&oldid=25776","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a399e298af63c84","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8117-r25776","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-6a399e298af63c84"},{"id":"cw-6a5af8a624b45dc3","name":"Core i5-7442EQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-7400","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-7442eq"],"fields":[{"key":"Model name","value":"Core i5-7442EQ","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7442EQ","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8067702998909","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR34U","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7400","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","alternatives":[{"value":"32 GiB","sourceId":"chipswiki-6417-r20017","reason":"Intel/core i5/i5-7442eq · revision 20017 · {{memory controller}} / max mem. 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Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6417-r20017","location":"Intel/core i5/i5-7442eq · revision 20017 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7442eq&oldid=20017","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-6a5af8a624b45dc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. 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Not an independent measurement.","entityId":"cw-6a645370389bc999","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fmadison&oldid=27221","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-8759-r27221","location":"Intel/microarchitectures/madison · revision 27221 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. 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Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-430M","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004161AD","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004161AD","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-400","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2266.66,"unit":"MHz","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2533.33,"unit":"MHz","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBPN","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBPM","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. Not an independent measurement.","entityId":"cw-6a8ffb7de6f6041e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-430m&oldid=14061","sourceDate":"2018-11-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4357-r14061","location":"Intel/core i5/i5-430m · revision 14061 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-26. 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Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-500","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2399.99,"unit":"MHz","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2933.33,"unit":"MHz","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBXK","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":766,"unit":"MHz","sourceId":"chipswiki-7937-r25483","location":"Intel/core i5/i5-520e · revision 25483 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-520e&oldid=25483","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6a984cdb7c7ff88f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. 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Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x5-Z8300","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. 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Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. 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Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x5","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z8000","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1440,"unit":"MHz","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1840,"unit":"MHz","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-01-14. 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Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. 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Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cherry Trail","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. 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Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. 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Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA592","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-3976-r12682","location":"Intel/atom x5/x5-z8300 · revision 12682 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-14. Not an independent measurement.","entityId":"cw-6ab493cf7e8dc0bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","sourceDate":"2019-01-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3976-r12682"],"url":"https://museum.vlsi.kr/objects/cw-6ab493cf7e8dc0bc"},{"id":"cw-6abe3c65a9f2941b","name":"Core i7-4930MX Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-4000","year":2013,"architecture":"Haswell","process":"22 nm","aliases":["Intel core i7ee i7-4930mx"],"fields":[{"key":"Model name","value":"Core i7-4930MX Extreme Edition","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-4930MX","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CW8064701471101","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 4, 2013","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 2, 2013","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-4000","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR15M","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Shark Bay","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Haswell","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":57,"unit":"W","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket G3","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7824-r25283","location":"Intel/core i7ee/i7-4930mx · revision 25283 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6abe3c65a9f2941b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-4930mx&oldid=25283","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7824-r25283"],"url":"https://museum.vlsi.kr/objects/cw-6abe3c65a9f2941b"},{"id":"cw-6abe92766a411031","name":"Ryzen 7 4700G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 7 4700g"],"fields":[{"key":"Model name","value":"Ryzen 7 4700G","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4700G","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000146","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 21, 2020","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2100,"unit":"MHz","sourceId":"chipswiki-701-r1701","location":"Amd/ryzen 7/4700g · revision 1701 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-02. Not an independent measurement.","entityId":"cw-6abe92766a411031","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","sourceDate":"2021-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-701-r1701"],"url":"https://museum.vlsi.kr/objects/cw-6abe92766a411031"},{"id":"cw-6ac4413e3a033f9f","name":"Core i7-660UE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-600","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7 i7-660ue"],"fields":[{"key":"Model name","value":"Intel Core i7-660UE","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-660UE","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617006204AA","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 15, 2010","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 15, 2010","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1333.33,"unit":"MHz","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2399.99,"unit":"MHz","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBWV","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-7844-r25341","location":"Intel/core i7/i7-660ue · revision 25341 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660ue&oldid=25341","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ac4413e3a033f9f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7844-r25341","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-6ac4413e3a033f9f"},{"id":"cw-6ad88a03fb41f95e","name":"Loihi","kind":"sku","entityType":"product-model","subtype":"sku","company":"Intel","year":2018,"process":"14 nm","aliases":["Intel loihi"],"fields":[{"key":"Model name","value":"Loihi","unit":"","sourceId":"chipswiki-592-r1384","location":"Intel/loihi · revision 1384 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-01. Not an independent measurement.","entityId":"cw-6ad88a03fb41f95e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi&oldid=1384","sourceDate":"2021-10-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-592-r1384","location":"Intel/loihi · revision 1384 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-01. Not an independent measurement.","entityId":"cw-6ad88a03fb41f95e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi&oldid=1384","sourceDate":"2021-10-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-592-r1384","location":"Intel/loihi · revision 1384 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-01. Not an independent measurement.","entityId":"cw-6ad88a03fb41f95e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi&oldid=1384","sourceDate":"2021-10-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Artificial Intelligence","unit":"","sourceId":"chipswiki-592-r1384","location":"Intel/loihi · revision 1384 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-01. Not an independent measurement.","entityId":"cw-6ad88a03fb41f95e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi&oldid=1384","sourceDate":"2021-10-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 25, 2017","unit":"","sourceId":"chipswiki-592-r1384","location":"Intel/loihi · revision 1384 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-01. Not an independent measurement.","entityId":"cw-6ad88a03fb41f95e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi&oldid=1384","sourceDate":"2021-10-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2018","unit":"","sourceId":"chipswiki-592-r1384","location":"Intel/loihi · revision 1384 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-01. Not an independent measurement.","entityId":"cw-6ad88a03fb41f95e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi&oldid=1384","sourceDate":"2021-10-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-592-r1384","location":"Intel/loihi · revision 1384 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-01. Not an independent measurement.","entityId":"cw-6ad88a03fb41f95e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi&oldid=1384","sourceDate":"2021-10-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2070000000,"unit":"","sourceId":"chipswiki-592-r1384","location":"Intel/loihi · revision 1384 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-01. Not an independent measurement.","entityId":"cw-6ad88a03fb41f95e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi&oldid=1384","sourceDate":"2021-10-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-592-r1384","location":"Intel/loihi · revision 1384 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-01. Not an independent measurement.","entityId":"cw-6ad88a03fb41f95e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi&oldid=1384","sourceDate":"2021-10-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":60,"unit":"mm²","sourceId":"chipswiki-592-r1384","location":"Intel/loihi · revision 1384 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-01. Not an independent measurement.","entityId":"cw-6ad88a03fb41f95e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi&oldid=1384","sourceDate":"2021-10-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":16384,"unit":"","sourceId":"chipswiki-592-r1384","location":"Intel/loihi · revision 1384 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-01. Not an independent measurement.","entityId":"cw-6ad88a03fb41f95e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi&oldid=1384","sourceDate":"2021-10-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-592-r1384"],"url":"https://museum.vlsi.kr/objects/cw-6ad88a03fb41f95e"},{"id":"cw-6affc492ff41dddc","name":"Atom Z520","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z500","year":2008,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z520"],"fields":[{"key":"Model name","value":"Atom Z520","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z520","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AC80566UE014DW","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLB2H","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z500","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1333.33,"unit":"MHz","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"533.33 MT/s","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Menlow","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Poulsbo","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":28,"unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":24.18,"unit":"mm²","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2,"unit":"W","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8066-r25702","location":"Intel/atom/z520 · revision 25702 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-441","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":441,"unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":14,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6affc492ff41dddc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8066-r25702","chipswiki-31513-r92656"],"url":"https://museum.vlsi.kr/objects/cw-6affc492ff41dddc"},{"id":"cw-6b0bd01166124d94","name":"Alchemy Au1550-400MBD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2004,"architecture":"Au1","aliases":["Alchemy au1550-400mbd"],"fields":[{"key":"Model name","value":"Alchemy Au1550-400MBD","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1550-400MBD","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1550-400MBDAA","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2004","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AA","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. 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Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-166","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.600 GB/s","unit":"","sourceId":"chipswiki-462-r943","location":"Alchemy/au1550-400mbd · revision 943 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-6b0bd01166124d94","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-462-r943"],"url":"https://museum.vlsi.kr/objects/cw-6b0bd01166124d94"},{"id":"cw-6b2a8232a7a364d2","name":"Ice Lake (client)","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2019,"process":"10 nm","aliases":["Intel microarchitectures ice lake (client)"],"fields":[{"key":"Architecture name","value":"Ice Lake (client)","unit":"","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"May 27, 2019","unit":"","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"5-way","unit":"","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake Y","unit":"","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake U","unit":"","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-06-20. Not an independent measurement.","entityId":"cw-6b2a8232a7a364d2","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fice%20lake%20(client)&oldid=1642","sourceDate":"2021-06-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cannon Lake","unit":"","sourceId":"chipswiki-673-r1642","location":"Intel/microarchitectures/ice lake (client) · revision 1642 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-20. 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Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5975WX","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000445","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 8, 2022","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Threadripper","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5900,"unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3600,"unit":"MHz","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4500,"unit":"MHz","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"WRX80","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chagall","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":280,"unit":"W","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32 × 512 KiB","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 32 MiB","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"204.8 GB/s","unit":"","sourceId":"chipswiki-392-r838","location":"Amd/ryzen threadripper/pro 5975wx · revision 838 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OLGA","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":4094,"unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.87,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":75.4,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":58.5,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":6.26,"unit":"mm","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"sWRX8","unit":"","sourceId":"chipswiki-31095-r91554","location":"Template:Packages/amd/socket swrx8 · revision 91554 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-14. Not an independent measurement.","entityId":"cw-6b4d8bbda1ad2d4f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20swrx8&oldid=91554","sourceDate":"2022-04-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-392-r838","chipswiki-31095-r91554"],"url":"https://museum.vlsi.kr/objects/cw-6b4d8bbda1ad2d4f"},{"id":"cw-6b6f69cb613697df","name":"Core i5-1035G4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-10000","year":2019,"architecture":"Ice Lake (Client)","process":"10 nm","aliases":["Intel core i5 i5-1035g4"],"fields":[{"key":"Model name","value":"Core i5-1035G4","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-1035G4","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 1, 2019","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-10000","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ice Lake (Client)","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Ice Lake","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ice Lake U","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x48 KiB","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics","unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-1257-r4084","location":"Intel/core i5/i5-1035g4 · revision 4084 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-6b6f69cb613697df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1035g4&oldid=4084","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1257-r4084"],"url":"https://museum.vlsi.kr/objects/cw-6b6f69cb613697df"},{"id":"cw-6b71c5ad2f21b0e2","name":"Tukwila","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2010,"process":"65 nm","aliases":["Intel microarchitectures tukwila"],"fields":[{"key":"Architecture name","value":"Tukwila","unit":"","sourceId":"chipswiki-8764-r27226","location":"Intel/microarchitectures/tukwila · revision 27226 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-6b71c5ad2f21b0e2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftukwila&oldid=27226","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8764-r27226","location":"Intel/microarchitectures/tukwila · revision 27226 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-6b71c5ad2f21b0e2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftukwila&oldid=27226","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8764-r27226","location":"Intel/microarchitectures/tukwila · revision 27226 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-6b71c5ad2f21b0e2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftukwila&oldid=27226","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"February 8, 2010","unit":"","sourceId":"chipswiki-8764-r27226","location":"Intel/microarchitectures/tukwila · revision 27226 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-6b71c5ad2f21b0e2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftukwila&oldid=27226","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-8764-r27226","location":"Intel/microarchitectures/tukwila · revision 27226 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-6b71c5ad2f21b0e2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftukwila&oldid=27226","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-8764-r27226","location":"Intel/microarchitectures/tukwila · revision 27226 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-6b71c5ad2f21b0e2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftukwila&oldid=27226","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"IA-64","unit":"","sourceId":"chipswiki-8764-r27226","location":"Intel/microarchitectures/tukwila · revision 27226 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-6b71c5ad2f21b0e2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftukwila&oldid=27226","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Montvale","unit":"","sourceId":"chipswiki-8764-r27226","location":"Intel/microarchitectures/tukwila · revision 27226 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-6b71c5ad2f21b0e2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftukwila&oldid=27226","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Poulson","unit":"","sourceId":"chipswiki-8764-r27226","location":"Intel/microarchitectures/tukwila · revision 27226 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-6b71c5ad2f21b0e2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftukwila&oldid=27226","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Dimona","unit":"","sourceId":"chipswiki-8764-r27226","location":"Intel/microarchitectures/tukwila · revision 27226 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-6b71c5ad2f21b0e2","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftukwila&oldid=27226","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8764-r27226"],"url":"https://museum.vlsi.kr/objects/cw-6b71c5ad2f21b0e2"},{"id":"cw-6b8bce5cf6280bf1","name":"Snapdragon 429","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","series":"400","year":2018,"architecture":"Cortex-A53","process":"12 nm","aliases":["Qualcomm snapdragon 400 429"],"fields":[{"key":"Model name","value":"Snapdragon 429","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM429","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 26, 2018","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 26, 2018","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 400","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":400,"unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1950,"unit":"MHz","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARM","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 504","unit":"","sourceId":"chipswiki-902-r2390","location":"Qualcomm/snapdragon 400/429 · revision 2390 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-25. Not an independent measurement.","entityId":"cw-6b8bce5cf6280bf1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F429&oldid=2390","sourceDate":"2020-11-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-902-r2390"],"url":"https://museum.vlsi.kr/objects/cw-6b8bce5cf6280bf1"},{"id":"cw-6bad3a2c7a9a4e9d","name":"z13","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"IBM","year":2015,"process":"22 nm","aliases":["Ibm microarchitectures z13"],"fields":[{"key":"Architecture name","value":"z13","unit":"","sourceId":"chipswiki-13213-r38676","location":"Ibm/microarchitectures/z13 · revision 38676 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-6bad3a2c7a9a4e9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz13&oldid=38676","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-13213-r38676","location":"Ibm/microarchitectures/z13 · revision 38676 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-6bad3a2c7a9a4e9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz13&oldid=38676","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-13213-r38676","location":"Ibm/microarchitectures/z13 · revision 38676 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-6bad3a2c7a9a4e9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz13&oldid=38676","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"January 14, 2015","unit":"","sourceId":"chipswiki-13213-r38676","location":"Ibm/microarchitectures/z13 · revision 38676 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-6bad3a2c7a9a4e9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz13&oldid=38676","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-13213-r38676","location":"Ibm/microarchitectures/z13 · revision 38676 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-6bad3a2c7a9a4e9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz13&oldid=38676","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-13213-r38676","location":"Ibm/microarchitectures/z13 · revision 38676 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-6bad3a2c7a9a4e9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz13&oldid=38676","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Pipelined","unit":"","sourceId":"chipswiki-13213-r38676","location":"Ibm/microarchitectures/z13 · revision 38676 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-6bad3a2c7a9a4e9d","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz13&oldid=38676","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"z/Architecture","unit":"","sourceId":"chipswiki-13213-r38676","location":"Ibm/microarchitectures/z13 · revision 38676 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-6bad3a2c7a9a4e9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz13&oldid=38676","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"z12","unit":"","sourceId":"chipswiki-13213-r38676","location":"Ibm/microarchitectures/z13 · revision 38676 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-6bad3a2c7a9a4e9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz13&oldid=38676","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"z14","unit":"","sourceId":"chipswiki-13213-r38676","location":"Ibm/microarchitectures/z13 · revision 38676 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-07-20. Not an independent measurement.","entityId":"cw-6bad3a2c7a9a4e9d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fz13&oldid=38676","sourceDate":"2017-07-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-13213-r38676"],"url":"https://museum.vlsi.kr/objects/cw-6bad3a2c7a9a4e9d"},{"id":"cw-6bbfb0b9f32545e1","name":"Pentium N4200","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N Series","year":2016,"architecture":"Goldmont","process":"14 nm","aliases":["Intel pentium (2009) n4200"],"fields":[{"key":"Model name","value":"Pentium","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N4200","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066802979703","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066802979703","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N Series","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2Y9","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2Z5","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Apollo Lake","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-1296","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1296","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-7780-r25212","location":"Intel/pentium (2009)/n4200 · revision 25212 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bbfb0b9f32545e1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn4200&oldid=25212","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7780-r25212"],"url":"https://museum.vlsi.kr/objects/cw-6bbfb0b9f32545e1"},{"id":"cw-6bc3f8f2deefd5e2","name":"Core i5-460M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-400","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i5 i5-460m"],"fields":[{"key":"Model name","value":"Intel Core i5-460M","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-460M","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004116AI","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004116AI","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-400","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2533.33,"unit":"MHz","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2799.99,"unit":"MHz","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBZW","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC22","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7940-r25487","location":"Intel/core i5/i5-460m · revision 25487 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-460m&oldid=25487","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"rPGA-988A","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"rPGA","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":988,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 1","value":1,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":36,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":2.12,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket — package module 1","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6bc3f8f2deefd5e2","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. 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Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":100,"unit":"W","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":10,"unit":"MiB","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x1","unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":13.75,"unit":"MiB","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x1.375 MiB","unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1170-r3648","location":"Intel/xeon silver/4210r · revision 3648 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-04. Not an independent measurement.","entityId":"cw-6bf74ccd03628554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4210r&oldid=3648","sourceDate":"2020-05-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1170-r3648"],"url":"https://museum.vlsi.kr/objects/cw-6bf74ccd03628554"},{"id":"cw-6bfb18ba02075d8e","name":"K6-2/400ACK-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-400ack-66"],"fields":[{"key":"Model name","value":"K6-2/400ACK-66","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/400ACK-66","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8357-r26052","location":"Amd/k6-2/k6-2-400ack-66 · revision 26052 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6bfb18ba02075d8e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400ack-66&oldid=26052","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8357-r26052"],"url":"https://museum.vlsi.kr/objects/cw-6bfb18ba02075d8e"},{"id":"cw-6c96edb7919aac5b","name":"Pentium B970","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"900","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel pentium (2009) b970"],"fields":[{"key":"Model name","value":"Pentium B970","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B970","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700998002","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0J2","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 16, 2012","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 16, 2012","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7790-r25226","location":"Intel/pentium (2009)/b970 · revision 25226 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fb970&oldid=25226","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6c96edb7919aac5b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7790-r25226","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-6c96edb7919aac5b"},{"id":"cw-6d11e72447766a02","name":"Core i7-7820HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-7800","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-7820hq"],"fields":[{"key":"Model name","value":"Core i7-7820HQ","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-7820HQ","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR32N","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-7800","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake H","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-6414-r20013","location":"Intel/core i7/i7-7820hq · revision 20013 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-6d11e72447766a02","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6414-r20013","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-6d11e72447766a02"},{"id":"cw-6d1e8c89491a3656","name":"Alchemy Au1210-333MGD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"RMI","year":2007,"architecture":"Au1","aliases":["Alchemy au1210-333mgd"],"fields":[{"key":"Model name","value":"Alchemy Au1210-333MGD","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"RMI","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1210-333MGD","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1210-333MGD","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 9, 2007","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 5, 2007","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1,"unit":"V","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"920 mW","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.332 GB/s","unit":"","sourceId":"chipswiki-449-r930","location":"Alchemy/au1210-333mgd · revision 930 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-6d1e8c89491a3656","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-333mgd&oldid=930","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-449-r930"],"url":"https://museum.vlsi.kr/objects/cw-6d1e8c89491a3656"},{"id":"cw-6d2651a0b0580e6f","name":"EPYC 7313","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7313"],"fields":[{"key":"Model name","value":"EPYC 7313","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7313,"unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000329","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000329WOF","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16 × 32 KiB","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16 × 512 KiB","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 32 MiB","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-729-r1750","location":"Amd/epyc/7313 · revision 1750 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-25. Not an independent measurement.","entityId":"cw-6d2651a0b0580e6f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","sourceDate":"2021-05-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-729-r1750"],"url":"https://museum.vlsi.kr/objects/cw-6d2651a0b0580e6f"},{"id":"cw-6d2a017f63dd3a1e","name":"AMD-K6-IIIE+/500ACR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-iii+ amd-k6-iiie+-500acr"],"fields":[{"key":"Model name","value":"AMD-K6-IIIE+/500ACR","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-IIIE+/500ACR","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-IIIE+/500ACR","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III+","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III+ Embedded","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":499.99,"unit":"MHz","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":3,"unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21400000,"unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":14.5,"unit":"W","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8313-r26003","location":"Amd/k6-iii+/amd-k6-iiie+-500acr · revision 26003 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d2a017f63dd3a1e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500acr&oldid=26003","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8313-r26003"],"url":"https://museum.vlsi.kr/objects/cw-6d2a017f63dd3a1e"},{"id":"cw-6d34269f10c160d8","name":"CN3110-500 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-500bg868-scp"],"fields":[{"key":"Model name","value":"Cavium CN3110-500 SCP","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-500 SCP","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-500BG868-SCP","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6d34269f10c160d8","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-scp&oldid=25918","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8258-r25918","location":"Cavium/octeon/cn3110-500bg868-scp · revision 25918 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6820HQ","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066202194731","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2FU","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 27, 2015","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-3972-r12659","location":"Intel/core i7/i7-6820hq · revision 12659 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6d5b6f3c502b43fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3972-r12659","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-6d5b6f3c502b43fb"},{"id":"cw-6d68f91b5cc6f4ca","name":"Celerity","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"University of Michigan","year":null,"process":"16 nm","aliases":["Umich microarchitectures celerity"],"fields":[{"key":"Architecture name","value":"Celerity","unit":"","sourceId":"chipswiki-1378-r4613","location":"Umich/microarchitectures/celerity · revision 4613 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-21. 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Not an independent measurement.","entityId":"cw-6d68f91b5cc6f4ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Umich%2Fmicroarchitectures%2Fcelerity&oldid=4613","sourceDate":"2020-01-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1378-r4613","location":"Umich/microarchitectures/celerity · revision 4613 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-21. 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Not an independent measurement.","entityId":"cw-6d68f91b5cc6f4ca","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Umich%2Fmicroarchitectures%2Fcelerity&oldid=4613","sourceDate":"2020-01-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1378-r4613"],"url":"https://museum.vlsi.kr/objects/cw-6d68f91b5cc6f4ca"},{"id":"cw-6da69413eecc86e2","name":"Xeon Gold 6138","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6138"],"fields":[{"key":"Model name","value":"Xeon Gold 6138","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6138,"unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806736138","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303406100","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":27.5,"unit":"MiB","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x1.375 MiB","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-6da69413eecc86e2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1506-r4958","location":"Intel/xeon gold/6138 · revision 4958 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i9","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i9-7900","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake X","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":14,"unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":28,"unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":102,"unit":"°C","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":896,"unit":"KiB","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":448,"unit":"KiB","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":448,"unit":"KiB","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"14x32 KiB","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":14,"unit":"MiB","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"14x1 MiB","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":19.25,"unit":"MiB","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"14x1.375 MiB","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-1086-r3189","location":"Intel/core i9/i9-7940x · revision 3189 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-06-10. Not an independent measurement.","entityId":"cw-6db57907f4f20ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-7940x&oldid=3189","sourceDate":"2020-06-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1086-r3189"],"url":"https://museum.vlsi.kr/objects/cw-6db57907f4f20ffe"},{"id":"cw-6db8a7a5c0746314","name":"Core i7-6498DU","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6498du"],"fields":[{"key":"Model name","value":"Core i7-6498DU","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6498DU","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066201930413","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2NS","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-3957-r12644","location":"Intel/core i7/i7-6498du · revision 12644 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6498du&oldid=12644","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-6db8a7a5c0746314","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3957-r12644","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-6db8a7a5c0746314"},{"id":"cw-6db942519d751c8f","name":"Westmere","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2010,"process":"32 nm","aliases":["Intel microarchitectures westmere (client)"],"fields":[{"key":"Architecture name","value":"Westmere","unit":"","sourceId":"chipswiki-6987-r21829","location":"Intel/microarchitectures/westmere (client) · revision 21829 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-6db942519d751c8f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwestmere%20(client)&oldid=21829","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6987-r21829","location":"Intel/microarchitectures/westmere (client) · revision 21829 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-6db942519d751c8f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwestmere%20(client)&oldid=21829","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6987-r21829","location":"Intel/microarchitectures/westmere (client) · revision 21829 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-6db942519d751c8f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwestmere%20(client)&oldid=21829","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"January, 2010","unit":"","sourceId":"chipswiki-6987-r21829","location":"Intel/microarchitectures/westmere (client) · revision 21829 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-6db942519d751c8f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwestmere%20(client)&oldid=21829","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6987-r21829","location":"Intel/microarchitectures/westmere (client) · revision 21829 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-6db942519d751c8f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwestmere%20(client)&oldid=21829","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6987-r21829","location":"Intel/microarchitectures/westmere (client) · revision 21829 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. Not an independent measurement.","entityId":"cw-6db942519d751c8f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwestmere%20(client)&oldid=21829","sourceDate":"2018-03-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Nehalem","unit":"","sourceId":"chipswiki-6987-r21829","location":"Intel/microarchitectures/westmere (client) · revision 21829 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-10. 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Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":837,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701080000","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701080001","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701080002","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR07K","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0EH","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0Q0","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-6940-r21627","location":"Intel/celeron/837 · revision 21627 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6dbed62d178503a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-6de4ed83d5197bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-4826&oldid=4005","sourceDate":"2020-03-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1247-r4005","location":"Hisilicon/kunpeng/920-4826 · revision 4005 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-05. 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Not an independent measurement.","entityId":"cw-6de4ed83d5197bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-4826&oldid=4005","sourceDate":"2020-03-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1247-r4005","location":"Hisilicon/kunpeng/920-4826 · revision 4005 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-05. 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Not an independent measurement.","entityId":"cw-6de4ed83d5197bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-4826&oldid=4005","sourceDate":"2020-03-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-1247-r4005","location":"Hisilicon/kunpeng/920-4826 · revision 4005 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-05. 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Not an independent measurement.","entityId":"cw-6de4ed83d5197bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-4826&oldid=4005","sourceDate":"2020-03-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"48x512 KiB","unit":"","sourceId":"chipswiki-1247-r4005","location":"Hisilicon/kunpeng/920-4826 · revision 4005 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-05. Not an independent measurement.","entityId":"cw-6de4ed83d5197bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-4826&oldid=4005","sourceDate":"2020-03-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":48,"unit":"MiB","sourceId":"chipswiki-1247-r4005","location":"Hisilicon/kunpeng/920-4826 · revision 4005 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-05. Not an independent measurement.","entityId":"cw-6de4ed83d5197bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-4826&oldid=4005","sourceDate":"2020-03-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"48x1 MiB","unit":"","sourceId":"chipswiki-1247-r4005","location":"Hisilicon/kunpeng/920-4826 · revision 4005 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-05. Not an independent measurement.","entityId":"cw-6de4ed83d5197bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-4826&oldid=4005","sourceDate":"2020-03-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1247-r4005","location":"Hisilicon/kunpeng/920-4826 · revision 4005 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-05. Not an independent measurement.","entityId":"cw-6de4ed83d5197bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-4826&oldid=4005","sourceDate":"2020-03-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1247-r4005","location":"Hisilicon/kunpeng/920-4826 · revision 4005 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-05. Not an independent measurement.","entityId":"cw-6de4ed83d5197bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-4826&oldid=4005","sourceDate":"2020-03-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1247-r4005","location":"Hisilicon/kunpeng/920-4826 · revision 4005 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-05. Not an independent measurement.","entityId":"cw-6de4ed83d5197bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-4826&oldid=4005","sourceDate":"2020-03-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-1247-r4005","location":"Hisilicon/kunpeng/920-4826 · revision 4005 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-05. Not an independent measurement.","entityId":"cw-6de4ed83d5197bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-4826&oldid=4005","sourceDate":"2020-03-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-1247-r4005","location":"Hisilicon/kunpeng/920-4826 · revision 4005 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-05. Not an independent measurement.","entityId":"cw-6de4ed83d5197bf2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkunpeng%2F920-4826&oldid=4005","sourceDate":"2020-03-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1247-r4005"],"url":"https://museum.vlsi.kr/objects/cw-6de4ed83d5197bf2"},{"id":"cw-6e1021d38c5f4701","name":"K6-2E/333AMZ-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-333amz-66"],"fields":[{"key":"Model name","value":"K6-2E/333AMZ-66","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/333AMZ-66","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/333AMZ-66","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 1999","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 1999","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.33,"unit":"MHz","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.9,"unit":"V","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8320-r26015","location":"Amd/k6-2/k6-2e-333amz-66 · revision 26015 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e1021d38c5f4701","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz-66&oldid=26015","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8320-r26015"],"url":"https://museum.vlsi.kr/objects/cw-6e1021d38c5f4701"},{"id":"cw-6e17fff1c92d61c7","name":"Pentium Gold G5420","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel pentium gold g5420"],"fields":[{"key":"Model name","value":"Pentium Gold G5420","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G5420","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403360113","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3XA","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium Gold","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54,"unit":"W","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 610","unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-2851-r9567","location":"Intel/pentium gold/g5420 · revision 9567 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-6e17fff1c92d61c7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5420&oldid=9567","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2851-r9567"],"url":"https://museum.vlsi.kr/objects/cw-6e17fff1c92d61c7"},{"id":"cw-6e23fe1db1f8a513","name":"AMD-X5-133SDY","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":1996,"architecture":"80486","process":"350 nm","aliases":["Amd am5x86 amd-x5-133sdy"],"fields":[{"key":"Model name","value":"AMD-X5-133SDY","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-X5-133SDY","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-X5-133SDY","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1996,"unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am5x86","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":133,"unit":"MHz","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5x","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1600000,"unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":43,"unit":"mm²","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.45,"unit":"V","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SQFP-208","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SQFP","unit":"","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":16,"unit":"KiB","sourceId":"chipswiki-8527-r26722","location":"Amd/am5x86/amd-x5-133sdy · revision 26722 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e23fe1db1f8a513","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8527-r26722"],"url":"https://museum.vlsi.kr/objects/cw-6e23fe1db1f8a513"},{"id":"cw-6e2ad4f46653d104","name":"Xeon Gold 6150","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6150"],"fields":[{"key":"Model name","value":"Xeon Gold 6150","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6150,"unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303328000","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR37K","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1496-r4948","location":"Intel/xeon gold/6150 · revision 4948 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-6e2ad4f46653d104","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1496-r4948"],"url":"https://museum.vlsi.kr/objects/cw-6e2ad4f46653d104"},{"id":"cw-6e69117dfc29c818","name":"Core i7-620LM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-600","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7 i7-620lm"],"fields":[{"key":"Model name","value":"Intel Core i7-620LM","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-620LM","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617003879AD","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1999.99,"unit":"MHz","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2799.99,"unit":"MHz","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBML","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBSU","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C2","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e69117dfc29c818","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620lm&oldid=25354","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7854-r25354","location":"Intel/core i7/i7-620lm · revision 25354 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6e6b2ec03bf17f2b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgolden%20cove&oldid=438","sourceDate":"2022-09-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"November 4, 2021","unit":"","sourceId":"chipswiki-214-r438","location":"Intel/microarchitectures/golden cove · revision 438 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-01. Not an independent measurement.","entityId":"cw-6e6b2ec03bf17f2b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgolden%20cove&oldid=438","sourceDate":"2022-09-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-214-r438","location":"Intel/microarchitectures/golden cove · revision 438 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-01. Not an independent measurement.","entityId":"cw-6e6b2ec03bf17f2b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgolden%20cove&oldid=438","sourceDate":"2022-09-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-214-r438","location":"Intel/microarchitectures/golden cove · revision 438 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-01. Not an independent measurement.","entityId":"cw-6e6b2ec03bf17f2b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgolden%20cove&oldid=438","sourceDate":"2022-09-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Alder Lake, Sapphire Rapids","unit":"","sourceId":"chipswiki-214-r438","location":"Intel/microarchitectures/golden cove · revision 438 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-01. Not an independent measurement.","entityId":"cw-6e6b2ec03bf17f2b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgolden%20cove&oldid=438","sourceDate":"2022-09-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Willow Cove","unit":"","sourceId":"chipswiki-214-r438","location":"Intel/microarchitectures/golden cove · revision 438 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-01. Not an independent measurement.","entityId":"cw-6e6b2ec03bf17f2b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgolden%20cove&oldid=438","sourceDate":"2022-09-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cypress Cove","unit":"","sourceId":"chipswiki-214-r438","location":"Intel/microarchitectures/golden cove · revision 438 · {{microarchitecture}} / predecessor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"predecessor 2","note":"Source-reported parameter; source revision 2022-09-01. Not an independent measurement.","entityId":"cw-6e6b2ec03bf17f2b","scope":"predecessor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgolden%20cove&oldid=438","sourceDate":"2022-09-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Ocean Cove","unit":"","sourceId":"chipswiki-214-r438","location":"Intel/microarchitectures/golden cove · revision 438 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-01. Not an independent measurement.","entityId":"cw-6e6b2ec03bf17f2b","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgolden%20cove&oldid=438","sourceDate":"2022-09-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-214-r438"],"url":"https://museum.vlsi.kr/objects/cw-6e6b2ec03bf17f2b"},{"id":"cw-6e714b7461fcb560","name":"Duron 1100 (Morgan)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhd1100amt1b"],"fields":[{"key":"Model name","value":"Duron 1100","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 1100","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHD1100AMT1B","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 1, 2001","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":50.3,"unit":"W","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8427-r26135","location":"Amd/duron/dhd1100amt1b · revision 26135 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e714b7461fcb560","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8427-r26135"],"url":"https://museum.vlsi.kr/objects/cw-6e714b7461fcb560"},{"id":"cw-6e7d369f42861c32","name":"Exynos Auto V9","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","year":2018,"architecture":"Cortex-A76","process":"8 nm","aliases":["Samsung exynos auto v9"],"fields":[{"key":"Model name","value":"Exynos Auto V9","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"V9","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2018","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2018","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos Auto","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.1,"unit":"GHz","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A76","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A76","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":8,"unit":"nm","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x64 KiB","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x64 KiB","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":"2-4? 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Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":"? 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Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-????","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR5-????","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G76","unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":6,"unit":"","sourceId":"chipswiki-1110-r3300","location":"Samsung/exynos auto/v9 · revision 3300 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-30. Not an independent measurement.","entityId":"cw-6e7d369f42861c32","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%20auto%2Fv9&oldid=3300","sourceDate":"2020-05-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1110-r3300"],"url":"https://museum.vlsi.kr/objects/cw-6e7d369f42861c32"},{"id":"cw-6e82640cbaa6d52a","name":"AMD-K6-III/400AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III Desktop","year":1999,"architecture":"K6-III","process":"0.25 µm","aliases":["Amd k6-iii amd-k6-iii-400afr"],"fields":[{"key":"Model name","value":"AMD-K6-III/400AFR","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III/400AFR","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III/400AFR","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 26, 1999","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 26, 1999","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III Desktop","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sharptooth","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":9,"unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21300000,"unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":118,"unit":"mm²","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8303-r25992","location":"Amd/k6-iii/amd-k6-iii-400afr · revision 25992 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e82640cbaa6d52a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2Famd-k6-iii-400afr&oldid=25992","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8303-r25992"],"url":"https://museum.vlsi.kr/objects/cw-6e82640cbaa6d52a"},{"id":"cw-6e83328397433e2b","name":"CN5734-600 SSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5734-600bg1217-ssp"],"fields":[{"key":"Model name","value":"Cavium CN5734-600 SSP","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5734-600 SSP","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5734-600BG1217-SSP","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":288,"unit":"KiB","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x16 KiB","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8190-r25849","location":"Cavium/octeon plus/cn5734-600bg1217-ssp · revision 25849 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6e83328397433e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8190-r25849","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-6e83328397433e2b"},{"id":"cw-6ead2048a39f8aa0","name":"Core i5-6267U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6267u"],"fields":[{"key":"Model name","value":"Core i5-6267U","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6267U","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066202499002","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2JK","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K1","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Graphics 550","unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7928-r25468","location":"Intel/core i5/i5-6267u · revision 25468 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6267u&oldid=25468","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6ead2048a39f8aa0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 2400+","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMSN2400DKT3C","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 10, 2002","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 10, 2002","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Thoroughbred","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37200000,"unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":85,"unit":"mm²","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.65,"unit":"V","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":60,"unit":"W","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8449-r26642","location":"Amd/athlon mp/amsn2400dkt3c · revision 26642 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famsn2400dkt3c&oldid=26642","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f078390b7cb42b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8449-r26642","chipswiki-31459-r92404"],"url":"https://museum.vlsi.kr/objects/cw-6f078390b7cb42b4"},{"id":"cw-6f32a435025ebd0f","name":"CN3005-500 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3000","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3005-500bg350-cp"],"fields":[{"key":"Model name","value":"Cavium CN3005-500 CP","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3005-500 CP","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3005-500BG350-CP","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3000","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-350","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":24,"unit":"KiB","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1,017 MiB/s","unit":"","sourceId":"chipswiki-8277-r25937","location":"Cavium/octeon/cn3005-500bg350-cp · revision 25937 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f32a435025ebd0f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3005-500bg350-cp&oldid=25937","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8277-r25937"],"url":"https://museum.vlsi.kr/objects/cw-6f32a435025ebd0f"},{"id":"cw-6f5adfe3214848d8","name":"FastMATH-LP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intrinsity","year":2003,"architecture":"FashMATH","process":"130 nm","aliases":["Intrinsity fastmath fastmath-lp"],"fields":[{"key":"Model name","value":"FastMATH-LP","unit":"","sourceId":"chipswiki-7687-r24982","location":"Intrinsity/fastmath/fastmath-lp · revision 24982 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f5adfe3214848d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-lp&oldid=24982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intrinsity","unit":"","sourceId":"chipswiki-7687-r24982","location":"Intrinsity/fastmath/fastmath-lp · revision 24982 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f5adfe3214848d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-lp&oldid=24982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7687-r24982","location":"Intrinsity/fastmath/fastmath-lp · revision 24982 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f5adfe3214848d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-lp&oldid=24982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"FastMATH-LP","unit":"","sourceId":"chipswiki-7687-r24982","location":"Intrinsity/fastmath/fastmath-lp · revision 24982 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f5adfe3214848d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-lp&oldid=24982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7687-r24982","location":"Intrinsity/fastmath/fastmath-lp · revision 24982 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f5adfe3214848d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-lp&oldid=24982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2002,"unit":"","sourceId":"chipswiki-7687-r24982","location":"Intrinsity/fastmath/fastmath-lp · revision 24982 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6f5adfe3214848d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-lp&oldid=24982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2003,"unit":"","sourceId":"chipswiki-7687-r24982","location":"Intrinsity/fastmath/fastmath-lp · revision 24982 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6f5adfe3214848d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-lp&oldid=24982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"GiB","sourceId":"chipswiki-7687-r24982","location":"Intrinsity/fastmath/fastmath-lp · revision 24982 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6f5adfe3214848d8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-lp&oldid=24982","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-670","unit":"","sourceId":"chipswiki-7687-r24982","location":"Intrinsity/fastmath/fastmath-lp · revision 24982 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B720","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701084101","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0EA","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 2012","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2012","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":700,"unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x1.5 MiB","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-6930-r21617","location":"Intel/celeron/b720 · revision 21617 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-6f677dbfff54bddb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-05-08. 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Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. 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Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. 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Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":165,"unit":"W","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.625,"unit":"MiB","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":832,"unit":"KiB","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"26x32 KiB","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":832,"unit":"KiB","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"26x32 KiB","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":26,"unit":"MiB","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"26x1 MiB","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-2557-r8820","location":"Intel/xeon platinum/8170f · revision 8820 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-6f69682410c31eb2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8170f&oldid=8820","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2557-r8820"],"url":"https://museum.vlsi.kr/objects/cw-6f69682410c31eb2"},{"id":"cw-6fa522c89c9d0afc","name":"Ryzen 5 3500U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 5 3500u"],"fields":[{"key":"Model name","value":"Ryzen 5 3500U","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3500U","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM3500C4T4MFG","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","alternatives":[{"value":"32 GiB","sourceId":"chipswiki-595-r1390","reason":"Amd/ryzen 5/3500u · revision 1390 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-595-r1390","location":"Amd/ryzen 5/3500u · revision 1390 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-30. Not an independent measurement.","entityId":"cw-6fa522c89c9d0afc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","sourceDate":"2021-09-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-595-r1390"],"url":"https://museum.vlsi.kr/objects/cw-6fa522c89c9d0afc"},{"id":"cw-6fbea897d416c792","name":"MR80186-3","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 mr80186-3"],"fields":[{"key":"Model name","value":"MR80186-3","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MR80186-3","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MR80186-3","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"2 MT/s","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8634-r26833","location":"Amd/am186/mr80186-3 · revision 26833 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fbea897d416c792","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8634-r26833"],"url":"https://museum.vlsi.kr/objects/cw-6fbea897d416c792"},{"id":"cw-6fc0e13b5719dc54","name":"CN5745-1000 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5745-1000bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5745-1000 SP","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5745-1000 SP","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5745-1000BG1217-SP","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":160,"unit":"KiB","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x16 KiB","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8177-r25836","location":"Cavium/octeon plus/cn5745-1000bg1217-sp · revision 25836 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-sp&oldid=25836","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-6fc0e13b5719dc54","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8177-r25836","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-6fc0e13b5719dc54"},{"id":"cw-6fc86a15946ddf0b","name":"Xeon D-1653N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1600","year":2019,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1653n"],"fields":[{"key":"Model name","value":"Xeon D-1653N","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1653N","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8068204235902","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRG04","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1600","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Hewitt Lake","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.5 MiB","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-3680-r11008","location":"Intel/xeon d/d-1653n · revision 11008 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-6fc86a15946ddf0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1653n&oldid=11008","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3680-r11008"],"url":"https://museum.vlsi.kr/objects/cw-6fc86a15946ddf0b"},{"id":"cw-6fe735fa07beb37f","name":"EPYC 7262","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7262"],"fields":[{"key":"Model name","value":"EPYC 7262","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000041","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000041WOF","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x16 MiB","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-854-r2234","location":"Amd/epyc/7262 · revision 2234 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-6fe735fa07beb37f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-854-r2234"],"url":"https://museum.vlsi.kr/objects/cw-6fe735fa07beb37f"},{"id":"cw-7008bc0fa6bad968","name":"Xeon W-3245M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-3200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon w w-3245m"],"fields":[{"key":"Model name","value":"Xeon W-3245M","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-3245M","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504248501","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFFH","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-3200","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1705-r5938","location":"Intel/xeon w/w-3245m · revision 5938 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-7008bc0fa6bad968","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1705-r5938"],"url":"https://museum.vlsi.kr/objects/cw-7008bc0fa6bad968"},{"id":"cw-70335a87980eef51","name":"Vector Engine Type 10AE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"NEC","series":"Type 10E","year":2020,"architecture":"SX-Aurora","process":"16 nm","aliases":["Nec vector engine type 10ae"],"fields":[{"key":"Model name","value":"VE Type 10AE","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"NEC","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Type 10AE","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 2019","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2020","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Vector Engine","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Type 10E","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1584,"unit":"MHz","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"SX-Aurora","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"SX-Aurora TSUBASA","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":493.68,"unit":"mm²","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":48,"unit":"GiB","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"HBM2-1800","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":6,"unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":48,"unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1,382 GB/s","unit":"","sourceId":"chipswiki-1592-r5326","location":"Nec/vector engine/type 10ae · revision 5326 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-70335a87980eef51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nec%2Fvector%20engine%2Ftype%2010ae&oldid=5326","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1592-r5326"],"url":"https://museum.vlsi.kr/objects/cw-70335a87980eef51"},{"id":"cw-7060a65ebb0a8598","name":"CN3010-400 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3000","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3010-400bg525-cp"],"fields":[{"key":"Model name","value":"Cavium CN3010-400 CP","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3010-400 CP","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3010-400BG525-CP","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3000","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-525","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":24,"unit":"KiB","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7060a65ebb0a8598","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-cp&oldid=25933","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":1.986,"unit":"GiB/s","sourceId":"chipswiki-8273-r25933","location":"Cavium/octeon/cn3010-400bg525-cp · revision 25933 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1585L v5","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500 v5","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"N0","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Pro Graphics P580","unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7751-r25133","location":"Intel/xeon e3/e3-1585l v5 · revision 25133 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585l%20v5&oldid=25133","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70695e7722829609","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7751-r25133","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-70695e7722829609"},{"id":"cw-708ac4b5459b84c2","name":"Pentium Silver J5005","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2017,"architecture":"Goldmont Plus","process":"14 nm","aliases":["Intel pentium silver j5005"],"fields":[{"key":"Model name","value":"Pentium Silver J5005","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J5005","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. 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Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3S3","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 11, 2017","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. 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Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium Silver","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-11-17. 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Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Gemini Lake","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. 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Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 605","unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":18,"unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":250,"unit":"MHz","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-22-r96949","location":"Intel/pentium silver/j5005 · revision 96949 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","sourceDate":"2022-11-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1090","unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1090,"unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-17. Not an independent measurement.","entityId":"cw-708ac4b5459b84c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-22-r96949","chipswiki-31338-r92075"],"url":"https://museum.vlsi.kr/objects/cw-708ac4b5459b84c2"},{"id":"cw-7096b3d25b03393a","name":"Pentium G4500","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel pentium (2009) g4500"],"fields":[{"key":"Model name","value":"Pentium G4500","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4500","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80662G4500","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80662G4500","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201927319","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2HJ","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-7786-r25221","location":"Intel/pentium (2009)/g4500 · revision 25221 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7096b3d25b03393a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4500&oldid=25221","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7786-r25221"],"url":"https://museum.vlsi.kr/objects/cw-7096b3d25b03393a"},{"id":"cw-70af7200be593a92","name":"Godson-2H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Loongson","series":"Godson 2","year":2011,"architecture":"GS464V","process":"65 nm","aliases":["Loongson godson 2 2h"],"fields":[{"key":"Model name","value":"Godson-2H","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Loongson","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"STMicroelectronics","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2H","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 2010","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2011","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Godson 2","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Godson 2","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"HyperTransport 1.03","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"GS464V","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"GS464V","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":152000000,"unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":117,"unit":"mm²","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-741","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-741","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"GC800","unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":4,"unit":"","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":400,"unit":"MHz","sourceId":"chipswiki-7677-r24972","location":"Loongson/godson 2/2h · revision 24972 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-70af7200be593a92","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7677-r24972"],"url":"https://museum.vlsi.kr/objects/cw-70af7200be593a92"},{"id":"cw-70b76d6470b2f366","name":"A10X Fusion","kind":"sku","entityType":"product-model","subtype":"soc","company":"Apple","year":2017,"architecture":"Hurricane","process":"10 nm","aliases":["Apple ax a10x"],"fields":[{"key":"Model name","value":"A10X Fusion","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Apple","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A10X Fusion","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2017","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 13, 2017","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ax","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Hurricane","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Hurricane","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Zephyr","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":96.4,"unit":"mm²","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":3,"unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-889-r2326","location":"Apple/ax/a10x · revision 2326 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-15. Not an independent measurement.","entityId":"cw-70b76d6470b2f366","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","sourceDate":"2020-12-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-889-r2326"],"url":"https://museum.vlsi.kr/objects/cw-70b76d6470b2f366"},{"id":"cw-70e0032bada74852","name":"Core i7-8510Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":2019,"architecture":"Amber Lake","process":"14 nm","aliases":["Intel core i7 i7-8510y"],"fields":[{"key":"Model name","value":"Core i7-8510Y","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8510Y","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702739887","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SREKN","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 4, 2019","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 4, 2019","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Amber Lake","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Amber Lake","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Amber Lake Y","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":7,"unit":"W","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 617","unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-3691-r11027","location":"Intel/core i7/i7-8510y · revision 11027 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-70e0032bada74852","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3691-r11027"],"url":"https://museum.vlsi.kr/objects/cw-70e0032bada74852"},{"id":"cw-7106596188130f89","name":"Pentium P6300","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P6000","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel pentium (2009) p6300"],"fields":[{"key":"Model name","value":"Intel Pentium P6300","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P6300","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004161AK","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 11, 2011","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 11, 2011","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P6000","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2266.66,"unit":"MHz","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBU8","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fp6300&oldid=25208","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7777-r25208","location":"Intel/pentium (2009)/p6300 · revision 25208 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 1","value":36,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 1","value":35,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 1","value":2.12,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket — package module 1","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7106596188130f89","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7777-r25208","chipswiki-31578-r92969","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-7106596188130f89"},{"id":"cw-7114e8c79cbc442b","name":"K6-2/366AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-366afr"],"fields":[{"key":"Model name","value":"K6-2/366AFR","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/366AFR","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/366AFR","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 28, 1998","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 1999","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":366.66,"unit":"MHz","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8362-r26057","location":"Amd/k6-2/k6-2-366afr · revision 26057 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7114e8c79cbc442b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-366afr&oldid=26057","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8362-r26057"],"url":"https://museum.vlsi.kr/objects/cw-7114e8c79cbc442b"},{"id":"cw-711f0dee7ce2188a","name":"CN5850-800 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5850-800bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5850-800 EXP","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5850-800 EXP","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5850-800BG1521-EXP","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8131-r25790","location":"Cavium/octeon plus/cn5850-800bg1521-exp · revision 25790 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-800bg1521-exp&oldid=25790","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-711f0dee7ce2188a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8131-r25790","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-711f0dee7ce2188a"},{"id":"cw-71225257b4c200eb","name":"N8086-2","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N8086","year":null,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 n8086-2"],"fields":[{"key":"Model name","value":"AMD N8086-2","unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N8086-2","unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"N8086-2","unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N8086","unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-44","unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8497-r26690","location":"Amd/am8086/n8086-2 · revision 26690 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71225257b4c200eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8497-r26690"],"url":"https://museum.vlsi.kr/objects/cw-71225257b4c200eb"},{"id":"cw-713e0ae7f30aaa86","name":"Xeon Gold 6138F","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6138f"],"fields":[{"key":"Model name","value":"Xeon Gold 6138F","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6138F","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303593900","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3KK","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":135,"unit":"W","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-713e0ae7f30aaa86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1507-r4959","location":"Intel/xeon gold/6138f · revision 4959 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x16 KiB","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8157-r25816","location":"Cavium/octeon plus/cn5830-600bg1521-nsp · revision 25816 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5830-600bg1521-nsp&oldid=25816","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-714e7cc9d937381a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8157-r25816","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-714e7cc9d937381a"},{"id":"cw-715e7dc164fcdcff","name":"Pentium Silver N5000","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2017,"architecture":"Goldmont Plus","process":"14 nm","aliases":["Intel pentium silver n5000"],"fields":[{"key":"Model name","value":"Pentium Silver N5000","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N5000","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8068003067406","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3RZ","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 11, 2017","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 11, 2017","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium Silver","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont Plus","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Gemini Lake","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 605","unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":18,"unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":200,"unit":"MHz","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":750,"unit":"MHz","sourceId":"chipswiki-7504-r24400","location":"Intel/pentium silver/n5000 · revision 24400 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fn5000&oldid=24400","sourceDate":"2018-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1090","unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1090,"unit":"","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":25,"unit":"mm","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31338-r92075","location":"Template:Packages/intel/fcbga-1090 · revision 92075 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-01. Not an independent measurement.","entityId":"cw-715e7dc164fcdcff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1090&oldid=92075","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7504-r24400","chipswiki-31338-r92075"],"url":"https://museum.vlsi.kr/objects/cw-715e7dc164fcdcff"},{"id":"cw-71640dfe210d61a9","name":"Pentium N3710","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N3000","year":2015,"architecture":"Airmont","process":"14 nm","aliases":["Intel pentium (2009) n3710"],"fields":[{"key":"Model name","value":"Intel Pentium N3710","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N3710","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715927","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KL","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March, 2015","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2015","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N3000","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2567,"unit":"MHz","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"IDI","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Braswell","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1170","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. 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Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x24 KiB","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. 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Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. 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Not an independent measurement.","entityId":"cw-71640dfe210d61a9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fn3710&oldid=21414","sourceDate":"2018-03-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-6861-r21414","location":"Intel/pentium (2009)/n3710 · revision 21414 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-27. 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Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-8860","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615005760AB","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-8800","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2266.66,"unit":"MHz","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2666.66,"unit":"MHz","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3F","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Boxboro","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":513,"unit":"mm²","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24,"unit":"MiB","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7177f8713d3c527e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-8860&oldid=25063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7693-r25063","location":"Intel/xeon e7/e7-8860 · revision 25063 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7752-r25134","location":"Intel/xeon e3/e3-1585 v5 · revision 25134 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1585%20v5&oldid=25134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-71813c0add424bc3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6140,"unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806736140","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303405200","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3AX","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 25, 2017","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1503-r4955","location":"Intel/xeon gold/6140 · revision 4955 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-71a29ebd56811678","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6140&oldid=4955","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1503-r4955"],"url":"https://museum.vlsi.kr/objects/cw-71a29ebd56811678"},{"id":"cw-71bb42fc4c8e88bf","name":"K6-2/475ADK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-475adk"],"fields":[{"key":"Model name","value":"K6-2/475ADK","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/475ADK","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/475ADK","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 20, 1999","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":475,"unit":"MHz","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95 MT/s","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.1,"unit":"V","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8341-r26036","location":"Amd/k6-2/k6-2-475adk · revision 26036 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71bb42fc4c8e88bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-475adk&oldid=26036","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8341-r26036"],"url":"https://museum.vlsi.kr/objects/cw-71bb42fc4c8e88bf"},{"id":"cw-71e5ac1fcd6fcd2a","name":"Am186ES–40KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ES","year":1995,"architecture":"80186","aliases":["Amd am186ex am186es–40kc\\w"],"fields":[{"key":"Model name","value":"Am186ES–40KC\\W","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ES–40KC\\W","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ES–40KC\\W","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ES","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14619-r44680","location":"Amd/am186ex/am186es–40kc\\w · revision 44680 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-71e5ac1fcd6fcd2a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14619-r44680"],"url":"https://museum.vlsi.kr/objects/cw-71e5ac1fcd6fcd2a"},{"id":"cw-71e5f69bb41c9688","name":"K6-2E/300AFR-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-300afr-66"],"fields":[{"key":"Model name","value":"K6-2E/300AFR-66","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/300AFR-66","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/300AFR-66","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1999","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1999","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8326-r26021","location":"Amd/k6-2/k6-2e-300afr-66 · revision 26021 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e5f69bb41c9688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-300afr-66&oldid=26021","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8326-r26021"],"url":"https://museum.vlsi.kr/objects/cw-71e5f69bb41c9688"},{"id":"cw-71e8a85f3224af95","name":"Core i7-2570QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2570qm"],"fields":[{"key":"Model name","value":"Core i7-2570QM","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2570QM","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701020900","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0CM","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2011,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2011,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7901-r25405","location":"Intel/core i7/i7-2570qm · revision 25405 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2570qm&oldid=25405","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-71e8a85f3224af95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7901-r25405","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-71e8a85f3224af95"},{"id":"cw-7205869e78bdec74","name":"Xeon D-1577","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1577"],"fields":[{"key":"Model name","value":"Xeon D-1577","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1577","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402570503","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2M2","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2016","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2016","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2100,"unit":"MHz","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Y0","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x256 KiB","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-7205869e78bdec74","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24,"unit":"MiB","sourceId":"chipswiki-3738-r11447","location":"Intel/xeon d/d-1577 · revision 11447 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-72136b7910aaf09c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4000&oldid=1226","sourceDate":"2021-11-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-571-r1226","location":"Intel/celeron/n4000 · revision 1226 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-08. 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Not an independent measurement.","entityId":"cw-72136b7910aaf09c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4000&oldid=1226","sourceDate":"2021-11-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-571-r1226","location":"Intel/celeron/n4000 · revision 1226 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-08. Not an independent measurement.","entityId":"cw-72136b7910aaf09c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4000&oldid=1226","sourceDate":"2021-11-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-571-r1226","location":"Intel/celeron/n4000 · revision 1226 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-08. Not an independent measurement.","entityId":"cw-72136b7910aaf09c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4000&oldid=1226","sourceDate":"2021-11-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-571-r1226","location":"Intel/celeron/n4000 · revision 1226 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-08. Not an independent measurement.","entityId":"cw-72136b7910aaf09c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4000&oldid=1226","sourceDate":"2021-11-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 600","unit":"","sourceId":"chipswiki-571-r1226","location":"Intel/celeron/n4000 · revision 1226 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-08. Not an independent measurement.","entityId":"cw-72136b7910aaf09c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4000&oldid=1226","sourceDate":"2021-11-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-571-r1226","location":"Intel/celeron/n4000 · revision 1226 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-08. Not an independent measurement.","entityId":"cw-72136b7910aaf09c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4000&oldid=1226","sourceDate":"2021-11-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-571-r1226","location":"Intel/celeron/n4000 · revision 1226 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-08. 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Not an independent measurement.","entityId":"cw-72136b7910aaf09c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4000&oldid=1226","sourceDate":"2021-11-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":650,"unit":"MHz","sourceId":"chipswiki-571-r1226","location":"Intel/celeron/n4000 · revision 1226 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-08. 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Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.6,"unit":"V","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-359","unit":"","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CBGA","unit":"","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-359","unit":"","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"KiB","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x2 KiB","unit":"","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"direct mapped","unit":"","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"KiB","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x2 KiB","unit":"","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"direct mapped","unit":"","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"KiB","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8112-r25771","location":"Exponential technology/x704/410 · revision 25771 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-728a0fadc2550996","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Exponential%20technology%2Fx704%2F410&oldid=25771","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8112-r25771"],"url":"https://museum.vlsi.kr/objects/cw-728a0fadc2550996"},{"id":"cw-72924f157ed81689","name":"Am486DX4-100SV8B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX4S","year":1996,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx4-100sv8b"],"fields":[{"key":"Model name","value":"Am486DX4-100SV8B","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX4-100SV8B","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX4-100SV8B","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"S80486DX4-100SV8B","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1995,"unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 1996","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX4S","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":100,"unit":"MHz","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am486DX4S","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8556-r26752","location":"Amd/am486/am486dx4-100sv8b · revision 26752 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-72924f157ed81689","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8556-r26752"],"url":"https://museum.vlsi.kr/objects/cw-72924f157ed81689"},{"id":"cw-7316de3094f80c39","name":"CN5860-800 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5860-800bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5860-800 EXP","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5860-800 EXP","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5860-800BG1521-EXP","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x16 KiB","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8119-r25778","location":"Cavium/octeon plus/cn5860-800bg1521-exp · revision 25778 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-800bg1521-exp&oldid=25778","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7316de3094f80c39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-732599078421d73f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-12. Not an independent measurement.","entityId":"cw-732599078421d73f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-12. Not an independent measurement.","entityId":"cw-732599078421d73f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-12. Not an independent measurement.","entityId":"cw-732599078421d73f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3889-r12296","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-732599078421d73f"},{"id":"cw-734911f028b1280f","name":"AMD-K6-200ALR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Desktop K6","year":1997,"architecture":"K6","process":"350 nm","aliases":["Amd k6 amd-k6-200alr"],"fields":[{"key":"Model name","value":"AMD-K6-200ALR","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-200ALR","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-200ALR","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1997","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1997","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Desktop K6","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":199.99,"unit":"MHz","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"6k86","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":162,"unit":"mm²","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.9,"unit":"V","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-911-r2490","location":"Amd/k6/amd-k6-200alr · revision 2490 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-11-09. Not an independent measurement.","entityId":"cw-734911f028b1280f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6-200alr&oldid=2490","sourceDate":"2020-11-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-911-r2490"],"url":"https://museum.vlsi.kr/objects/cw-734911f028b1280f"},{"id":"cw-734bc5c045955245","name":"Core i5-8420T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-8420t"],"fields":[{"key":"Model name","value":"Core i5-8420T","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8420T","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4968-r16065","location":"Intel/core i5/i5-8420t · revision 16065 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-734bc5c045955245","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420t&oldid=16065","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4968-r16065"],"url":"https://museum.vlsi.kr/objects/cw-734bc5c045955245"},{"id":"cw-735726ad79aab884","name":"Xeon Silver 4215","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon silver 4215"],"fields":[{"key":"Model name","value":"Xeon Silver 4215","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4215,"unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504212701","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFBA","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4200,"unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L0","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L1","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":11,"unit":"MiB","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x1.375 MiB","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1444-r4884","location":"Intel/xeon silver/4215 · revision 4884 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-735726ad79aab884","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4215&oldid=4884","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1444-r4884"],"url":"https://museum.vlsi.kr/objects/cw-735726ad79aab884"},{"id":"cw-7377c43a4dcb58af","name":"K6-2E/350AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-350afr"],"fields":[{"key":"Model name","value":"K6-2E/350AFR","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/350AFR","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/350AFR","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 1999","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 1999","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":349.99,"unit":"MHz","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7377c43a4dcb58af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-350afr&oldid=26014","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8319-r26014","location":"Amd/k6-2/k6-2e-350afr · revision 26014 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5750-600 SSP","unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5750-600BG1217-SSP","unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8166-r25825","location":"Cavium/octeon plus/cn5750-600bg1217-ssp · revision 25825 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-600bg1217-ssp&oldid=25825","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-737bada7109cc5de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7383c2ef114452d9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a32&oldid=3790","sourceDate":"2020-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":8,"unit":"","sourceId":"chipswiki-1212-r3790","location":"Arm holdings/microarchitectures/cortex-a32 · revision 3790 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-07. Not an independent measurement.","entityId":"cw-7383c2ef114452d9","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-a32&oldid=3790","sourceDate":"2020-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8 AArch32","unit":"","sourceId":"chipswiki-1212-r3790","location":"Arm holdings/microarchitectures/cortex-a32 · revision 3790 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-07. 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Not an independent measurement.","entityId":"cw-739403e5333e918b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dcb&oldid=26681","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-1DCB","unit":"","sourceId":"chipswiki-8488-r26681","location":"Amd/am9080/am9080a-1dcb · revision 26681 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHM0800ALS1B","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 14, 2001","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 14, 2001","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8418-r26126","location":"Amd/duron/dhm0800als1b · revision 26126 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73a5e0256668925d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8418-r26126"],"url":"https://museum.vlsi.kr/objects/cw-73a5e0256668925d"},{"id":"cw-73baf5f2f3833337","name":"Pentium 987","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"900","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel pentium (2009) 987"],"fields":[{"key":"Model name","value":"Pentium 987","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":987,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701147601","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701084700","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701084701","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0FA","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR08E","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0F1","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0V4","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2012","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 2012","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73baf5f2f3833337","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F987&oldid=25231","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7793-r25231","location":"Intel/pentium (2009)/987 · revision 25231 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8360-r26055","location":"Amd/k6-2/k6-2-380afk · revision 26055 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73c0295e308a082d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-380afk&oldid=26055","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8360-r26055"],"url":"https://museum.vlsi.kr/objects/cw-73c0295e308a082d"},{"id":"cw-73d28e16ab019bf3","name":"Pentium 967","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"900","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel pentium (2009) 967"],"fields":[{"key":"Model name","value":"Pentium 967","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":967,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701147801","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701022501","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0FC","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0EX","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 3, 2011","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 3, 2011","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7795-r25233","location":"Intel/pentium (2009)/967 · revision 25233 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F967&oldid=25233","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73d28e16ab019bf3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7795-r25233","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-73d28e16ab019bf3"},{"id":"cw-73d9234f8d268548","name":"Snapdragon 865","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","series":"800","year":2020,"architecture":"Cortex-A77","process":"7 nm","aliases":["Qualcomm snapdragon 800 865"],"fields":[{"key":"Model name","value":"Snapdragon 865","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM865","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"SM8250","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 4, 2019","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2020","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 800","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2110,"unit":"MHz","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-02-10. 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Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":2840,"unit":"MHz","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A77","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 585 Gold","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 585 Silver","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-02-10. 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Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. 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Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-02-10. 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Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":64,"unit":"KiB","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"1x64 KiB","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-02-10. Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity — Cache (section 1)","value":"4-way set associative","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-02-10. 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Not an independent measurement.","entityId":"cw-73d9234f8d268548","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F865&oldid=1036","sourceDate":"2022-02-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"1x512 KiB","unit":"","sourceId":"chipswiki-514-r1036","location":"Qualcomm/snapdragon 800/865 · revision 1036 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-02-10. 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Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 2, 2009","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 2, 2009","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z500","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1599.99,"unit":"MHz","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"533.33 MT/s","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Menlow","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Poulsbo","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":28,"unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":24.18,"unit":"mm²","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2,"unit":"W","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8063-r25699","location":"Intel/atom/z530p · revision 25699 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-437","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":437,"unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73de904511c39d5c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8063-r25699","chipswiki-31502-r92564"],"url":"https://museum.vlsi.kr/objects/cw-73de904511c39d5c"},{"id":"cw-73e4ced23c27d9a5","name":"K6-2E/333AMZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-333amz"],"fields":[{"key":"Model name","value":"K6-2E/333AMZ","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/333AMZ","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/333AMZ","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 1999","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 1999","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.66,"unit":"MHz","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95.33 MT/s","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.9,"unit":"V","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8321-r26016","location":"Amd/k6-2/k6-2e-333amz · revision 26016 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-73e4ced23c27d9a5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-333amz&oldid=26016","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8321-r26016"],"url":"https://museum.vlsi.kr/objects/cw-73e4ced23c27d9a5"},{"id":"cw-73ebedd9d5d952af","name":"Xiaomi","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Phytium","year":2017,"process":"28 nm","aliases":["Phytium microarchitectures xiaomi"],"fields":[{"key":"Architecture name","value":"Xiaomi","unit":"","sourceId":"chipswiki-807-r2046","location":"Phytium/microarchitectures/xiaomi · revision 2046 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-08. Not an independent measurement.","entityId":"cw-73ebedd9d5d952af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fxiaomi&oldid=2046","sourceDate":"2021-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Phytium","unit":"","sourceId":"chipswiki-807-r2046","location":"Phytium/microarchitectures/xiaomi · revision 2046 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-08. Not an independent measurement.","entityId":"cw-73ebedd9d5d952af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fxiaomi&oldid=2046","sourceDate":"2021-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-807-r2046","location":"Phytium/microarchitectures/xiaomi · revision 2046 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-08. Not an independent measurement.","entityId":"cw-73ebedd9d5d952af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fxiaomi&oldid=2046","sourceDate":"2021-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2017,"unit":"","sourceId":"chipswiki-807-r2046","location":"Phytium/microarchitectures/xiaomi · revision 2046 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-08. Not an independent measurement.","entityId":"cw-73ebedd9d5d952af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fxiaomi&oldid=2046","sourceDate":"2021-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-807-r2046","location":"Phytium/microarchitectures/xiaomi · revision 2046 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-08. Not an independent measurement.","entityId":"cw-73ebedd9d5d952af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fxiaomi&oldid=2046","sourceDate":"2021-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-807-r2046","location":"Phytium/microarchitectures/xiaomi · revision 2046 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-08. Not an independent measurement.","entityId":"cw-73ebedd9d5d952af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fxiaomi&oldid=2046","sourceDate":"2021-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-807-r2046","location":"Phytium/microarchitectures/xiaomi · revision 2046 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-08. Not an independent measurement.","entityId":"cw-73ebedd9d5d952af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fxiaomi&oldid=2046","sourceDate":"2021-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-807-r2046","location":"Phytium/microarchitectures/xiaomi · revision 2046 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Panel","note":"Source-reported parameter; source revision 2021-03-08. Not an independent measurement.","entityId":"cw-73ebedd9d5d952af","scope":"Panel","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fxiaomi&oldid=2046","sourceDate":"2021-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-807-r2046","location":"Phytium/microarchitectures/xiaomi · revision 2046 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"CMC","note":"Source-reported parameter; source revision 2021-03-08. Not an independent measurement.","entityId":"cw-73ebedd9d5d952af","scope":"CMC","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fxiaomi&oldid=2046","sourceDate":"2021-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"FTC660","unit":"","sourceId":"chipswiki-807-r2046","location":"Phytium/microarchitectures/xiaomi · revision 2046 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-03-08. Not an independent measurement.","entityId":"cw-73ebedd9d5d952af","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fxiaomi&oldid=2046","sourceDate":"2021-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"FTC661","unit":"","sourceId":"chipswiki-807-r2046","location":"Phytium/microarchitectures/xiaomi · revision 2046 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-03-08. Not an independent measurement.","entityId":"cw-73ebedd9d5d952af","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fxiaomi&oldid=2046","sourceDate":"2021-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"FTC662","unit":"","sourceId":"chipswiki-807-r2046","location":"Phytium/microarchitectures/xiaomi · revision 2046 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2021-03-08. Not an independent measurement.","entityId":"cw-73ebedd9d5d952af","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Fmicroarchitectures%2Fxiaomi&oldid=2046","sourceDate":"2021-03-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-807-r2046"],"url":"https://museum.vlsi.kr/objects/cw-73ebedd9d5d952af"},{"id":"cw-741f96a6cf9a149c","name":"Snapdragon 720G","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","year":2020,"architecture":"Cortex-A76","process":"8 nm","aliases":["Qualcomm snapdragon 700 720g"],"fields":[{"key":"Model name","value":"Snapdragon 720G","unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. 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Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. 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Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"SM7125","unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 20, 2020","unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 20, 2020","unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 700","unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2300,"unit":"MHz","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-10-06. 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Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A76","unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 465 Gold","unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 465 Silver","unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-10-06. 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Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. 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Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. 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Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 618","unit":"","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-591-r1367","location":"Qualcomm/snapdragon 700/720g · revision 1367 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-06. Not an independent measurement.","entityId":"cw-741f96a6cf9a149c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20700%2F720g&oldid=1367","sourceDate":"2021-10-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-591-r1367"],"url":"https://museum.vlsi.kr/objects/cw-741f96a6cf9a149c"},{"id":"cw-7422600a4e0fa02c","name":"Snapdragon 439","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","series":"400","year":2018,"architecture":"Cortex-A53","process":"12 nm","aliases":["Qualcomm snapdragon 400 439"],"fields":[{"key":"Model name","value":"Snapdragon 439","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM439","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 26, 2018","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 26, 2018","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 400","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":400,"unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1450,"unit":"MHz","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1950,"unit":"MHz","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","alternatives":[{"value":"4 GB","sourceId":"chipswiki-534-r1093","reason":"Qualcomm/snapdragon 400/439 · revision 1093 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Memory type","value":"LPDDR4","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 505","unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":1080,"unit":"","sourceId":"chipswiki-534-r1093","location":"Qualcomm/snapdragon 400/439 · revision 1093 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-20. Not an independent measurement.","entityId":"cw-7422600a4e0fa02c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20400%2F439&oldid=1093","sourceDate":"2022-01-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-534-r1093"],"url":"https://museum.vlsi.kr/objects/cw-7422600a4e0fa02c"},{"id":"cw-7489d6bce74e9703","name":"Celeron G3920","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel celeron g3920"],"fields":[{"key":"Model name","value":"Celeron G3920","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G3920","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80662G3920","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2HX","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-8028-r25632","location":"Intel/celeron/g3920 · revision 25632 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7489d6bce74e9703","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8028-r25632","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-7489d6bce74e9703"},{"id":"cw-748ec4b84f00d13e","name":"Am186ED–25KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186ed–25kc\\w"],"fields":[{"key":"Model name","value":"Am186ED–25KC\\W","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ED–25KC\\W","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ED–25KC\\W","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14669-r44730","location":"Amd/am186ex/am186ed–25kc\\w · revision 44730 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-748ec4b84f00d13e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14669-r44730"],"url":"https://museum.vlsi.kr/objects/cw-748ec4b84f00d13e"},{"id":"cw-74ee951d87905c07","name":"CN3010-400 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3000","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3010-400bg525-scp"],"fields":[{"key":"Model name","value":"Cavium CN3010-400 SCP","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3010-400 SCP","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3010-400BG525-SCP","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3000","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-525","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":24,"unit":"KiB","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":1.986,"unit":"GiB/s","sourceId":"chipswiki-8272-r25932","location":"Cavium/octeon/cn3010-400bg525-scp · revision 25932 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74ee951d87905c07","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-400bg525-scp&oldid=25932","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8272-r25932"],"url":"https://museum.vlsi.kr/objects/cw-74ee951d87905c07"},{"id":"cw-74f88d1a2577aca5","name":"K6-2/400AFK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile P","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-400afk"],"fields":[{"key":"Model name","value":"K6-2/400AFK","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/400AFK","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/400AFK","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile P","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":399.99,"unit":"MHz","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8356-r26051","location":"Amd/k6-2/k6-2-400afk · revision 26051 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-74f88d1a2577aca5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-400afk&oldid=26051","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8356-r26051"],"url":"https://museum.vlsi.kr/objects/cw-74f88d1a2577aca5"},{"id":"cw-74fc50bdaaf91c9f","name":"ARM6","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2022,"process":"0.8 µm","aliases":["Arm holdings microarchitectures arm6"],"fields":[{"key":"Architecture name","value":"ARM4","unit":"","sourceId":"chipswiki-32-r96962","location":"Arm holdings/microarchitectures/arm6 · revision 96962 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-05. Not an independent measurement.","entityId":"cw-74fc50bdaaf91c9f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm6&oldid=96962","sourceDate":"2022-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-32-r96962","location":"Arm holdings/microarchitectures/arm6 · revision 96962 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-05. Not an independent measurement.","entityId":"cw-74fc50bdaaf91c9f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm6&oldid=96962","sourceDate":"2022-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"VLSI Technology","unit":"","sourceId":"chipswiki-32-r96962","location":"Arm holdings/microarchitectures/arm6 · revision 96962 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-05. Not an independent measurement.","entityId":"cw-74fc50bdaaf91c9f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm6&oldid=96962","sourceDate":"2022-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GEC-Plessey Semiconductors","unit":"","sourceId":"chipswiki-32-r96962","location":"Arm holdings/microarchitectures/arm6 · revision 96962 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-11-05. Not an independent measurement.","entityId":"cw-74fc50bdaaf91c9f","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm6&oldid=96962","sourceDate":"2022-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Sharp","unit":"","sourceId":"chipswiki-32-r96962","location":"Arm holdings/microarchitectures/arm6 · revision 96962 · {{microarchitecture}} / manufacturer 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 3","note":"Source-reported parameter; source revision 2022-11-05. Not an independent measurement.","entityId":"cw-74fc50bdaaf91c9f","scope":"manufacturer 3","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm6&oldid=96962","sourceDate":"2022-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2022,"unit":"","sourceId":"chipswiki-32-r96962","location":"Arm holdings/microarchitectures/arm6 · revision 96962 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-05. Not an independent measurement.","entityId":"cw-74fc50bdaaf91c9f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm6&oldid=96962","sourceDate":"2022-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.8,"unit":"µm","sourceId":"chipswiki-32-r96962","location":"Arm holdings/microarchitectures/arm6 · revision 96962 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-05. Not an independent measurement.","entityId":"cw-74fc50bdaaf91c9f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm6&oldid=96962","sourceDate":"2022-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-32-r96962","location":"Arm holdings/microarchitectures/arm6 · revision 96962 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-05. Not an independent measurement.","entityId":"cw-74fc50bdaaf91c9f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm6&oldid=96962","sourceDate":"2022-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Scalar","unit":"","sourceId":"chipswiki-32-r96962","location":"Arm holdings/microarchitectures/arm6 · revision 96962 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-05. 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Not an independent measurement.","entityId":"cw-74fc50bdaaf91c9f","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm6&oldid=96962","sourceDate":"2022-11-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"1-way","unit":"","sourceId":"chipswiki-32-r96962","location":"Arm holdings/microarchitectures/arm6 · revision 96962 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-05. 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Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8cx","unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 6, 2018","unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. 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Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 800","unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2840,"unit":"MHz","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-01-17. 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Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 4","value":3020,"unit":"MHz","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / frequency 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 4","note":"Source-reported parameter; source revision 2022-01-17. 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Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. 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Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. 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Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":10,"unit":"MiB","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. 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Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":63.58,"unit":"GiB/s","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 680 GPU","unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-539-r1099","location":"Qualcomm/snapdragon 800/8cx · revision 1099 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-17. Not an independent measurement.","entityId":"cw-74fe3bafffc775bf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20800%2F8cx&oldid=1099","sourceDate":"2022-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-539-r1099"],"url":"https://museum.vlsi.kr/objects/cw-74fe3bafffc775bf"},{"id":"cw-750025e7bfabf917","name":"QorIQ P1021","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":2010,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1021"],"fields":[{"key":"Model name","value":"QorIQ P1021","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1021","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 7, 2009","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2010","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":2.98,"unit":"GiB/s","sourceId":"chipswiki-8098-r25757","location":"Freescale/qoriq/p1021 · revision 25757 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1021&oldid=25757","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-II-689","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":689,"unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750025e7bfabf917","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-ii-689&oldid=92168","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":31,"unit":"mm","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2609 v4","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002032901","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80660E52609V4","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2P1","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":20,"unit":"MiB","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2.5 MiB","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7746-r25123","location":"Intel/xeon e5/e5-2609 v4 · revision 25123 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7505c399a63651f6","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2609%20v4&oldid=25123","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7746-r25123"],"url":"https://museum.vlsi.kr/objects/cw-7505c399a63651f6"},{"id":"cw-750d4876d4f2ebb1","name":"Duron 800 (Camaro)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhm0800avs1bm"],"fields":[{"key":"Model name","value":"Duron 800","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 800","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHM0800AVS1BM","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2001,"unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2001,"unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.4,"unit":"V","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8417-r26125","location":"Amd/duron/dhm0800avs1bm · revision 26125 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-750d4876d4f2ebb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8417-r26125"],"url":"https://museum.vlsi.kr/objects/cw-750d4876d4f2ebb1"},{"id":"cw-75583e533b32772f","name":"AMD-K6/266ACZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Mobile K6","year":1998,"architecture":"K6","process":"250 nm","aliases":["Amd k6 amd-k6 266acz"],"fields":[{"key":"Model name","value":"AMD-K6/266ACZ","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6/266ACZ","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6/266ACZ","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 1998","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 5, 1998","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Mobile K6","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266.66,"unit":"MHz","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Little Foot","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":68,"unit":"mm²","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.1,"unit":"V","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8288-r25975","location":"Amd/k6/amd-k6/266acz · revision 25975 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-75583e533b32772f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F266acz&oldid=25975","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8288-r25975"],"url":"https://museum.vlsi.kr/objects/cw-75583e533b32772f"},{"id":"cw-757ea1034c8718ea","name":"EPYC 7662","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7662"],"fields":[{"key":"Model name","value":"EPYC 7662","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7662,"unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000137","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000137WOF","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 19, 2020","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 19, 2020","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":64,"unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":128,"unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":225,"unit":"W","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"MiB","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64 × 32 KiB","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"MiB","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64 × 32 KiB","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"64 × 512 KiB","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16 × 16 MiB","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-555-r1152","location":"Amd/epyc/7662 · revision 1152 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-12-21. Not an independent measurement.","entityId":"cw-757ea1034c8718ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","sourceDate":"2021-12-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-555-r1152"],"url":"https://museum.vlsi.kr/objects/cw-757ea1034c8718ea"},{"id":"cw-759aa5d877148044","name":"Ryzen 7 PRO 5750GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 7 pro 5750ge"],"fields":[{"key":"Model name","value":"Ryzen 7 5750GE","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5750GE","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000257","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2021","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4600,"unit":"MHz","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2000,"unit":"MHz","sourceId":"chipswiki-607-r1429","location":"Amd/ryzen 7/pro 5750ge · revision 1429 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-14. Not an independent measurement.","entityId":"cw-759aa5d877148044","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","sourceDate":"2021-09-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-607-r1429"],"url":"https://museum.vlsi.kr/objects/cw-759aa5d877148044"},{"id":"cw-75f9344092227db5","name":"Am186CC-40KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CC","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186cc-40kc\\w"],"fields":[{"key":"Model name","value":"Am186CC-40KC\\W","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CC-40KC\\W","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CC-40KC\\W","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CC","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14689-r44750","location":"Amd/am186cx/am186cc-40kc\\w · revision 44750 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-75f9344092227db5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14689-r44750"],"url":"https://museum.vlsi.kr/objects/cw-75f9344092227db5"},{"id":"cw-762c8db035826e75","name":"QorIQ P1013","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":2010,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1013"],"fields":[{"key":"Model name","value":"QorIQ P1013","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1013","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 9, 2009","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2010,"unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1067,"unit":"MHz","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8104-r25763","location":"Freescale/qoriq/p1013 · revision 25763 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-762c8db035826e75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1013&oldid=25763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TE-PBGA-II-689","unit":"","sourceId":"chipswiki-31374-r92168","location":"Template:Packages/freescale/te-pbga-ii-689 · revision 92168 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–50KC\\W","unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 31, 1998","unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"12.5 MT/s","unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14636-r44697","location":"Amd/am186ex/am186er–50kc\\w · revision 44697 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-76533b278c80cc1b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14636-r44697"],"url":"https://museum.vlsi.kr/objects/cw-76533b278c80cc1b"},{"id":"cw-765993365e31a93d","name":"Knights Peak","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":null,"process":"7 nm","aliases":["Intel microarchitectures knights peak"],"fields":[{"key":"Architecture name","value":"Knights Peak","unit":"","sourceId":"chipswiki-6404-r19999","location":"Intel/microarchitectures/knights peak · revision 19999 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-765993365e31a93d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20peak&oldid=19999","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6404-r19999","location":"Intel/microarchitectures/knights peak · revision 19999 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-765993365e31a93d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20peak&oldid=19999","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6404-r19999","location":"Intel/microarchitectures/knights peak · revision 19999 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-765993365e31a93d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20peak&oldid=19999","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-6404-r19999","location":"Intel/microarchitectures/knights peak · revision 19999 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-765993365e31a93d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20peak&oldid=19999","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-6404-r19999","location":"Intel/microarchitectures/knights peak · revision 19999 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-765993365e31a93d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20peak&oldid=19999","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-16","unit":"","sourceId":"chipswiki-6404-r19999","location":"Intel/microarchitectures/knights peak · revision 19999 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-765993365e31a93d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20peak&oldid=19999","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Knights Hill","unit":"","sourceId":"chipswiki-6404-r19999","location":"Intel/microarchitectures/knights peak · revision 19999 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-08. Not an independent measurement.","entityId":"cw-765993365e31a93d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fknights%20peak&oldid=19999","sourceDate":"2018-04-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6404-r19999"],"url":"https://museum.vlsi.kr/objects/cw-765993365e31a93d"},{"id":"cw-765ec6d34abe9867","name":"CN3110-500 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-500bg868-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3110-500 NSP","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-500 NSP","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-500BG868-NSP","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-500bg868-nsp&oldid=25919","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8259-r25919","location":"Cavium/octeon/cn3110-500bg868-nsp · revision 25919 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-765ec6d34abe9867","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8259-r25919","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-765ec6d34abe9867"},{"id":"cw-768fbd61c6959c3a","name":"Core i5-2520M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i5 i5-2520m"],"fields":[{"key":"Model name","value":"Core i5-2520M","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-2520M","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700840017","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062700844214S","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR048","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04A","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 2011","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-2000","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-768fbd61c6959c3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2520m&oldid=25500","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7952-r25500","location":"Intel/core i5/i5-2520m · revision 25500 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-76d079eea4288a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Falc12b00&oldid=432","sourceDate":"2022-09-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Neoverse N1","unit":"","sourceId":"chipswiki-212-r432","location":"Annapurna labs/alpine/alc12b00 · revision 432 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-02. Not an independent measurement.","entityId":"cw-76d079eea4288a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Falc12b00&oldid=432","sourceDate":"2022-09-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Neoverse N1","unit":"","sourceId":"chipswiki-212-r432","location":"Annapurna labs/alpine/alc12b00 · revision 432 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-02. Not an independent measurement.","entityId":"cw-76d079eea4288a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Falc12b00&oldid=432","sourceDate":"2022-09-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-212-r432","location":"Annapurna labs/alpine/alc12b00 · revision 432 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-02. Not an independent measurement.","entityId":"cw-76d079eea4288a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Falc12b00&oldid=432","sourceDate":"2022-09-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":30000000000,"unit":"","sourceId":"chipswiki-212-r432","location":"Annapurna labs/alpine/alc12b00 · revision 432 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-02. 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Not an independent measurement.","entityId":"cw-76d079eea4288a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Falc12b00&oldid=432","sourceDate":"2022-09-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"MiB","sourceId":"chipswiki-212-r432","location":"Annapurna labs/alpine/alc12b00 · revision 432 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-02. Not an independent measurement.","entityId":"cw-76d079eea4288a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Falc12b00&oldid=432","sourceDate":"2022-09-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":4,"unit":"MiB","sourceId":"chipswiki-212-r432","location":"Annapurna labs/alpine/alc12b00 · revision 432 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-02. Not an independent measurement.","entityId":"cw-76d079eea4288a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Falc12b00&oldid=432","sourceDate":"2022-09-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64x64 KiB","unit":"","sourceId":"chipswiki-212-r432","location":"Annapurna labs/alpine/alc12b00 · revision 432 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-02. 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Not an independent measurement.","entityId":"cw-76d079eea4288a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Falc12b00&oldid=432","sourceDate":"2022-09-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64x64 KiB","unit":"","sourceId":"chipswiki-212-r432","location":"Annapurna labs/alpine/alc12b00 · revision 432 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-02. 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Not an independent measurement.","entityId":"cw-76d079eea4288a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Falc12b00&oldid=432","sourceDate":"2022-09-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"64x1 MiB","unit":"","sourceId":"chipswiki-212-r432","location":"Annapurna labs/alpine/alc12b00 · revision 432 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-02. 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Not an independent measurement.","entityId":"cw-76d079eea4288a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Falc12b00&oldid=432","sourceDate":"2022-09-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x32 MiB","unit":"","sourceId":"chipswiki-212-r432","location":"Annapurna labs/alpine/alc12b00 · revision 432 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-02. 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Not an independent measurement.","entityId":"cw-76d079eea4288a98","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Annapurna%20labs%2Falpine%2Falc12b00&oldid=432","sourceDate":"2022-09-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-212-r432","location":"Annapurna labs/alpine/alc12b00 · revision 432 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-02. 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Not an independent measurement.","entityId":"cw-76e1763c12b05a8e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsandy%20bridge%20(client)&oldid=2299","sourceDate":"2020-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-885-r2299","location":"Intel/microarchitectures/sandy bridge (client) · revision 2299 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-29. 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Not an independent measurement.","entityId":"cw-76e1763c12b05a8e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsandy%20bridge%20(client)&oldid=2299","sourceDate":"2020-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Westmere","unit":"","sourceId":"chipswiki-885-r2299","location":"Intel/microarchitectures/sandy bridge (client) · revision 2299 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-12-29. Not an independent measurement.","entityId":"cw-76e1763c12b05a8e","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fsandy%20bridge%20(client)&oldid=2299","sourceDate":"2020-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"NetBurst","unit":"","sourceId":"chipswiki-885-r2299","location":"Intel/microarchitectures/sandy bridge (client) · revision 2299 · {{microarchitecture}} / predecessor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"predecessor 2","note":"Source-reported parameter; source revision 2020-12-29. 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Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x7-E3950","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 26, 2016","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2017,"unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x7","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3900","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2000,"unit":"MHz","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Apollo Lake","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Apollo Lake","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":12,"unit":"W","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":"-40 °C","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":110,"unit":"°C","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-1296","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1296","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-8041-r25673","location":"Intel/atom x7/x7-e3950 · revision 25673 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-770a844340766b79","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8041-r25673"],"url":"https://museum.vlsi.kr/objects/cw-770a844340766b79"},{"id":"cw-7726cf8456979362","name":"Celeron N3050","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N3000","year":2015,"architecture":"Airmont","process":"14 nm","aliases":["Intel celeron n3050"],"fields":[{"key":"Model name","value":"Intel Celeron N3050","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N3050","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715914","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715925","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR29H","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2A9","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March, 2015","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2015","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N3000","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2160,"unit":"MHz","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"IDI","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Braswell","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1170","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-292-r589","location":"Intel/celeron/n3050 · revision 589 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-08. Not an independent measurement.","entityId":"cw-7726cf8456979362","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3050&oldid=589","sourceDate":"2022-07-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-292-r589"],"url":"https://museum.vlsi.kr/objects/cw-7726cf8456979362"},{"id":"cw-77339aad71385b46","name":"Xeon W-3275M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"W-3200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon w w-3275m"],"fields":[{"key":"Model name","value":"Xeon W-3275M","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"W-3275M","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504248702","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFFK","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 3, 2019","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon W","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"W-3200","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":28,"unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.75,"unit":"MiB","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":896,"unit":"KiB","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":896,"unit":"KiB","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"28x32 KiB","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"28x1 MiB","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1709-r5944","location":"Intel/xeon w/w-3275m · revision 5944 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-07. Not an independent measurement.","entityId":"cw-77339aad71385b46","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","sourceDate":"2019-10-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1709-r5944"],"url":"https://museum.vlsi.kr/objects/cw-77339aad71385b46"},{"id":"cw-7738f95b46a90a44","name":"PipeRench","kind":"sku","entityType":"product-model","subtype":"sku","company":"Carnegie Mellon University","year":2002,"process":"180 nm","aliases":["Cmu piperench"],"fields":[{"key":"Model name","value":"PipeRench","unit":"","sourceId":"chipswiki-8113-r25772","location":"Cmu/piperench · revision 25772 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7738f95b46a90a44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cmu%2Fpiperench&oldid=25772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Carnegie Mellon University","unit":"","sourceId":"chipswiki-8113-r25772","location":"Cmu/piperench · revision 25772 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7738f95b46a90a44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cmu%2Fpiperench&oldid=25772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 2000","unit":"","sourceId":"chipswiki-8113-r25772","location":"Cmu/piperench · revision 25772 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7738f95b46a90a44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cmu%2Fpiperench&oldid=25772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2002,"unit":"","sourceId":"chipswiki-8113-r25772","location":"Cmu/piperench · revision 25772 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7738f95b46a90a44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cmu%2Fpiperench&oldid=25772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":120,"unit":"MHz","sourceId":"chipswiki-8113-r25772","location":"Cmu/piperench · revision 25772 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7738f95b46a90a44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cmu%2Fpiperench&oldid=25772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8113-r25772","location":"Cmu/piperench · revision 25772 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7738f95b46a90a44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cmu%2Fpiperench&oldid=25772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3650000,"unit":"","sourceId":"chipswiki-8113-r25772","location":"Cmu/piperench · revision 25772 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7738f95b46a90a44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cmu%2Fpiperench&oldid=25772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8113-r25772","location":"Cmu/piperench · revision 25772 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7738f95b46a90a44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cmu%2Fpiperench&oldid=25772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":49,"unit":"mm²","sourceId":"chipswiki-8113-r25772","location":"Cmu/piperench · revision 25772 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7738f95b46a90a44","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cmu%2Fpiperench&oldid=25772","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8113-r25772"],"url":"https://museum.vlsi.kr/objects/cw-7738f95b46a90a44"},{"id":"cw-773a6812fdd10dfb","name":"CN3850-500 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3850-500bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN3850-500 SCP","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3850-500 SCP","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3850-500BG1521-SCP","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":480,"unit":"KiB","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8206-r25865","location":"Cavium/octeon/cn3850-500bg1521-scp · revision 25865 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3850-500bg1521-scp&oldid=25865","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-773a6812fdd10dfb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8206-r25865","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-773a6812fdd10dfb"},{"id":"cw-7765b0ec40c1d810","name":"Core i3-9000T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-9000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-9000t"],"fields":[{"key":"Model name","value":"Core i3-9000T","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-9000T","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZC","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-9000","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-5264-r17225","location":"Intel/core i3/i3-9000t · revision 17225 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-7765b0ec40c1d810","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000t&oldid=17225","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5264-r17225"],"url":"https://museum.vlsi.kr/objects/cw-7765b0ec40c1d810"},{"id":"cw-777714fedeb26fbe","name":"Core i5-8420","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-8420"],"fields":[{"key":"Model name","value":"Core i5-8420","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8420","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4969-r16066","location":"Intel/core i5/i5-8420 · revision 16066 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-777714fedeb26fbe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8420&oldid=16066","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4969-r16066"],"url":"https://museum.vlsi.kr/objects/cw-777714fedeb26fbe"},{"id":"cw-7796016cfed61736","name":"AMD-K6-III+/500ACZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III+ Mobile","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-iii+ amd-k6-iii+-500acz"],"fields":[{"key":"Model name","value":"AMD-K6-III+/500ACZ","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-III+/500ACZ","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-III+/500ACZ","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 18, 2000","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 18, 2000","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III+","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III+ Mobile","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":499.99,"unit":"MHz","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":3,"unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21400000,"unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8316-r26010","location":"Amd/k6-iii+/amd-k6-iii+-500acz · revision 26010 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7796016cfed61736","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iii%2B-500acz&oldid=26010","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8316-r26010"],"url":"https://museum.vlsi.kr/objects/cw-7796016cfed61736"},{"id":"cw-77c04cdfd5a42708","name":"Xeon D-1559","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1559"],"fields":[{"key":"Model name","value":"Xeon D-1559","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1559","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402570801","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2M5","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 2016","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 2016","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2100,"unit":"MHz","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Y0","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4700000000,"unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":306.18,"unit":"mm²","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x256 KiB","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.5 MiB","unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-77c04cdfd5a42708","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3736-r11445","location":"Intel/xeon d/d-1559 · revision 11445 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-IIIE+/450ACR","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":3,"unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21400000,"unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":12,"unit":"W","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8315-r26005","location":"Amd/k6-iii+/amd-k6-iiie+-450acr · revision 26005 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-77c08b0efea8a670","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-450acr&oldid=26005","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8315-r26005"],"url":"https://museum.vlsi.kr/objects/cw-77c08b0efea8a670"},{"id":"cw-77e4d302a63aa1c5","name":"Ryzen 5 5600H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 5 5600h"],"fields":[{"key":"Model name","value":"Ryzen 5 5600H","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5600H","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000296","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1800,"unit":"MHz","sourceId":"chipswiki-714-r1721","location":"Amd/ryzen 5/5600h · revision 1721 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-77e4d302a63aa1c5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-714-r1721"],"url":"https://museum.vlsi.kr/objects/cw-77e4d302a63aa1c5"},{"id":"cw-78001513f5f4e3b0","name":"Cortex-X3","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":null,"aliases":["Arm holdings microarchitectures cortex-x3"],"fields":[{"key":"Architecture name","value":"Cortex-X3","unit":"","sourceId":"chipswiki-301-r614","location":"Arm holdings/microarchitectures/cortex-x3 · revision 614 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-78001513f5f4e3b0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x3&oldid=614","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-301-r614","location":"Arm holdings/microarchitectures/cortex-x3 · revision 614 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-78001513f5f4e3b0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x3&oldid=614","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-301-r614","location":"Arm holdings/microarchitectures/cortex-x3 · revision 614 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-78001513f5f4e3b0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x3&oldid=614","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-X2","unit":"","sourceId":"chipswiki-301-r614","location":"Arm holdings/microarchitectures/cortex-x3 · revision 614 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-78001513f5f4e3b0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x3&oldid=614","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Hunter-ELP","unit":"","sourceId":"chipswiki-301-r614","location":"Arm holdings/microarchitectures/cortex-x3 · revision 614 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-78001513f5f4e3b0","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x3&oldid=614","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-301-r614"],"url":"https://museum.vlsi.kr/objects/cw-78001513f5f4e3b0"},{"id":"cw-78026914e3224b38","name":"EyeQ6","kind":"sku","entityType":"product-model","subtype":"sku","company":"Mobileye","year":2022,"aliases":["Mobileye eyeq eyeq6"],"fields":[{"key":"Model name","value":"EyeQ6","unit":"","sourceId":"chipswiki-2941-r9848","location":"Mobileye/eyeq/eyeq6 · revision 9848 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-78026914e3224b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq6&oldid=9848","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Mobileye","unit":"","sourceId":"chipswiki-2941-r9848","location":"Mobileye/eyeq/eyeq6 · revision 9848 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-78026914e3224b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq6&oldid=9848","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Automotive","unit":"","sourceId":"chipswiki-2941-r9848","location":"Mobileye/eyeq/eyeq6 · revision 9848 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-78026914e3224b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq6&oldid=9848","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 9, 2018","unit":"","sourceId":"chipswiki-2941-r9848","location":"Mobileye/eyeq/eyeq6 · revision 9848 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-78026914e3224b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq6&oldid=9848","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"2022/3","unit":"","sourceId":"chipswiki-2941-r9848","location":"Mobileye/eyeq/eyeq6 · revision 9848 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-78026914e3224b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq6&oldid=9848","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EyeQ","unit":"","sourceId":"chipswiki-2941-r9848","location":"Mobileye/eyeq/eyeq6 · revision 9848 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-78026914e3224b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq6&oldid=9848","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2941-r9848","location":"Mobileye/eyeq/eyeq6 · revision 9848 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-29. Not an independent measurement.","entityId":"cw-78026914e3224b38","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mobileye%2Feyeq%2Feyeq6&oldid=9848","sourceDate":"2019-04-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2941-r9848"],"url":"https://museum.vlsi.kr/objects/cw-78026914e3224b38"},{"id":"cw-782523c8453a05bd","name":"Core i3-9000","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-9000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i3 i3-9000"],"fields":[{"key":"Model name","value":"Core i3-9000","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-9000","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3XN","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-9000","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake R","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-5263-r17220","location":"Intel/core i3/i3-9000 · revision 17220 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-782523c8453a05bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-9000&oldid=17220","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5263-r17220"],"url":"https://museum.vlsi.kr/objects/cw-782523c8453a05bd"},{"id":"cw-783930cd92628a85","name":"Core i5-6585R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6585r"],"fields":[{"key":"Model name","value":"Core i5-6585R","unit":"","sourceId":"chipswiki-7915-r25453","location":"Intel/core i5/i5-6585r · revision 25453 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-783930cd92628a85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6585r&oldid=25453","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6585R","unit":"","sourceId":"chipswiki-7915-r25453","location":"Intel/core i5/i5-6585r · revision 25453 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-783930cd92628a85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6585r&oldid=25453","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7915-r25453","location":"Intel/core i5/i5-6585r · revision 25453 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-783930cd92628a85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6585r&oldid=25453","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 22, 2016","unit":"","sourceId":"chipswiki-7915-r25453","location":"Intel/core i5/i5-6585r · revision 25453 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-783930cd92628a85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6585r&oldid=25453","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7915-r25453","location":"Intel/core i5/i5-6585r · revision 25453 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-783930cd92628a85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6585r&oldid=25453","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7915-r25453","location":"Intel/core i5/i5-6585r · revision 25453 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-783930cd92628a85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6585r&oldid=25453","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7915-r25453","location":"Intel/core i5/i5-6585r · revision 25453 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-783930cd92628a85","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6585r&oldid=25453","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7915-r25453","location":"Intel/core i5/i5-6585r · revision 25453 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-786be0e17b8acf05","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2640m&oldid=25396","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7892-r25396","location":"Intel/core i7/i7-2640m · revision 25396 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"2 MT/s","unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8648-r26847","location":"Amd/am186/ic80186-3 · revision 26847 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-789412896d76ff4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8648-r26847"],"url":"https://museum.vlsi.kr/objects/cw-789412896d76ff4d"},{"id":"cw-7894c392a629546e","name":"Core i5-8650K","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":null,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i5 i5-8650k"],"fields":[{"key":"Model name","value":"Core i5-8650K","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8650K","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4962-r16056","location":"Intel/core i5/i5-8650k · revision 16056 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-7894c392a629546e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8650k&oldid=16056","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4962-r16056"],"url":"https://museum.vlsi.kr/objects/cw-7894c392a629546e"},{"id":"cw-78c1d15c5fa47888","name":"Athlon 240GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"200","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd athlon 240ge"],"fields":[{"key":"Model name","value":"Athlon 240GE","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"240GE","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD240GC6M2OFB","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 6, 2018","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 21, 2018","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":200,"unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-2537-r8749","location":"Amd/athlon/240ge · revision 8749 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-78c1d15c5fa47888","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2537-r8749","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-78c1d15c5fa47888"},{"id":"cw-78d6e99f962c9904","name":"CN5860-1000 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5860-1000bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN5860-1000 SCP","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5860-1000 SCP","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5860-1000BG1521-SCP","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x16 KiB","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8123-r25782","location":"Cavium/octeon plus/cn5860-1000bg1521-scp · revision 25782 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-scp&oldid=25782","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-78d6e99f962c9904","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8123-r25782","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-78d6e99f962c9904"},{"id":"cw-790af5ec1afda4f7","name":"Storm","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AppliedMicro","year":2011,"process":"40 nm","aliases":["Apm microarchitectures storm"],"fields":[{"key":"Architecture name","value":"Storm","unit":"","sourceId":"chipswiki-4744-r15309","location":"Apm/microarchitectures/storm · revision 15309 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-790af5ec1afda4f7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fstorm&oldid=15309","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AppliedMicro","unit":"","sourceId":"chipswiki-4744-r15309","location":"Apm/microarchitectures/storm · revision 15309 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-790af5ec1afda4f7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fstorm&oldid=15309","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4744-r15309","location":"Apm/microarchitectures/storm · revision 15309 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-790af5ec1afda4f7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fstorm&oldid=15309","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2011,"unit":"","sourceId":"chipswiki-4744-r15309","location":"Apm/microarchitectures/storm · revision 15309 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-790af5ec1afda4f7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fstorm&oldid=15309","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-4744-r15309","location":"Apm/microarchitectures/storm · revision 15309 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-790af5ec1afda4f7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fstorm&oldid=15309","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":8,"unit":"","sourceId":"chipswiki-4744-r15309","location":"Apm/microarchitectures/storm · revision 15309 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-790af5ec1afda4f7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fstorm&oldid=15309","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-4744-r15309","location":"Apm/microarchitectures/storm · revision 15309 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-790af5ec1afda4f7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fstorm&oldid=15309","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4744-r15309","location":"Apm/microarchitectures/storm · revision 15309 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-790af5ec1afda4f7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fstorm&oldid=15309","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Shadowcat","unit":"","sourceId":"chipswiki-4744-r15309","location":"Apm/microarchitectures/storm · revision 15309 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-26. Not an independent measurement.","entityId":"cw-790af5ec1afda4f7","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Apm%2Fmicroarchitectures%2Fstorm&oldid=15309","sourceDate":"2018-09-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4744-r15309"],"url":"https://museum.vlsi.kr/objects/cw-790af5ec1afda4f7"},{"id":"cw-790bf589cd5d5adf","name":"Duron 950 (Morgan)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhd950amt1b"],"fields":[{"key":"Model name","value":"Duron 950","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 950","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHD950AMT1B","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 12, 2001","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 12, 2001","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":950,"unit":"MHz","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":44.4,"unit":"W","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8420-r26128","location":"Amd/duron/dhd950amt1b · revision 26128 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-790bf589cd5d5adf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8420-r26128"],"url":"https://museum.vlsi.kr/objects/cw-790bf589cd5d5adf"},{"id":"cw-792075bec4452fd8","name":"P8086-2","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 p8086-2"],"fields":[{"key":"Model name","value":"AMD P8086-2","unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P8086-2","unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"P8086-2","unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P8086","unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PDIP-40","unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PDIP","unit":"","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8493-r26686","location":"Amd/am8086/p8086-2 · revision 26686 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-792075bec4452fd8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086-2&oldid=26686","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8493-r26686"],"url":"https://museum.vlsi.kr/objects/cw-792075bec4452fd8"},{"id":"cw-7921608d5bb2b065","name":"Dimensity 800","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","year":2020,"architecture":"Cortex-A76","process":"7 nm","aliases":["Mediatek dimensity 800"],"fields":[{"key":"Model name","value":"Dimensity 800","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":800,"unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2020","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2020","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Dimensity","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2-A","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A76","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A76","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-4266","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":17.07,"unit":"GiB/s","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G57","unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":4,"unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-832-r2147","location":"Mediatek/dimensity/800 · revision 2147 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-31. Not an independent measurement.","entityId":"cw-7921608d5bb2b065","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fdimensity%2F800&oldid=2147","sourceDate":"2021-01-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-832-r2147"],"url":"https://museum.vlsi.kr/objects/cw-7921608d5bb2b065"},{"id":"cw-793b5e2f3077d10b","name":"Mobile Pentium II 333","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":1999,"architecture":"P6","process":"250 nm","aliases":["Intel mobile pentium ii 333"],"fields":[{"key":"Model name","value":"Mobile Pentium II 333","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":333,"unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PMF33302001AA","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KP80524KX333256","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KC80524KX333256","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1998,"unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 25, 1999","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Mobile Pentium II","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL3HK","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL32S","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL32P","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL3KG","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"P6","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Dixon","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdpA0","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdbA0","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdxA0","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":27400000,"unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":180,"unit":"mm²","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":11.8,"unit":"W","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"240-pin connector","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7803-r25242","location":"Intel/mobile pentium ii/333 · revision 25242 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-793b5e2f3077d10b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7803-r25242"],"url":"https://museum.vlsi.kr/objects/cw-793b5e2f3077d10b"},{"id":"cw-794777da343b6f19","name":"Alpha 21264","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"DEC","year":1998,"process":"0.35 µm","aliases":["Dec microarchitectures alpha 21264"],"fields":[{"key":"Architecture name","value":"Alpha 21264","unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"DEC","unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"DEC","unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / manufacturer 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 3","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"manufacturer 3","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"February, 1998","unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.35,"unit":"µm","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU pipeline stages","value":6,"unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / stages","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4-way","unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Alpha","unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Alpha 21164","unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Alpha 21364","unit":"","sourceId":"chipswiki-15454-r48629","location":"Dec/microarchitectures/alpha 21264 · revision 48629 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-13. Not an independent measurement.","entityId":"cw-794777da343b6f19","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Dec%2Fmicroarchitectures%2Falpha%2021264&oldid=48629","sourceDate":"2017-06-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-15454-r48629"],"url":"https://museum.vlsi.kr/objects/cw-794777da343b6f19"},{"id":"cw-7954b74272255123","name":"Xeon Gold 5220S","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 5220s"],"fields":[{"key":"Model name","value":"Xeon Gold 5220S","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5220S","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5200,"unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1519-r4971","location":"Intel/xeon gold/5220s · revision 4971 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7954b74272255123","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1519-r4971"],"url":"https://museum.vlsi.kr/objects/cw-7954b74272255123"},{"id":"cw-795ffa983759b688","name":"Celeron G4930T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel celeron g4930t"],"fields":[{"key":"Model name","value":"Celeron G4930T","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4930T","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403379313","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3YQ","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. 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Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":88,"unit":"°C","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 610","unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-2854-r9581","location":"Intel/celeron/g4930t · revision 9581 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-795ffa983759b688","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4930t&oldid=9581","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2854-r9581"],"url":"https://museum.vlsi.kr/objects/cw-795ffa983759b688"},{"id":"cw-796d2fe04c15e9b7","name":"EPYC Embedded 3255","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":null,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc embedded 3255"],"fields":[{"key":"Model name","value":"EPYC Embedded 3255","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3255,"unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PE3255BGR88AF","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC Embedded","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Snowy Owl","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":55,"unit":"W","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":"-40 °C","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8 × 64 KiB","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8 × 32 KiB","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8 × 512 KiB","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2 × 8 MiB","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. 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Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. 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Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3255&oldid=877","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-407-r877","location":"Amd/epyc embedded/3255 · revision 877 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. 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Not an independent measurement.","entityId":"cw-796d2fe04c15e9b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":45,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. 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Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1262-r4096","location":"Intel/xeon gold/6246r · revision 4096 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-797a87a61cf3e302","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246r&oldid=4096","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1262-r4096"],"url":"https://museum.vlsi.kr/objects/cw-797a87a61cf3e302"},{"id":"cw-797fd57a12e3a554","name":"Celeron B810E","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron b810e"],"fields":[{"key":"Model name","value":"Celeron B810E","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0BT","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-797fd57a12e3a554","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6927-r21613","location":"Intel/celeron/b810e · revision 21613 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402569700","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DN","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 9, 2015","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 9, 2015","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"V2","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3727-r11426","location":"Intel/xeon d/d-1518 · revision 11426 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-79a36c8cd2f3cb75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3727-r11426"],"url":"https://museum.vlsi.kr/objects/cw-79a36c8cd2f3cb75"},{"id":"cw-79d43b1000b2085d","name":"R-Car H3 (SiP)","kind":"sku","entityType":"product-model","subtype":"soc","company":"Renesas","series":"3rd Gen","year":2018,"architecture":"Cortex-A53","process":"16 nm","aliases":["Renesas r-car h3 (sip)"],"fields":[{"key":"Model name","value":"R-Car H3 (SiP)","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Renesas","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"H3 (SiP)","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"R8J77950","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 2, 2015","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2018","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"R-Car","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"3rd Gen","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A57","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":111.36,"unit":"mm²","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":9,"unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.8,"unit":"V","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":352,"unit":"KiB","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x48+5x32 KiB","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":288,"unit":"KiB","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"9x32 KiB","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-3200","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR GX6650","unit":"","sourceId":"chipswiki-7649-r24909","location":"Renesas/r-car/h3 (sip) · revision 24909 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Renesas%2Fr-car%2Fh3%20(sip)&oldid=24909","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1255","unit":"","sourceId":"chipswiki-31420-r92284","location":"Template:Packages/renesas/fcbga-1255 · revision 92284 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31420-r92284","location":"Template:Packages/renesas/fcbga-1255 · revision 92284 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1255,"unit":"","sourceId":"chipswiki-31420-r92284","location":"Template:Packages/renesas/fcbga-1255 · revision 92284 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31420-r92284","location":"Template:Packages/renesas/fcbga-1255 · revision 92284 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42.5,"unit":"mm","sourceId":"chipswiki-31420-r92284","location":"Template:Packages/renesas/fcbga-1255 · revision 92284 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":42.5,"unit":"mm","sourceId":"chipswiki-31420-r92284","location":"Template:Packages/renesas/fcbga-1255 · revision 92284 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d43b1000b2085d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Frenesas%2Ffcbga-1255&oldid=92284","sourceDate":"2017-07-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7649-r24909","chipswiki-31420-r92284"],"url":"https://museum.vlsi.kr/objects/cw-79d43b1000b2085d"},{"id":"cw-79d69c73595e12b8","name":"CG80186-3","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 cg80186-3"],"fields":[{"key":"Model name","value":"CG80186-3","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CG80186-3","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CG80186-3","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CG80186-3B","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"2 MT/s","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-79d69c73595e12b8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8651-r26850","location":"Amd/am186/cg80186-3 · revision 26850 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6025","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2003","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 2003","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM7","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM7TDMI","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FBGA-208","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FBGA","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":0,"unit":"KiB","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-79e3e95009c6c21a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6025&oldid=24935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-7669-r24935","location":"Qualcomm/msm6xxx/msm6025 · revision 24935 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4116T","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303645400","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3MQ","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x1 MiB","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-272-r547","location":"Intel/xeon silver/4116t · revision 547 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-03. Not an independent measurement.","entityId":"cw-79ec05c64534411a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4116t&oldid=547","sourceDate":"2022-08-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-272-r547"],"url":"https://museum.vlsi.kr/objects/cw-79ec05c64534411a"},{"id":"cw-7a04f51cbe8b9df8","name":"Celeron J3355","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"J Series","year":2016,"architecture":"Goldmont","process":"14 nm","aliases":["Intel celeron j3355"],"fields":[{"key":"Model name","value":"Celeron J3355","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"J3355","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066802986000","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 30, 2016","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"J Series","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2500,"unit":"MHz","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2Z8","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Apollo Lake","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":10,"unit":"W","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-1296","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1296","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-6285-r19523","location":"Intel/celeron/j3355 · revision 19523 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-09. Not an independent measurement.","entityId":"cw-7a04f51cbe8b9df8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","sourceDate":"2018-05-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6285-r19523"],"url":"https://museum.vlsi.kr/objects/cw-7a04f51cbe8b9df8"},{"id":"cw-7a0a26d984e6f1cd","name":"Helio X27 (MT6797X)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio X","year":2016,"architecture":"Cortex-A53","process":"20 nm","aliases":["Mediatek helio mt6797x"],"fields":[{"key":"Model name","value":"MediaTek Helio X27","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Helio X27","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6797X","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MTK6797X","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 2, 2016","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 2, 2016","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio X","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2600,"unit":"MHz","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":1600,"unit":"MHz","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A72","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":20,"unit":"nm","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1600","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T880","unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":4,"unit":"","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":875,"unit":"MHz","sourceId":"chipswiki-3802-r11852","location":"Mediatek/helio/mt6797x · revision 11852 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-15. Not an independent measurement.","entityId":"cw-7a0a26d984e6f1cd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797x&oldid=11852","sourceDate":"2019-03-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3802-r11852"],"url":"https://museum.vlsi.kr/objects/cw-7a0a26d984e6f1cd"},{"id":"cw-7a30ac1c9f6ed6d5","name":"Ryzen 3 3300U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 3 3300u"],"fields":[{"key":"Model name","value":"Ryzen 3 3300U","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3300U","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM3300C4T4MFG","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2019","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","alternatives":[{"value":"32 GiB","sourceId":"chipswiki-1406-r4746","reason":"Amd/ryzen 3/3300u · revision 4746 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-1406-r4746","location":"Amd/ryzen 3/3300u · revision 4746 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-01-07. Not an independent measurement.","entityId":"cw-7a30ac1c9f6ed6d5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","sourceDate":"2020-01-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1406-r4746"],"url":"https://museum.vlsi.kr/objects/cw-7a30ac1c9f6ed6d5"},{"id":"cw-7a597196f21afa0e","name":"Xeon D-1602","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1600","year":2019,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1602"],"fields":[{"key":"Model name","value":"Xeon D-1602","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1602","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1600","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Hewitt Lake","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":27,"unit":"W","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3688-r11019","location":"Intel/xeon d/d-1602 · revision 11019 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7a597196f21afa0e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1602&oldid=11019","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3688-r11019"],"url":"https://museum.vlsi.kr/objects/cw-7a597196f21afa0e"},{"id":"cw-7a85bdf2de71d942","name":"EPYC Embedded 3201","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc embedded 3201"],"fields":[{"key":"Model name","value":"EPYC Embedded 3201","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3201,"unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PE3201BHR88AF","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC Embedded","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Snowy Owl","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":30,"unit":"W","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8 × 64 KiB","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8 × 32 KiB","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8 × 512 KiB","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2 × 8 MiB","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"34.13 GB/s","unit":"","sourceId":"chipswiki-409-r879","location":"Amd/epyc embedded/3201 · revision 879 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3201&oldid=879","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SP4r2","unit":"","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OBGA","unit":"","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":45,"unit":"mm","sourceId":"chipswiki-31098-r91557","location":"Template:Packages/amd/package sp4r2 · revision 91557 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-7a85bdf2de71d942","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-409-r879","chipswiki-31098-r91557"],"url":"https://museum.vlsi.kr/objects/cw-7a85bdf2de71d942"},{"id":"cw-7aa0c356ff387837","name":"Core i5-450M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-400","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i5 i5-450m"],"fields":[{"key":"Model name","value":"Intel Core i5-450M","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-450M","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004119AI","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004119AI","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2010","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2010","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-400","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2399.99,"unit":"MHz","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2666.66,"unit":"MHz","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBTZ","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBTY","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7942-r25489","location":"Intel/core i5/i5-450m · revision 25489 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-450m&oldid=25489","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA-988A","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aa0c356ff387837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CU-40KC\\W","unit":"","sourceId":"chipswiki-14679-r44740","location":"Amd/am186cx/am186cu-40kc\\w · revision 44740 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14679-r44740","location":"Amd/am186cx/am186cu-40kc\\w · revision 44740 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14679-r44740","location":"Amd/am186cx/am186cu-40kc\\w · revision 44740 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14679-r44740","location":"Amd/am186cx/am186cu-40kc\\w · revision 44740 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14679-r44740","location":"Amd/am186cx/am186cu-40kc\\w · revision 44740 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14679-r44740","location":"Amd/am186cx/am186cu-40kc\\w · revision 44740 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14679-r44740","location":"Amd/am186cx/am186cu-40kc\\w · revision 44740 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14679-r44740","location":"Amd/am186cx/am186cu-40kc\\w · revision 44740 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14679-r44740","location":"Amd/am186cx/am186cu-40kc\\w · revision 44740 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14679-r44740","location":"Amd/am186cx/am186cu-40kc\\w · revision 44740 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14679-r44740","location":"Amd/am186cx/am186cu-40kc\\w · revision 44740 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14679-r44740","location":"Amd/am186cx/am186cu-40kc\\w · revision 44740 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7aa575a500f3b95a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14679-r44740"],"url":"https://museum.vlsi.kr/objects/cw-7aa575a500f3b95a"},{"id":"cw-7aab3381659e1c40","name":"Core i5-7287U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-7200","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-7287u"],"fields":[{"key":"Model name","value":"Core i5-7287U","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7287U","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR360","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7200","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7908-r25444","location":"Intel/core i5/i5-7287u · revision 25444 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aab3381659e1c40","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7287u&oldid=25444","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFBJ","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5200,"unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A0","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L0","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L1","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":125,"unit":"W","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1520-r4972","location":"Intel/xeon gold/5220 · revision 4972 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-7aadefcf39022545","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1520-r4972"],"url":"https://museum.vlsi.kr/objects/cw-7aadefcf39022545"},{"id":"cw-7ab2de06454fcc16","name":"Core i5-6300HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6300hq"],"fields":[{"key":"Model name","value":"Core i5-6300HQ","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-6300HQ","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066202194632","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2FP","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-6000","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-7ab2de06454fcc16","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6300hq&oldid=12655","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3968-r12655","location":"Intel/core i5/i5-6300hq · revision 12655 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-7add7489e75fb9ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-390m&oldid=25568","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC25","unit":"","sourceId":"chipswiki-7989-r25568","location":"Intel/core i3/i3-390m · revision 25568 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7add7489e75fb9ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-390m&oldid=25568","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7989-r25568","location":"Intel/core i3/i3-390m · revision 25568 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7add7489e75fb9ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-390m&oldid=25568","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7989-r25568","location":"Intel/core i3/i3-390m · revision 25568 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7add7489e75fb9ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-390m&oldid=25568","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7989-r25568","location":"Intel/core i3/i3-390m · revision 25568 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":251,"unit":"mm²","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8391-r26087","location":"Amd/k5/amd-ssa-5-75abr · revision 26087 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b1a442db9c28f91","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-ssa-5-75abr&oldid=26087","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8391-r26087"],"url":"https://museum.vlsi.kr/objects/cw-7b1a442db9c28f91"},{"id":"cw-7b57195b4498c4a6","name":"Hunter-ELP","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":2023,"aliases":["Arm holdings microarchitectures hunter-elp"],"fields":[{"key":"Architecture name","value":"Hunter-ELP","unit":"","sourceId":"chipswiki-300-r612","location":"Arm holdings/microarchitectures/hunter-elp · revision 612 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-7b57195b4498c4a6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter-elp&oldid=612","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-300-r612","location":"Arm holdings/microarchitectures/hunter-elp · revision 612 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-7b57195b4498c4a6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter-elp&oldid=612","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-300-r612","location":"Arm holdings/microarchitectures/hunter-elp · revision 612 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-7b57195b4498c4a6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter-elp&oldid=612","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2023,"unit":"","sourceId":"chipswiki-300-r612","location":"Arm holdings/microarchitectures/hunter-elp · revision 612 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-7b57195b4498c4a6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter-elp&oldid=612","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-X3","unit":"","sourceId":"chipswiki-300-r612","location":"Arm holdings/microarchitectures/hunter-elp · revision 612 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-7b57195b4498c4a6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter-elp&oldid=612","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Chaberton-ELP","unit":"","sourceId":"chipswiki-300-r612","location":"Arm holdings/microarchitectures/hunter-elp · revision 612 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-7b57195b4498c4a6","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fhunter-elp&oldid=612","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-300-r612"],"url":"https://museum.vlsi.kr/objects/cw-7b57195b4498c4a6"},{"id":"cw-7b6a79f45f0cec53","name":"Atom x5-E3930","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3900","year":2017,"architecture":"Goldmont","process":"14 nm","aliases":["Intel atom x5 x5-e3930"],"fields":[{"key":"Model name","value":"Intel Atom x5-E3930","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"x5-E3930","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 26, 2016","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2017,"unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom x5","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3900","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":1800,"unit":"MHz","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Goldmont","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Apollo Lake","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Apollo Lake","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6.5,"unit":"W","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":"-40 °C","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":110,"unit":"°C","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-1296","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1296","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-1653-r5735","location":"Intel/atom x5/x5-e3930 · revision 5735 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-24. Not an independent measurement.","entityId":"cw-7b6a79f45f0cec53","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","sourceDate":"2019-10-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1653-r5735"],"url":"https://museum.vlsi.kr/objects/cw-7b6a79f45f0cec53"},{"id":"cw-7b7ae5d5c464a4ea","name":"Xeon D-1612","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1600","year":2019,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1612"],"fields":[{"key":"Model name","value":"Xeon D-1612","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1612","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8068204236701","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRG06","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1600","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2500,"unit":"MHz","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Hewitt Lake","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":22,"unit":"W","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3689-r11021","location":"Intel/xeon d/d-1612 · revision 11021 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-06. Not an independent measurement.","entityId":"cw-7b7ae5d5c464a4ea","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1612&oldid=11021","sourceDate":"2019-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3689-r11021"],"url":"https://museum.vlsi.kr/objects/cw-7b7ae5d5c464a4ea"},{"id":"cw-7b7e2f0fd4c73410","name":"Atom 330","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"200","year":2008,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom 330"],"fields":[{"key":"Model name","value":"Atom 330","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":330,"unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AU80587RE0251M","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLG9Y","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2008","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 21, 2008","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":200,"unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1599.99,"unit":"MHz","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"533.33 MT/s","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Nettop 2008","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Calistoga","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Diamondville","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":112,"unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":94424414,"unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":51.9276,"unit":"mm²","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":8,"unit":"W","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":112,"unit":"KiB","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8074-r25725","location":"Intel/atom/330 · revision 25725 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2F330&oldid=25725","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-437","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":437,"unit":"","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":22,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31502-r92564","location":"Template:Packages/intel/fcbga-437 · revision 92564 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7b7e2f0fd4c73410","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-437&oldid=92564","sourceDate":"2017-04-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8074-r25725","chipswiki-31502-r92564"],"url":"https://museum.vlsi.kr/objects/cw-7b7e2f0fd4c73410"},{"id":"cw-7b9e86f76307ec4d","name":"Exynos 5410","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 5","year":2013,"architecture":"Cortex-A15","process":"28 nm","aliases":["Samsung exynos 5410"],"fields":[{"key":"Model name","value":"Exynos 5410","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5410,"unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 2013","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 2013","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 5","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1600,"unit":"MHz","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1200,"unit":"MHz","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A15","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A15","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A7","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6848-r21340","location":"Samsung/exynos/5410 · revision 21340 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-7b9e86f76307ec4d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6848-r21340"],"url":"https://museum.vlsi.kr/objects/cw-7b9e86f76307ec4d"},{"id":"cw-7bae571f6a597900","name":"Core i3-6006U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-6000","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i3 i3-6006u"],"fields":[{"key":"Model name","value":"Core i3-6006U","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6006U","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066201931106","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FJ8066202498906","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2UW","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2JG","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 10, 2016","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 10, 2016","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake U","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K1","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-3959-r12646","location":"Intel/core i3/i3-6006u · revision 12646 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-7bae571f6a597900","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3959-r12646","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-7bae571f6a597900"},{"id":"cw-7bb0be157ba0e435","name":"CN5840-900 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN58xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5840-900bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN5840-900 EXP","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5840-900 EXP","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5840-900BG1521-EXP","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Network","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":900,"unit":"MHz","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x16 KiB","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8140-r25799","location":"Cavium/octeon plus/cn5840-900bg1521-exp · revision 25799 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5840-900bg1521-exp&oldid=25799","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7bb0be157ba0e435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8140-r25799","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-7bb0be157ba0e435"},{"id":"cw-7bd7949b58e4f6ad","name":"K6-2E+/450APZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2e+-450apz"],"fields":[{"key":"Model name","value":"K6-2E+/450APZ","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E+/450APZ","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E+/450APZ","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":450,"unit":"MHz","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":12,"unit":"W","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.7,"unit":"V","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Embedded","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1006-r2857","location":"Amd/k6-2+/k6-2e+-450apz · revision 2857 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":321,"unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":2.54,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.3,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super Socket 7","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-7bd7949b58e4f6ad","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1006-r2857","chipswiki-31126-r91598"],"url":"https://museum.vlsi.kr/objects/cw-7bd7949b58e4f6ad"},{"id":"cw-7c219d937a51951b","name":"MR80186-6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am186","year":1984,"architecture":"80186","process":"1.5 µm","aliases":["Amd am186 mr80186-6"],"fields":[{"key":"Model name","value":"MR80186-6","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MR80186-6","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MR80186-6","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":6,"unit":"MHz","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"1.5 MT/s","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8633-r26832","location":"Amd/am186/mr80186-6 · revision 26832 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c219d937a51951b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8633-r26832"],"url":"https://museum.vlsi.kr/objects/cw-7c219d937a51951b"},{"id":"cw-7c3a2ee340d862b4","name":"Xeon E3-1578L v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1500 v5","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1578l v5"],"fields":[{"key":"Model name","value":"Xeon E3-1578L v5","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1578L v5","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2TT","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 31, 2016","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 31, 2016","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1500 v5","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"N0","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Pro Graphics P580","unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":72,"unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-7753-r25135","location":"Intel/xeon e3/e3-1578l v5 · revision 25135 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1578l%20v5&oldid=25135","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7c3a2ee340d862b4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7753-r25135","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-7c3a2ee340d862b4"},{"id":"cw-7c7d88ae7b176539","name":"Helio P20 (MT6757)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio P","year":2016,"architecture":"Cortex-A53","process":"16 nm","aliases":["Mediatek helio mt6757"],"fields":[{"key":"Model name","value":"Helio P20","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P20","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6757","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MTK6757","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 22, 2016","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2016","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio P","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":6,"unit":"GiB","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3200","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":23.84,"unit":"GiB/s","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T880","unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":900,"unit":"MHz","sourceId":"chipswiki-2211-r7484","location":"Mediatek/helio/mt6757 · revision 7484 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-23. Not an independent measurement.","entityId":"cw-7c7d88ae7b176539","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6757&oldid=7484","sourceDate":"2019-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2211-r7484"],"url":"https://museum.vlsi.kr/objects/cw-7c7d88ae7b176539"},{"id":"cw-7cb092528bf660e9","name":"Ryzen 9 5980HS","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 9 5980hs"],"fields":[{"key":"Model name","value":"Ryzen 9 5980HS","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5980HS","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000474","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 9","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4800,"unit":"MHz","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2100,"unit":"MHz","sourceId":"chipswiki-723-r1733","location":"Amd/ryzen 9/5980hs · revision 1733 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-31. Not an independent measurement.","entityId":"cw-7cb092528bf660e9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","sourceDate":"2021-05-31","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-723-r1733"],"url":"https://museum.vlsi.kr/objects/cw-7cb092528bf660e9"},{"id":"cw-7ccff1fffeee6ccf","name":"AMD-K5-PR133ABR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5k86","year":1996,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr133abr"],"fields":[{"key":"Model name","value":"AMD-K5-PR133ABR","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR133ABR","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR133ABR","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 7, 1996","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 7, 1996","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"5k86","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":99.99,"unit":"MHz","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.666 MT/s","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5k86","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":181,"unit":"mm²","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8399-r26095","location":"Amd/k5/amd-k5-pr133abr · revision 26095 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ccff1fffeee6ccf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr133abr&oldid=26095","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8399-r26095"],"url":"https://museum.vlsi.kr/objects/cw-7ccff1fffeee6ccf"},{"id":"cw-7cd38fde97e4eb18","name":"Willow Cove","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2020,"process":"10 nm","aliases":["Intel microarchitectures willow cove"],"fields":[{"key":"Architecture name","value":"Willow Cove","unit":"","sourceId":"chipswiki-195-r394","location":"Intel/microarchitectures/willow cove · revision 394 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-17. Not an independent measurement.","entityId":"cw-7cd38fde97e4eb18","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwillow%20cove&oldid=394","sourceDate":"2022-09-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-195-r394","location":"Intel/microarchitectures/willow cove · revision 394 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-17. Not an independent measurement.","entityId":"cw-7cd38fde97e4eb18","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwillow%20cove&oldid=394","sourceDate":"2022-09-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-195-r394","location":"Intel/microarchitectures/willow cove · revision 394 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-17. Not an independent measurement.","entityId":"cw-7cd38fde97e4eb18","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwillow%20cove&oldid=394","sourceDate":"2022-09-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2020,"unit":"","sourceId":"chipswiki-195-r394","location":"Intel/microarchitectures/willow cove · revision 394 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-17. Not an independent measurement.","entityId":"cw-7cd38fde97e4eb18","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwillow%20cove&oldid=394","sourceDate":"2022-09-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-195-r394","location":"Intel/microarchitectures/willow cove · revision 394 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-17. Not an independent measurement.","entityId":"cw-7cd38fde97e4eb18","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwillow%20cove&oldid=394","sourceDate":"2022-09-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-195-r394","location":"Intel/microarchitectures/willow cove · revision 394 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-17. Not an independent measurement.","entityId":"cw-7cd38fde97e4eb18","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwillow%20cove&oldid=394","sourceDate":"2022-09-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"5-way","unit":"","sourceId":"chipswiki-195-r394","location":"Intel/microarchitectures/willow cove · revision 394 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-17. Not an independent measurement.","entityId":"cw-7cd38fde97e4eb18","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwillow%20cove&oldid=394","sourceDate":"2022-09-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-195-r394","location":"Intel/microarchitectures/willow cove · revision 394 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-17. Not an independent measurement.","entityId":"cw-7cd38fde97e4eb18","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwillow%20cove&oldid=394","sourceDate":"2022-09-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Tiger Lake","unit":"","sourceId":"chipswiki-195-r394","location":"Intel/microarchitectures/willow cove · revision 394 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-17. Not an independent measurement.","entityId":"cw-7cd38fde97e4eb18","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwillow%20cove&oldid=394","sourceDate":"2022-09-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Sunny Cove","unit":"","sourceId":"chipswiki-195-r394","location":"Intel/microarchitectures/willow cove · revision 394 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-17. Not an independent measurement.","entityId":"cw-7cd38fde97e4eb18","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwillow%20cove&oldid=394","sourceDate":"2022-09-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Golden Cove","unit":"","sourceId":"chipswiki-195-r394","location":"Intel/microarchitectures/willow cove · revision 394 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-09-17. Not an independent measurement.","entityId":"cw-7cd38fde97e4eb18","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fwillow%20cove&oldid=394","sourceDate":"2022-09-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-195-r394"],"url":"https://museum.vlsi.kr/objects/cw-7cd38fde97e4eb18"},{"id":"cw-7cdc5cd7db57ef75","name":"CN3840-600 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3840-600bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN3840-600 SCP","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3840-600 SCP","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3840-600BG1521-SCP","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x8 KiB","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8212-r25871","location":"Cavium/octeon/cn3840-600bg1521-scp · revision 25871 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7cdc5cd7db57ef75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8212-r25871","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-7cdc5cd7db57ef75"},{"id":"cw-7d08291dd1990d9d","name":"Helio X30 (MT6799)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio X","year":2017,"architecture":"Cortex-A53","process":"10 nm","aliases":["Mediatek helio mt6799"],"fields":[{"key":"Model name","value":"MediaTek Helio X30","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Helio X30","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6799","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 26, 2016","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 27, 2017","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio X","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2500,"unit":"MHz","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2200,"unit":"MHz","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":1900,"unit":"MHz","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A35","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A73","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3732","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"PowerVR GT7400 Plus","unit":"","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":800,"unit":"MHz","sourceId":"chipswiki-4170-r13344","location":"Mediatek/helio/mt6799 · revision 13344 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-29. Not an independent measurement.","entityId":"cw-7d08291dd1990d9d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6799&oldid=13344","sourceDate":"2018-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4170-r13344"],"url":"https://museum.vlsi.kr/objects/cw-7d08291dd1990d9d"},{"id":"cw-7d26bfbf636c5632","name":"AMD-K5-PR120ABQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5k86","year":1996,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr120abq"],"fields":[{"key":"Model name","value":"AMD-K5-PR120ABQ","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR120ABQ","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR120ABQ","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 7, 1996","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 7, 1996","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"5k86","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":90,"unit":"MHz","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"60 MT/s","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"5k86","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":181,"unit":"mm²","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"SPGA","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8402-r26098","location":"Amd/k5/amd-k5-pr120abq · revision 26098 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7d26bfbf636c5632","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr120abq&oldid=26098","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8402-r26098"],"url":"https://museum.vlsi.kr/objects/cw-7d26bfbf636c5632"},{"id":"cw-7dbcba43397abd3a","name":"Alchemy Au1550-500MBD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2004,"architecture":"Au1","aliases":["Alchemy au1550-500mbd"],"fields":[{"key":"Model name","value":"Alchemy Au1550-500MBD","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1550-500MBD","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1550-500MBDAA","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2004","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2004","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"AA","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":192,"unit":"MiB","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1440 mW","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-166","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.333 GB/s","unit":"","sourceId":"chipswiki-460-r941","location":"Alchemy/au1550-500mbd · revision 941 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-17. Not an independent measurement.","entityId":"cw-7dbcba43397abd3a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","sourceDate":"2022-03-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-460-r941"],"url":"https://museum.vlsi.kr/objects/cw-7dbcba43397abd3a"},{"id":"cw-7dcbaff4ad013d66","name":"Snapdragon 670","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","year":2018,"architecture":"Cortex-A75","process":"10 nm","aliases":["Qualcomm snapdragon 600 670"],"fields":[{"key":"Model name","value":"Snapdragon 670","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"SDM670","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 8, 2018","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 8, 2018","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 600","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2200,"unit":"MHz","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1700,"unit":"MHz","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A75","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 360 Gold","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 360 Silver","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 615","unit":"","sourceId":"chipswiki-2829-r9257","location":"Qualcomm/snapdragon 600/670 · revision 9257 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-08. Not an independent measurement.","entityId":"cw-7dcbaff4ad013d66","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F670&oldid=9257","sourceDate":"2019-05-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2829-r9257"],"url":"https://museum.vlsi.kr/objects/cw-7dcbaff4ad013d66"},{"id":"cw-7deadd3e0e23c455","name":"80286","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":null,"process":"1.5 µm","aliases":["Intel microarchitectures 80286"],"fields":[{"key":"Architecture name","value":80286,"unit":"","sourceId":"chipswiki-8775-r27274","location":"Intel/microarchitectures/80286 · revision 27274 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-7deadd3e0e23c455","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80286&oldid=27274","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8775-r27274","location":"Intel/microarchitectures/80286 · revision 27274 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-7deadd3e0e23c455","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80286&oldid=27274","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8775-r27274","location":"Intel/microarchitectures/80286 · revision 27274 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-7deadd3e0e23c455","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80286&oldid=27274","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8775-r27274","location":"Intel/microarchitectures/80286 · revision 27274 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-7deadd3e0e23c455","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80286&oldid=27274","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-16","unit":"","sourceId":"chipswiki-8775-r27274","location":"Intel/microarchitectures/80286 · revision 27274 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-7deadd3e0e23c455","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80286&oldid=27274","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":8086,"unit":"","sourceId":"chipswiki-8775-r27274","location":"Intel/microarchitectures/80286 · revision 27274 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-7deadd3e0e23c455","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80286&oldid=27274","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":80186,"unit":"","sourceId":"chipswiki-8775-r27274","location":"Intel/microarchitectures/80286 · revision 27274 · {{microarchitecture}} / predecessor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"predecessor 2","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-7deadd3e0e23c455","scope":"predecessor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80286&oldid=27274","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":80386,"unit":"","sourceId":"chipswiki-8775-r27274","location":"Intel/microarchitectures/80286 · revision 27274 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-11-30. Not an independent measurement.","entityId":"cw-7deadd3e0e23c455","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2F80286&oldid=27274","sourceDate":"2017-11-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8775-r27274"],"url":"https://museum.vlsi.kr/objects/cw-7deadd3e0e23c455"},{"id":"cw-7e20aacf3eb83e2f","name":"Am186ER–50VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–50vc\\w"],"fields":[{"key":"Model name","value":"Am186ER–50VC\\W","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–50VC\\W","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–50VC\\W","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 31, 1998","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"12.5 MT/s","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e20aacf3eb83e2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14634-r44695","location":"Amd/am186ex/am186er–50vc\\w · revision 44695 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Phytium","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"FT-1500A/4","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 26, 2015","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 26, 2016","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"FeiTeng","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"FT-1500A","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Earth","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Xiaomi FTC660","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":0.9,"unit":"V","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"fcBGA-1150","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"fcBGA","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1150","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-3764-r11686","location":"Phytium/feiteng/ft-1500a-4 · revision 11686 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-26. Not an independent measurement.","entityId":"cw-7e380f2f2441f773","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Phytium%2Ffeiteng%2Fft-1500a-4&oldid=11686","sourceDate":"2019-03-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3764-r11686"],"url":"https://museum.vlsi.kr/objects/cw-7e380f2f2441f773"},{"id":"cw-7e38c926ecee6006","name":"Ryzen 3 PRO 2200GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 3 pro 2200ge"],"fields":[{"key":"Model name","value":"Ryzen 3 PRO 2200GE","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 2200GE","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD220BC6FBMPK","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 10, 2018","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 10, 2018","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-1244-r3996","location":"Amd/ryzen 3/pro 2200ge · revision 3996 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202200ge&oldid=3996","sourceDate":"2020-03-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-08. Not an independent measurement.","entityId":"cw-7e38c926ecee6006","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1244-r3996","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-7e38c926ecee6006"},{"id":"cw-7e829f1e6693ed86","name":"Xeon E-2186G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E-2000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel xeon e e-2186g"],"fields":[{"key":"Model name","value":"Xeon E-2186G","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2186G","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403379918","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3WR","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 12, 2018","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 12, 2018","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2000","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4700,"unit":"MHz","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake E","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":95,"unit":"W","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. 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Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. 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Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics P630","unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-3027-r10094","location":"Intel/xeon e/e-2186g · revision 10094 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-25. Not an independent measurement.","entityId":"cw-7e829f1e6693ed86","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","sourceDate":"2019-04-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3027-r10094"],"url":"https://museum.vlsi.kr/objects/cw-7e829f1e6693ed86"},{"id":"cw-7e95da6f85461d5a","name":"EPYC 7532","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7532"],"fields":[{"key":"Model name","value":"EPYC 7532","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7532,"unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000136","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000136WOF","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 19, 2020","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 19, 2020","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":200,"unit":"W","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32 × 32 KiB","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32 × 512 KiB","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16 × 16 MiB","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-276-r560","location":"Amd/epyc/7532 · revision 560 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-26. Not an independent measurement.","entityId":"cw-7e95da6f85461d5a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","sourceDate":"2022-07-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-276-r560"],"url":"https://museum.vlsi.kr/objects/cw-7e95da6f85461d5a"},{"id":"cw-7e9f3b106610df11","name":"Am186CH-25KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186CH","year":1998,"architecture":"80186","process":"350 nm","aliases":["Amd am186cx am186ch-25ki\\w"],"fields":[{"key":"Model name","value":"Am186CU-25KI\\W","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186CU-25KI\\W","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186CU-25KI\\W","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1998,"unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CH","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14685-r44746","location":"Amd/am186cx/am186ch-25ki\\w · revision 44746 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7e9f3b106610df11","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14685-r44746"],"url":"https://museum.vlsi.kr/objects/cw-7e9f3b106610df11"},{"id":"cw-7ee7d9b4c78535ed","name":"Am186ER–40KC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1996,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–40kc\\w"],"fields":[{"key":"Model name","value":"Am186ER–40KC\\W","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–40KC\\W","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–40KC\\W","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 1996","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1996","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"10 MT/s","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14640-r44701","location":"Amd/am186ex/am186er–40kc\\w · revision 44701 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-7ee7d9b4c78535ed","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14640-r44701"],"url":"https://museum.vlsi.kr/objects/cw-7ee7d9b4c78535ed"},{"id":"cw-7f7618556c200613","name":"Loihi 2","kind":"sku","entityType":"product-model","subtype":"sku","company":"Intel","year":2021,"process":"Intel 4","aliases":["Intel loihi 2"],"fields":[{"key":"Model name","value":"Loihi 2","unit":"","sourceId":"chipswiki-10-r96927","location":"Intel/loihi 2 · revision 96927 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-28. Not an independent measurement.","entityId":"cw-7f7618556c200613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi%202&oldid=96927","sourceDate":"2022-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-10-r96927","location":"Intel/loihi 2 · revision 96927 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-28. Not an independent measurement.","entityId":"cw-7f7618556c200613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi%202&oldid=96927","sourceDate":"2022-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-10-r96927","location":"Intel/loihi 2 · revision 96927 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-28. Not an independent measurement.","entityId":"cw-7f7618556c200613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi%202&oldid=96927","sourceDate":"2022-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Artificial Intelligence","unit":"","sourceId":"chipswiki-10-r96927","location":"Intel/loihi 2 · revision 96927 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-28. Not an independent measurement.","entityId":"cw-7f7618556c200613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi%202&oldid=96927","sourceDate":"2022-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 30, 2021","unit":"","sourceId":"chipswiki-10-r96927","location":"Intel/loihi 2 · revision 96927 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-28. Not an independent measurement.","entityId":"cw-7f7618556c200613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi%202&oldid=96927","sourceDate":"2022-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 30, 2021","unit":"","sourceId":"chipswiki-10-r96927","location":"Intel/loihi 2 · revision 96927 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-28. Not an independent measurement.","entityId":"cw-7f7618556c200613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi%202&oldid=96927","sourceDate":"2022-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"Intel 4","unit":"","sourceId":"chipswiki-10-r96927","location":"Intel/loihi 2 · revision 96927 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-28. Not an independent measurement.","entityId":"cw-7f7618556c200613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi%202&oldid=96927","sourceDate":"2022-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2300000000,"unit":"","sourceId":"chipswiki-10-r96927","location":"Intel/loihi 2 · revision 96927 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-28. Not an independent measurement.","entityId":"cw-7f7618556c200613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi%202&oldid=96927","sourceDate":"2022-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-10-r96927","location":"Intel/loihi 2 · revision 96927 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-28. Not an independent measurement.","entityId":"cw-7f7618556c200613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi%202&oldid=96927","sourceDate":"2022-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":31,"unit":"mm²","sourceId":"chipswiki-10-r96927","location":"Intel/loihi 2 · revision 96927 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-28. Not an independent measurement.","entityId":"cw-7f7618556c200613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi%202&oldid=96927","sourceDate":"2022-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":16384,"unit":"","sourceId":"chipswiki-10-r96927","location":"Intel/loihi 2 · revision 96927 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-11-28. Not an independent measurement.","entityId":"cw-7f7618556c200613","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Floihi%202&oldid=96927","sourceDate":"2022-11-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-10-r96927"],"url":"https://museum.vlsi.kr/objects/cw-7f7618556c200613"},{"id":"cw-7f7d9e00e579777d","name":"P6","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":1995,"process":"350 nm","aliases":["Intel microarchitectures p6"],"fields":[{"key":"Architecture name","value":"P6","unit":"","sourceId":"chipswiki-1276-r4197","location":"Intel/microarchitectures/p6 · revision 4197 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-23. Not an independent measurement.","entityId":"cw-7f7d9e00e579777d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp6&oldid=4197","sourceDate":"2020-02-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1276-r4197","location":"Intel/microarchitectures/p6 · revision 4197 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-23. Not an independent measurement.","entityId":"cw-7f7d9e00e579777d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp6&oldid=4197","sourceDate":"2020-02-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1276-r4197","location":"Intel/microarchitectures/p6 · revision 4197 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-23. Not an independent measurement.","entityId":"cw-7f7d9e00e579777d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp6&oldid=4197","sourceDate":"2020-02-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"October, 1995","unit":"","sourceId":"chipswiki-1276-r4197","location":"Intel/microarchitectures/p6 · revision 4197 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-23. Not an independent measurement.","entityId":"cw-7f7d9e00e579777d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp6&oldid=4197","sourceDate":"2020-02-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-1276-r4197","location":"Intel/microarchitectures/p6 · revision 4197 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-23. Not an independent measurement.","entityId":"cw-7f7d9e00e579777d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp6&oldid=4197","sourceDate":"2020-02-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-1276-r4197","location":"Intel/microarchitectures/p6 · revision 4197 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-02-23. Not an independent measurement.","entityId":"cw-7f7d9e00e579777d","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp6&oldid=4197","sourceDate":"2020-02-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-1276-r4197","location":"Intel/microarchitectures/p6 · revision 4197 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-23. Not an independent measurement.","entityId":"cw-7f7d9e00e579777d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp6&oldid=4197","sourceDate":"2020-02-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"P5","unit":"","sourceId":"chipswiki-1276-r4197","location":"Intel/microarchitectures/p6 · revision 4197 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-23. Not an independent measurement.","entityId":"cw-7f7d9e00e579777d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp6&oldid=4197","sourceDate":"2020-02-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"NetBurst","unit":"","sourceId":"chipswiki-1276-r4197","location":"Intel/microarchitectures/p6 · revision 4197 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-23. Not an independent measurement.","entityId":"cw-7f7d9e00e579777d","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp6&oldid=4197","sourceDate":"2020-02-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Pentium M","unit":"","sourceId":"chipswiki-1276-r4197","location":"Intel/microarchitectures/p6 · revision 4197 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2020-02-23. Not an independent measurement.","entityId":"cw-7f7d9e00e579777d","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fp6&oldid=4197","sourceDate":"2020-02-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1276-r4197"],"url":"https://museum.vlsi.kr/objects/cw-7f7d9e00e579777d"},{"id":"cw-7f7e6a774baa47f8","name":"Ryzen 7 PRO 2700","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000","year":2018,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 7 pro 2700"],"fields":[{"key":"Model name","value":"Ryzen 7 PRO 2700","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 2700","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD270BBBM88AF","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 6, 2018","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 6, 2018","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Pinnacle Ridge","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x64 KiB","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x8 MiB","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-4914-r15851","location":"Amd/ryzen 7/pro 2700 · revision 15851 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","sourceDate":"2018-09-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-09-06. Not an independent measurement.","entityId":"cw-7f7e6a774baa47f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4914-r15851","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-7f7e6a774baa47f8"},{"id":"cw-7f8406a7b08a3492","name":"POWER9 02CY228","kind":"sku","entityType":"product-model","subtype":"cpu","company":"IBM","series":"POWER9","year":2017,"architecture":"POWER9","process":"14 nm","aliases":["Ibm power 02cy228"],"fields":[{"key":"Model name","value":"02CY228","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"IBM","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"02CY228","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"02CY228","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2017","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November, 2017","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"POWER","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"POWER9","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.7,"unit":"GHz","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3.8,"unit":"GHz","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v3.0B","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"POWER9","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sforza","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8000000000,"unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":693.37,"unit":"mm²","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":80,"unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":190,"unit":"W","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":85,"unit":"°C","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5,"unit":"MiB","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x512 KiB","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":100,"unit":"MiB","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x10 MiB","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":158.95,"unit":"GiB/s","sourceId":"chipswiki-3948-r12593","location":"Ibm/power/02cy228 · revision 12593 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-17. Not an independent measurement.","entityId":"cw-7f8406a7b08a3492","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ibm%2Fpower%2F02cy228&oldid=12593","sourceDate":"2019-01-17","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3948-r12593"],"url":"https://museum.vlsi.kr/objects/cw-7f8406a7b08a3492"},{"id":"cw-7f9fc5d4c6f03423","name":"Am2035","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Ambric","series":"Gen 1","year":2007,"architecture":"Ambric","process":"130 nm","aliases":["Ambric am2000 am2035"],"fields":[{"key":"Model name","value":"Am2035","unit":"","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Ambric","unit":"","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am2035","unit":"","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am2035","unit":"","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 10, 2006","unit":"","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2007","unit":"","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am2000","unit":"","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Gen 1","unit":"","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ambric","unit":"","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":280,"unit":"","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8664-r26863","location":"Ambric/am2000/am2035 · revision 26863 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7f9fc5d4c6f03423","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8664-r26863"],"url":"https://museum.vlsi.kr/objects/cw-7f9fc5d4c6f03423"},{"id":"cw-7faf1eaca130e138","name":"Pentium G4400TE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel pentium (2009) g4400te"],"fields":[{"key":"Model name","value":"Pentium G4400TE","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4400TE","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201938702","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LT","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 9, 2015","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-7787-r25222","location":"Intel/pentium (2009)/g4400te · revision 25222 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7faf1eaca130e138","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4400te&oldid=25222","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7787-r25222"],"url":"https://museum.vlsi.kr/objects/cw-7faf1eaca130e138"},{"id":"cw-7fc13ac395f10c75","name":"Core i7-3920XM Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-3000","year":2012,"architecture":"Ivy Bridge","process":"22 nm","aliases":["Intel core i7ee i7-3920xm"],"fields":[{"key":"Model name","value":"Core i7-3920XM Extreme Edition","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-3920XM","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AW8063801009606","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0MH","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0T2","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2012","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 28, 2012","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-3000","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ivy Bridge","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Panther Point","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ivy Bridge","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"E1","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":55,"unit":"W","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-7fc13ac395f10c75","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-3920xm&oldid=11899","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3808-r11899","location":"Intel/core i7ee/i7-3920xm · revision 11899 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-7fd8e9916617019b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4830&oldid=25070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7700-r25070","location":"Intel/xeon e7/e7-4830 · revision 25070 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7fd8e9916617019b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4830&oldid=25070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-4800","unit":"","sourceId":"chipswiki-7700-r25070","location":"Intel/xeon e7/e7-4830 · revision 25070 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7fd8e9916617019b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4830&oldid=25070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2133.33,"unit":"MHz","sourceId":"chipswiki-7700-r25070","location":"Intel/xeon e7/e7-4830 · revision 25070 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7fd8e9916617019b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4830&oldid=25070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-7700-r25070","location":"Intel/xeon e7/e7-4830 · revision 25070 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7fd8e9916617019b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4830&oldid=25070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7700-r25070","location":"Intel/xeon e7/e7-4830 · revision 25070 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7fd8e9916617019b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4830&oldid=25070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7700-r25070","location":"Intel/xeon e7/e7-4830 · revision 25070 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7fd8e9916617019b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4830&oldid=25070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7700-r25070","location":"Intel/xeon e7/e7-4830 · revision 25070 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7fd8e9916617019b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4830&oldid=25070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7700-r25070","location":"Intel/xeon e7/e7-4830 · revision 25070 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7fd8e9916617019b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4830&oldid=25070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7700-r25070","location":"Intel/xeon e7/e7-4830 · revision 25070 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7fd8e9916617019b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4830&oldid=25070","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-7700-r25070","location":"Intel/xeon e7/e7-4830 · revision 25070 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-7fd8e9916617019b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Flga-1567&oldid=92962","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7700-r25070","chipswiki-31576-r92962"],"url":"https://museum.vlsi.kr/objects/cw-7fd8e9916617019b"},{"id":"cw-7fe4b6dcf92624f8","name":"Embedded G-Series T52R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"G-Series APU/CPU","year":2011,"architecture":"Bobcat","process":"40 nm","aliases":["Amd embedded t52r"],"fields":[{"key":"Model name","value":"Embedded G-Series T52R","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"T52R","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GET52RGBB12GVE","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 19, 2011","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Embedded G-Series","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G-Series APU/CPU","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bobcat","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"eBrazos","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":20,"unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":40,"unit":"nm","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":451000000,"unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":75,"unit":"mm²","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 32 KiB","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 32 KiB","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1 × 512 KiB","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"10.67 GB/s","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon HD 6310","unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-416-r888","location":"Amd/embedded/t52r · revision 888 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","sourceDate":"2022-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FT1","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":413,"unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.8-1.0 mm","unit":"","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.92,"unit":"mm","sourceId":"chipswiki-31122-r91589","location":"Template:Packages/amd/FT1 · revision 91589 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-04. Not an independent measurement.","entityId":"cw-7fe4b6dcf92624f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FFT1&oldid=91589","sourceDate":"2020-09-05","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-416-r888","chipswiki-31122-r91589"],"url":"https://museum.vlsi.kr/objects/cw-7fe4b6dcf92624f8"},{"id":"cw-7fea35e2aa36f155","name":"KaiXian KX-5540","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Zhaoxin","series":"KX-5000","year":2017,"architecture":"WuDaoKou","process":"28 nm","aliases":["Zhaoxin kaixian kx-5540"],"fields":[{"key":"Model name","value":"KaiXian KX-5540","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Zhaoxin","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"HLMC","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"KX-5540","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KX-5540","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"December 28, 2017","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"KaiXian","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"KX-5000","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"WuDaoKou","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2100000000,"unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":187,"unit":"mm²","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"32-way set associative","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5652-r18550","location":"Zhaoxin/kaixian/kx-5540 · revision 18550 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-7fea35e2aa36f155","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5652-r18550"],"url":"https://museum.vlsi.kr/objects/cw-7fea35e2aa36f155"},{"id":"cw-7ff3956efabda4e4","name":"Am486DX2-66","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2","year":1993,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486dx2-66"],"fields":[{"key":"Model name","value":"Am486DX2-66","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-66","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-66","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 1993","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 1993","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":66,"unit":"MHz","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8567-r26765","location":"Amd/am486/am486dx2-66 · revision 26765 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-7ff3956efabda4e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8567-r26765"],"url":"https://museum.vlsi.kr/objects/cw-7ff3956efabda4e4"},{"id":"cw-801ae876b7b89a5e","name":"Xeon Platinum 8176F","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon platinum 8176f"],"fields":[{"key":"Model name","value":"Xeon Platinum 8176F","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"8176F","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8000,"unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":56,"unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1469-r4916","location":"Intel/xeon platinum/8176f · revision 4916 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-801ae876b7b89a5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8176f&oldid=4916","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1469-r4916"],"url":"https://museum.vlsi.kr/objects/cw-801ae876b7b89a5e"},{"id":"cw-801f5a6ee4cc27be","name":"EPYC 7302P","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7302p"],"fields":[{"key":"Model name","value":"EPYC 7302P","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7302P","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000049","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000049WOF","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":155,"unit":"W","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x512 KiB","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x16 MiB","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-857-r2237","location":"Amd/epyc/7302p · revision 2237 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-801f5a6ee4cc27be","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7302p&oldid=2237","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-857-r2237"],"url":"https://museum.vlsi.kr/objects/cw-801f5a6ee4cc27be"},{"id":"cw-803ba432cc125438","name":"Xeon Silver 4114","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon silver 4114"],"fields":[{"key":"Model name","value":"Xeon Silver 4114","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4114,"unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806734114","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303561800","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3GK","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":85,"unit":"W","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":10,"unit":"MiB","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x1 MiB","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":13.75,"unit":"MiB","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x1.375 MiB","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1449-r4893","location":"Intel/xeon silver/4114 · revision 4893 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-803ba432cc125438","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4114&oldid=4893","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1449-r4893"],"url":"https://museum.vlsi.kr/objects/cw-803ba432cc125438"},{"id":"cw-804cdd79d1591e21","name":"EPYC 7763","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7003","year":2021,"architecture":"Zen 3","process":"7 nm+","aliases":["Amd epyc 7763"],"fields":[{"key":"Model name","value":"EPYC 7763","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7763,"unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000312","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000312WOF","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 12, 2021","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 15, 2021","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7003,"unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2450,"unit":"MHz","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Milan","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":"7 nm+","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":64,"unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":128,"unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":280,"unit":"W","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":4,"unit":"MiB","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":2,"unit":"MiB","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"64 × 32 KiB","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":2,"unit":"MiB","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"64 × 32 KiB","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"64 × 512 KiB","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":256,"unit":"MiB","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8 × 32 MiB","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.73,"unit":"GiB/s","sourceId":"chipswiki-44-r96984","location":"Amd/epyc/7763 · revision 96984 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-10-27. Not an independent measurement.","entityId":"cw-804cdd79d1591e21","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","sourceDate":"2022-10-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-44-r96984"],"url":"https://museum.vlsi.kr/objects/cw-804cdd79d1591e21"},{"id":"cw-805599b77244b092","name":"Celeron U3400","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P3000","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel celeron u3400"],"fields":[{"key":"Model name","value":"Intel Celeron U3400","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"U3400","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617006039AA","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 24, 2010","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 24, 2010","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P3000","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1066.66,"unit":"MHz","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBUE","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-800","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-8023-r25605","location":"Intel/celeron/u3400 · revision 25605 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-805599b77244b092","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8023-r25605","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-805599b77244b092"},{"id":"cw-8076c372420ba72a","name":"Xeon D-1539","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1539"],"fields":[{"key":"Model name","value":"Xeon D-1539","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1539","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402569000","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DH","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 2016","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 2016","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2200,"unit":"MHz","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"V2","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-3742-r11451","location":"Intel/xeon d/d-1539 · revision 11451 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-8076c372420ba72a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3742-r11451"],"url":"https://museum.vlsi.kr/objects/cw-8076c372420ba72a"},{"id":"cw-807e92fa47588f7f","name":"TMS1099C","kind":"sku","entityType":"product-model","subtype":"sku","company":"Texas Instruments","year":null,"architecture":"TMS1000","process":"8 µm","aliases":["Ti tms1000 tms1099c"],"fields":[{"key":"Model name","value":"TMS1099","unit":"","sourceId":"chipswiki-602-r1403","location":"Ti/tms1000/tms1099c · revision 1403 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-19. 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Not an independent measurement.","entityId":"cw-807e92fa47588f7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099c&oldid=1403","sourceDate":"2021-09-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"TMS1000","unit":"","sourceId":"chipswiki-602-r1403","location":"Ti/tms1000/tms1099c · revision 1403 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-19. Not an independent measurement.","entityId":"cw-807e92fa47588f7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099c&oldid=1403","sourceDate":"2021-09-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":8,"unit":"µm","sourceId":"chipswiki-602-r1403","location":"Ti/tms1000/tms1099c · revision 1403 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-19. Not an independent measurement.","entityId":"cw-807e92fa47588f7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099c&oldid=1403","sourceDate":"2021-09-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":4,"unit":"bit","sourceId":"chipswiki-602-r1403","location":"Ti/tms1000/tms1099c · revision 1403 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-19. Not an independent measurement.","entityId":"cw-807e92fa47588f7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099c&oldid=1403","sourceDate":"2021-09-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"KiB","sourceId":"chipswiki-602-r1403","location":"Ti/tms1000/tms1099c · revision 1403 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-19. Not an independent measurement.","entityId":"cw-807e92fa47588f7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099c&oldid=1403","sourceDate":"2021-09-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":15,"unit":"V","sourceId":"chipswiki-602-r1403","location":"Ti/tms1000/tms1099c · revision 1403 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-19. Not an independent measurement.","entityId":"cw-807e92fa47588f7f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1099c&oldid=1403","sourceDate":"2021-09-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 1","value":"PDIP-64","unit":"","sourceId":"chipswiki-31332-r92062","location":"Template:Packages/pdip-64 · revision 92062 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2021-09-19. Not an independent measurement.","entityId":"cw-807e92fa47588f7f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpdip-64&oldid=92062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 1","value":"PDIP","unit":"","sourceId":"chipswiki-31332-r92062","location":"Template:Packages/pdip-64 · revision 92062 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2021-09-19. Not an independent measurement.","entityId":"cw-807e92fa47588f7f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpdip-64&oldid=92062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 1","value":64,"unit":"","sourceId":"chipswiki-31332-r92062","location":"Template:Packages/pdip-64 · revision 92062 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2021-09-19. Not an independent measurement.","entityId":"cw-807e92fa47588f7f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fpdip-64&oldid=92062","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"CDIP-64","unit":"","sourceId":"chipswiki-31333-r92063","location":"Template:Packages/cdip-64 · revision 92063 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-09-19. Not an independent measurement.","entityId":"cw-807e92fa47588f7f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcdip-64&oldid=92063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"CDIP","unit":"","sourceId":"chipswiki-31333-r92063","location":"Template:Packages/cdip-64 · revision 92063 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-09-19. Not an independent measurement.","entityId":"cw-807e92fa47588f7f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcdip-64&oldid=92063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":64,"unit":"","sourceId":"chipswiki-31333-r92063","location":"Template:Packages/cdip-64 · revision 92063 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-09-19. Not an independent measurement.","entityId":"cw-807e92fa47588f7f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcdip-64&oldid=92063","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-602-r1403","chipswiki-31332-r92062","chipswiki-31333-r92063"],"url":"https://museum.vlsi.kr/objects/cw-807e92fa47588f7f"},{"id":"cw-8085e045e2bf4171","name":"Core i7-4860EQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2014,"architecture":"Haswell","process":"22 nm","aliases":["Intel core i7 i7-4860eq"],"fields":[{"key":"Model name","value":"Intel Core i7-4860EQ","unit":"","sourceId":"chipswiki-7866-r25369","location":"Intel/core i7/i7-4860eq · revision 25369 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8085e045e2bf4171","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860eq&oldid=25369","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7866-r25369","location":"Intel/core i7/i7-4860eq · revision 25369 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8085e045e2bf4171","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860eq&oldid=25369","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7866-r25369","location":"Intel/core i7/i7-4860eq · revision 25369 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8085e045e2bf4171","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860eq&oldid=25369","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-4860EQ","unit":"","sourceId":"chipswiki-7866-r25369","location":"Intel/core i7/i7-4860eq · revision 25369 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8085e045e2bf4171","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860eq&oldid=25369","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7866-r25369","location":"Intel/core i7/i7-4860eq · revision 25369 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8085e045e2bf4171","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860eq&oldid=25369","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7866-r25369","location":"Intel/core i7/i7-4860eq · revision 25369 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8085e045e2bf4171","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4860eq&oldid=25369","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7866-r25369","location":"Intel/core i7/i7-4860eq · revision 25369 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8094588d30d092b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350m&oldid=25589","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8008-r25589","location":"Intel/core i3/i3-2350m · revision 25589 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8094588d30d092b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350m&oldid=25589","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8008-r25589","location":"Intel/core i3/i3-2350m · revision 25589 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8094588d30d092b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350m&oldid=25589","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8008-r25589","location":"Intel/core i3/i3-2350m · revision 25589 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8094588d30d092b5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2350m&oldid=25589","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8008-r25589","location":"Intel/core i3/i3-2350m · revision 25589 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":55.63,"unit":"GiB/s","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics","unit":"","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":64,"unit":"","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-1240-r3950","location":"Intel/core i5/i5-1030g7 · revision 3950 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-18. Not an independent measurement.","entityId":"cw-809ebcfb55458b5e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-1030g7&oldid=3950","sourceDate":"2020-03-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1240-r3950"],"url":"https://museum.vlsi.kr/objects/cw-809ebcfb55458b5e"},{"id":"cw-80bcd5f1b5113de4","name":"Celeron G3950","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"G3900","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel celeron g3950"],"fields":[{"key":"Model name","value":"Celeron G3950","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G3950","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80677G3950","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35J","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"G3900","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake S","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"S0","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 610","unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-6432-r20114","location":"Intel/celeron/g3950 · revision 20114 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-80bcd5f1b5113de4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6432-r20114"],"url":"https://museum.vlsi.kr/objects/cw-80bcd5f1b5113de4"},{"id":"cw-80bf1e68e0eeb377","name":"Kirin 980","kind":"sku","entityType":"product-model","subtype":"soc","company":"HiSilicon","year":2018,"architecture":"Cortex-A76","process":"7 nm","aliases":["Hisilicon kirin 980"],"fields":[{"key":"Model name","value":"Kirin 980","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":980,"unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 31, 2018","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 31, 2018","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Kirin","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2600,"unit":"MHz","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1920,"unit":"MHz","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":1800,"unit":"MHz","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A76","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A76","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":6900000000,"unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":74.13,"unit":"mm²","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":512,"unit":"KiB","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"4x64 KiB","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":2,"unit":"MiB","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"4x512 KiB","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":256,"unit":"KiB","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":128,"unit":"KiB","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"4x32 KiB","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":512,"unit":"KiB","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"4x128 KiB","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-4266","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G76","unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":10,"unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":720,"unit":"MHz","sourceId":"chipswiki-4-r96916","location":"Hisilicon/kirin/980 · revision 96916 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-12-10. Not an independent measurement.","entityId":"cw-80bf1e68e0eeb377","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F980&oldid=96916","sourceDate":"2022-12-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4-r96916"],"url":"https://museum.vlsi.kr/objects/cw-80bf1e68e0eeb377"},{"id":"cw-812bed30f48a38fb","name":"Core i7-2670QM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-2000","year":2011,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel core i7 i7-2670qm"],"fields":[{"key":"Model name","value":"Core i7-2670QM","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-2670QM","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701065500","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR02N","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 4, 2011","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-2000","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3100,"unit":"MHz","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D2","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1160000000,"unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":216,"unit":"mm²","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-7884-r25388","location":"Intel/core i7/i7-2670qm · revision 25388 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2670qm&oldid=25388","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-812bed30f48a38fb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7884-r25388","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-812bed30f48a38fb"},{"id":"cw-8166a0f4e2ac25eb","name":"Exynos 5433","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 7","year":2014,"architecture":"Cortex-A57","process":"20 nm","aliases":["Samsung exynos 5433"],"fields":[{"key":"Model name","value":"Exynos 5433","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5433,"unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 7, 2014","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 7, 2014","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 7","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1900,"unit":"MHz","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1300,"unit":"MHz","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":2340,"unit":"MHz","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 4","value":1101,"unit":"MHz","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / frequency 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 4","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"Multiple clock domains; raw parameter frequency 4","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A57","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A57","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":20,"unit":"nm","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":113,"unit":"mm²","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. Not an independent measurement.","entityId":"cw-8166a0f4e2ac25eb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5433&oldid=984","sourceDate":"2022-03-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-492-r984","location":"Samsung/exynos/5433 · revision 984 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-06. 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Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-4970-r16067","location":"Intel/core i5/i5-8400t · revision 16067 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-8172b5cbf14bd163","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8400t&oldid=16067","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4970-r16067"],"url":"https://museum.vlsi.kr/objects/cw-8172b5cbf14bd163"},{"id":"cw-818033ce0b7faaf5","name":"Cortex-X2","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Arm","year":null,"aliases":["Arm holdings microarchitectures cortex-x2"],"fields":[{"key":"Architecture name","value":"Cortex-X2","unit":"","sourceId":"chipswiki-302-r615","location":"Arm holdings/microarchitectures/cortex-x2 · revision 615 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-818033ce0b7faaf5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x2&oldid=615","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-302-r615","location":"Arm holdings/microarchitectures/cortex-x2 · revision 615 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-818033ce0b7faaf5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x2&oldid=615","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-302-r615","location":"Arm holdings/microarchitectures/cortex-x2 · revision 615 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-818033ce0b7faaf5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x2&oldid=615","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Cortex-X1","unit":"","sourceId":"chipswiki-302-r615","location":"Arm holdings/microarchitectures/cortex-x2 · revision 615 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-818033ce0b7faaf5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x2&oldid=615","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Cortex-X3","unit":"","sourceId":"chipswiki-302-r615","location":"Arm holdings/microarchitectures/cortex-x2 · revision 615 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-07-04. Not an independent measurement.","entityId":"cw-818033ce0b7faaf5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x2&oldid=615","sourceDate":"2022-07-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-302-r615"],"url":"https://museum.vlsi.kr/objects/cw-818033ce0b7faaf5"},{"id":"cw-81ad177fd1b86606","name":"Myriad 1 MA1133","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Movidius","series":"1","year":2011,"architecture":"LEON3","process":"65 nm","aliases":["Movidius myriad ma1133"],"fields":[{"key":"Model name","value":"Myriad 1 MA1133","unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Movidius","unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MA1133","unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September, 2010","unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2011","unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Myriad","unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":1,"unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":180,"unit":"MHz","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SPARC V8","unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"LEON3","unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"TSMC","unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":9,"unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":9,"unit":"","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-6968-r21747","location":"Movidius/myriad/ma1133 · revision 21747 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-81ad177fd1b86606","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1133&oldid=21747","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6968-r21747"],"url":"https://museum.vlsi.kr/objects/cw-81ad177fd1b86606"},{"id":"cw-81d92d487f739a2f","name":"Celeron B820","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron b820"],"fields":[{"key":"Model name","value":"Celeron B820","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B820","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700848602","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0HQ","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July, 2012","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July, 2012","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-6926-r21612","location":"Intel/celeron/b820 · revision 21612 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-81d92d487f739a2f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-1866","unit":"","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-3723-r11414","location":"Intel/xeon d/d-1523n · revision 11414 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-81de6b1eba73a045","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1523n&oldid=11414","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3723-r11414"],"url":"https://museum.vlsi.kr/objects/cw-81de6b1eba73a045"},{"id":"cw-81f102379ca5548b","name":"AM9080ADCB","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080adcb"],"fields":[{"key":"Model name","value":"AMD AM9080ADCB","unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080ADCB","unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.083,"unit":"MHz","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8468-r26661","location":"Amd/am9080/am9080adcb · revision 26661 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-81f102379ca5548b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8468-r26661"],"url":"https://museum.vlsi.kr/objects/cw-81f102379ca5548b"},{"id":"cw-8204c9930f4da69e","name":"Exynos 5422","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 5","year":2014,"architecture":"Cortex-A15","process":"32 nm","aliases":["Samsung exynos 5422"],"fields":[{"key":"Model name","value":"Exynos 5422","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":5422,"unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 26, 2014","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 26, 2014","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 5","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2100,"unit":"MHz","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1500,"unit":"MHz","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv7","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A15","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A15","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A7","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6850-r21344","location":"Samsung/exynos/5422 · revision 21344 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-29. Not an independent measurement.","entityId":"cw-8204c9930f4da69e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","sourceDate":"2018-03-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6850-r21344"],"url":"https://museum.vlsi.kr/objects/cw-8204c9930f4da69e"},{"id":"cw-82143fe096f29386","name":"AM9080A-4DC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-4dc"],"fields":[{"key":"Model name","value":"AMD AM9080A-4DC","unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-4DC","unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-4DC","unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":4,"unit":"MHz","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8473-r26666","location":"Amd/am9080/am9080a-4dc · revision 26666 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82143fe096f29386","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-4dc&oldid=26666","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8473-r26666"],"url":"https://museum.vlsi.kr/objects/cw-82143fe096f29386"},{"id":"cw-8216b8ed9c9a88b7","name":"Exynos 7420","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 7","year":2015,"architecture":"Cortex-A57","process":"14 nm","aliases":["Samsung exynos 7420"],"fields":[{"key":"Model name","value":"Exynos 7420","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7420,"unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April, 2015","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 2015","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 7","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2100,"unit":"MHz","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1500,"unit":"MHz","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A57","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A57","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":78.23,"unit":"mm²","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1289-r4300","location":"Samsung/exynos/7420 · revision 4300 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-15. Not an independent measurement.","entityId":"cw-8216b8ed9c9a88b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","sourceDate":"2020-02-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1289-r4300"],"url":"https://museum.vlsi.kr/objects/cw-8216b8ed9c9a88b7"},{"id":"cw-825db3f8e11e4eae","name":"Mobile Pentium II 266","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":1998,"architecture":"P6","process":"250 nm","aliases":["Intel mobile pentium ii 266"],"fields":[{"key":"Model name","value":"Mobile Pentium II 266","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":266,"unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"80523TX266512","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PMD26605001AA","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PMD26605002AB","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PME26605001AA","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1997","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 1998","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Mobile Pentium II","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266,"unit":"MHz","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL2KJ","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL2RR","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL2U9","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"P6","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Tonga","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":5,"unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdA0","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdB0","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdB0","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":7500000,"unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":10.3,"unit":"W","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"240-pin connector","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7807-r25246","location":"Intel/mobile pentium ii/266 · revision 25246 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-825db3f8e11e4eae","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7807-r25246"],"url":"https://museum.vlsi.kr/objects/cw-825db3f8e11e4eae"},{"id":"cw-82a301da04d06e2b","name":"AMD-K6-IIIE+/500ANZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-III+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-iii+ amd-k6-iiie+-500anz"],"fields":[{"key":"Model name","value":"AMD-K6-IIIE+/500ANZ","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6-IIIE+/500ANZ","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-IIIE+/500ANZ","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-III+","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-III+ Embedded","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":499.99,"unit":"MHz","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":3,"unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":21400000,"unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":14.5,"unit":"W","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8312-r26002","location":"Amd/k6-iii+/amd-k6-iiie+-500anz · revision 26002 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82a301da04d06e2b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-iii%2B%2Famd-k6-iiie%2B-500anz&oldid=26002","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8312-r26002"],"url":"https://museum.vlsi.kr/objects/cw-82a301da04d06e2b"},{"id":"cw-82a68c40b7ad57f4","name":"Am186ER–25KI\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ER","year":1996,"architecture":"80186","process":"350 nm","aliases":["Amd am186ex am186er–25ki\\w"],"fields":[{"key":"Model name","value":"Am186ER–25KI\\W","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186ER–25KI\\W","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186ER–25KI\\W","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 1996","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1996","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ER","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"6.25 MT/s","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14647-r44708","location":"Amd/am186ex/am186er–25ki\\w · revision 44708 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-82a68c40b7ad57f4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14647-r44708"],"url":"https://museum.vlsi.kr/objects/cw-82a68c40b7ad57f4"},{"id":"cw-82b436129340888a","name":"Helio P65","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio P","year":2019,"architecture":"Cortex-A75","process":"12 nm","aliases":["Mediatek helio p65"],"fields":[{"key":"Model name","value":"Helio P65","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P65","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 25, 2019","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 25, 2019","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio P","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2000,"unit":"MHz","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A75","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A75","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3600","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.41,"unit":"GiB/s","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G52","unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":2,"unit":"","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":820,"unit":"MHz","sourceId":"chipswiki-662-r1598","location":"Mediatek/helio/p65 · revision 1598 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-07-26. Not an independent measurement.","entityId":"cw-82b436129340888a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fp65&oldid=1598","sourceDate":"2021-07-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-662-r1598"],"url":"https://museum.vlsi.kr/objects/cw-82b436129340888a"},{"id":"cw-82df50945ae21318","name":"Xeon Gold 6144","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6100","year":2017,"architecture":"Skylake (server)","process":"14 nm","aliases":["Intel xeon gold 6144"],"fields":[{"key":"Model name","value":"Xeon Gold 6144","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6144,"unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303657302","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8067303843000","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3MB","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3TR","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"July 11, 2017","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6100,"unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3500,"unit":"MHz","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake SP","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":768,"unit":"GiB","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":8,"unit":"MiB","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x1 MiB","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1499-r4951","location":"Intel/xeon gold/6144 · revision 4951 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-82df50945ae21318","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6144&oldid=4951","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1499-r4951"],"url":"https://museum.vlsi.kr/objects/cw-82df50945ae21318"},{"id":"cw-82e18374c68a082c","name":"Myriad 1 MA1110","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Movidius","series":"1","year":2009,"architecture":"LEON3","process":"65 nm","aliases":["Movidius myriad ma1110"],"fields":[{"key":"Model name","value":"Myriad 1 MA1110","unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Movidius","unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MA1110","unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 15, 2009","unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2009","unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Myriad","unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":1,"unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":180,"unit":"MHz","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SPARC V8","unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"LEON3","unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"TSMC","unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":9,"unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":9,"unit":"","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-6969-r21749","location":"Movidius/myriad/ma1110 · revision 21749 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-11. Not an independent measurement.","entityId":"cw-82e18374c68a082c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Movidius%2Fmyriad%2Fma1110&oldid=21749","sourceDate":"2018-03-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6969-r21749"],"url":"https://museum.vlsi.kr/objects/cw-82e18374c68a082c"},{"id":"cw-82f5e928ed5952c2","name":"AMD-K6-2/300BNZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-300bnz"],"fields":[{"key":"Model name","value":"K6-2/300BNZ","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/300BNZ","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/300BNZ","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CBGA-360","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CBGA","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-360","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8377-r26072","location":"Amd/k6-2/k6-2-300bnz · revision 26072 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-82f5e928ed5952c2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300bnz&oldid=26072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8377-r26072"],"url":"https://museum.vlsi.kr/objects/cw-82f5e928ed5952c2"},{"id":"cw-82f64ce1d0174fac","name":"EPYC 7F32","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7f32"],"fields":[{"key":"Model name","value":"EPYC 7F32","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"7F32","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000139","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000139WOF","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 14, 2020","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 14, 2020","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":180,"unit":"W","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":128,"unit":"MiB","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x16 MiB","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-1194-r3736","location":"Amd/epyc/7f32 · revision 3736 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-15. Not an independent measurement.","entityId":"cw-82f64ce1d0174fac","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7f32&oldid=3736","sourceDate":"2020-04-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1194-r3736"],"url":"https://museum.vlsi.kr/objects/cw-82f64ce1d0174fac"},{"id":"cw-830426b3f1c7609f","name":"Core i7-8850H","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i7 i7-8850h"],"fields":[{"key":"Model name","value":"Core i7-8850H","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8850H","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8068403359725","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3YZ","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4300,"unit":"MHz","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake H","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":9,"unit":"MiB","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x1.5 MiB","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-4959-r16044","location":"Intel/core i7/i7-8850h · revision 16044 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8850h&oldid=16044","sourceDate":"2018-08-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-29. Not an independent measurement.","entityId":"cw-830426b3f1c7609f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4959-r16044","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-830426b3f1c7609f"},{"id":"cw-8305ec320208c322","name":"AMD-K6-2/266ANZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-266anz"],"fields":[{"key":"Model name","value":"K6-2/266ANZ","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/266ANZ","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/266ANZ","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266.66,"unit":"MHz","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8384-r26079","location":"Amd/k6-2/k6-2-266anz · revision 26079 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8305ec320208c322","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8384-r26079"],"url":"https://museum.vlsi.kr/objects/cw-8305ec320208c322"},{"id":"cw-833a5d5d7e358e1d","name":"N80L286-20","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N80L286","year":1989,"architecture":"80286","aliases":["Amd am286 n80l286-20"],"fields":[{"key":"Model name","value":"N80L286-20","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N80L286-20","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1989,"unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N80L286","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"20 MT/s","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PLCC-68","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PLCC","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PLCC-68","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8587-r26785","location":"Amd/am286/n80l286-20 · revision 26785 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-833a5d5d7e358e1d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8587-r26785"],"url":"https://museum.vlsi.kr/objects/cw-833a5d5d7e358e1d"},{"id":"cw-834b17f2a6531f9b","name":"Xeon Gold 6222V","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6222v"],"fields":[{"key":"Model name","value":"Xeon Gold 6222V","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":6222,"unit":"V","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":115,"unit":"W","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":27.5,"unit":"MiB","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x1.375 MiB","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1492-r4944","location":"Intel/xeon gold/6222v · revision 4944 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-834b17f2a6531f9b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6222v&oldid=4944","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1492-r4944"],"url":"https://museum.vlsi.kr/objects/cw-834b17f2a6531f9b"},{"id":"cw-8353b09bb1e2af39","name":"AM9080A-1DIB","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-1dib"],"fields":[{"key":"Model name","value":"AMD AM9080A-1DIB","unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-1DIB","unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-1DIB","unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Industrial","unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3.125,"unit":"MHz","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8486-r26679","location":"Amd/am9080/am9080a-1dib · revision 26679 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8353b09bb1e2af39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1dib&oldid=26679","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8486-r26679"],"url":"https://museum.vlsi.kr/objects/cw-8353b09bb1e2af39"},{"id":"cw-837240661829a090","name":"Ryzen Embedded R1606G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"R1000","year":2019,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen embedded r1606g"],"fields":[{"key":"Model name","value":"Ryzen Embedded R1606G","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"R1606G","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YE1606C4T2OFG","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 16, 2019","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 16, 2019","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"R1000","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Banded Kestrel","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-923-r2547","location":"Amd/ryzen embedded/r1606g · revision 2547 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. 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Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-837240661829a090","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-923-r2547","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-837240661829a090"},{"id":"cw-837d4110f346ced2","name":"Bonnell","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2008,"process":"45 nm","aliases":["Intel microarchitectures bonnell"],"fields":[{"key":"Architecture name","value":"Bonnell","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"March 2, 2008","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Core","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"Core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Diamondville","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Lincroft","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / core name 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 3","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"core name 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Pineview","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / core name 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 4","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"core name 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Tunnel Creek","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / core name 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 5","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"core name 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Stellarton","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / core name 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 6","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"core name 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sodaville","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / core name 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 7","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"core name 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Groveland","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / core name 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 8","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"core name 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Saltwell","unit":"","sourceId":"chipswiki-2476-r8449","location":"Intel/microarchitectures/bonnell · revision 8449 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-24. Not an independent measurement.","entityId":"cw-837d4110f346ced2","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fbonnell&oldid=8449","sourceDate":"2019-05-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2476-r8449"],"url":"https://museum.vlsi.kr/objects/cw-837d4110f346ced2"},{"id":"cw-8397fb4da664bad7","name":"CN5734-1000 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5734-1000bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5734-1000 SP","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5734-1000 SP","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN5734-1000BG1217-SP","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Storage","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jun 26, 2007","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 2007","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":288,"unit":"KiB","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x16 KiB","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8193-r25852","location":"Cavium/octeon plus/cn5734-1000bg1217-sp · revision 25852 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8397fb4da664bad7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8193-r25852","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-8397fb4da664bad7"},{"id":"cw-83d63007dd64aa69","name":"Am486DX-25","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX","year":1993,"architecture":"80486","process":"700 nm","aliases":["Amd am486 am486dx-25"],"fields":[{"key":"Model name","value":"Am486DX-25","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX-25","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX-25","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February, 1992","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 1993","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"25 MT/s","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":700,"unit":"nm","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":89,"unit":"mm²","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8575-r26773","location":"Amd/am486/am486dx-25 · revision 26773 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-83d63007dd64aa69","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8575-r26773"],"url":"https://museum.vlsi.kr/objects/cw-83d63007dd64aa69"},{"id":"cw-83ee16518f2c297c","name":"Xeon Gold 6210U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 6210u"],"fields":[{"key":"Model name","value":"Xeon Gold 6210U","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"6210U","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504198101","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF9B","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. 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Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. 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Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. 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Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. 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Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":20,"unit":"MiB","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":27.5,"unit":"MiB","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x1.375 MiB","unit":"","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. 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Not an independent measurement.","entityId":"cw-83ee16518f2c297c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6210u&oldid=5293","sourceDate":"2019-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":131.13,"unit":"GiB/s","sourceId":"chipswiki-1587-r5293","location":"Intel/xeon gold/6210u · revision 5293 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-01. 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Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF9P","unit":"","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":8,"unit":"","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":205,"unit":"W","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":28,"unit":"MiB","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":38.5,"unit":"MiB","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"28x1.375 MiB","unit":"","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-83f3dd2d2c035c6c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8280&oldid=4902","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1455-r4902","location":"Intel/xeon platinum/8280 · revision 4902 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-83fe963227ef13ff","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fgen10&oldid=12431","sourceDate":"2019-01-31","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Gen9.5","unit":"","sourceId":"chipswiki-3922-r12431","location":"Intel/microarchitectures/gen10 · revision 12431 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-31. 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Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Cx","unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186CU","unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":50,"unit":"MHz","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"12.5 MT/s","unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":160,"unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":48,"unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-160","unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-160","unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14677-r44738","location":"Amd/am186cx/am186cu-50kc\\w · revision 44738 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8403a3f5f0b179a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14677-r44738"],"url":"https://museum.vlsi.kr/objects/cw-8403a3f5f0b179a2"},{"id":"cw-84115659e9932d09","name":"Celeron 3755U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel celeron 3755u"],"fields":[{"key":"Model name","value":"Celeron 3755U","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3755U","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8065801620801","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 5, 2015","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 5, 2015","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1700,"unit":"MHz","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR211","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell U","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1168","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-1168","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8038-r25670","location":"Intel/celeron/3755u · revision 25670 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84115659e9932d09","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8038-r25670"],"url":"https://museum.vlsi.kr/objects/cw-84115659e9932d09"},{"id":"cw-8479175bb8f056af","name":"AMD-K6-2/333ANZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-333anz"],"fields":[{"key":"Model name","value":"K6-2/333ANZ","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/333ANZ","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/333ANZ","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 14, 1999","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333.66,"unit":"MHz","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"95.33 MT/s","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.8,"unit":"V","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8371-r26066","location":"Amd/k6-2/k6-2-333anz · revision 26066 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8479175bb8f056af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-333anz&oldid=26066","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8371-r26066"],"url":"https://museum.vlsi.kr/objects/cw-8479175bb8f056af"},{"id":"cw-84a234ea0fda438f","name":"Snapdragon 662","kind":"sku","entityType":"product-model","subtype":"soc","company":"Qualcomm","year":2020,"architecture":"Cortex-A73","process":"11 nm","aliases":["Qualcomm snapdragon 600 662"],"fields":[{"key":"Model name","value":"Snapdragon 662","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Snapdragon 662","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"SM6115","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 20, 2020","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 20, 2020","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Snapdragon 600","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A73","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 260 Gold","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kryo 260 Silver","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":11,"unit":"nm","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. 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Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. 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Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3733","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":13.91,"unit":"GiB/s","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. Not an independent measurement.","entityId":"cw-84a234ea0fda438f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fsnapdragon%20600%2F662&oldid=1188","sourceDate":"2021-11-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Adreno 610","unit":"","sourceId":"chipswiki-562-r1188","location":"Qualcomm/snapdragon 600/662 · revision 1188 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-11-25. 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Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2278G","unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. 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Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics P630","unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-2406-r8038","location":"Intel/xeon e/e-2278g · revision 8038 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-06-02. Not an independent measurement.","entityId":"cw-84b112296f2bdf76","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","sourceDate":"2019-06-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2406-r8038"],"url":"https://museum.vlsi.kr/objects/cw-84b112296f2bdf76"},{"id":"cw-84b790350a0f85b2","name":"Mobile Pentium II 366","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":1999,"architecture":"P6","process":"250 nm","aliases":["Intel mobile pentium ii 366"],"fields":[{"key":"Model name","value":"Mobile Pentium II 366","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":366,"unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PMG36602002AA","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1998,"unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 25, 1999","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Mobile Pentium II","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":366,"unit":"MHz","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL3HL","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL3AG","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SL36Z","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"P6","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Dixon","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdpA0","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdbA0","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"mdxA0","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":27400000,"unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":180,"unit":"mm²","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":13.1,"unit":"W","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"240-pin connector","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7802-r25241","location":"Intel/mobile pentium ii/366 · revision 25241 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-84b790350a0f85b2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7802-r25241"],"url":"https://museum.vlsi.kr/objects/cw-84b790350a0f85b2"},{"id":"cw-84edc12a63f6284c","name":"Celeron 4305U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2019,"architecture":"Whiskey Lake","process":"14 nm","aliases":["Intel celeron 4305u"],"fields":[{"key":"Model name","value":"Celeron 4305U","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4305U","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8068404066103","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFA5","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"16 April 2019","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"16 April 2019","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Whiskey Lake","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Whiskey Lake","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Whiskey Lake U","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"V0","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-05-01. 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Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 610","unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. Not an independent measurement.","entityId":"cw-84edc12a63f6284c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4305u&oldid=9782","sourceDate":"2019-05-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-2924-r9782","location":"Intel/celeron/4305u · revision 9782 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-01. 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Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3200U","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YM3200C4T2OFG","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. 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Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 3","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","alternatives":[{"value":"32 GiB","sourceId":"chipswiki-267-r542","reason":"Amd/ryzen 3/3200u · revision 542 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1200,"unit":"MHz","sourceId":"chipswiki-267-r542","location":"Amd/ryzen 3/3200u · revision 542 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-08-04. Not an independent measurement.","entityId":"cw-851b45fdf161db73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3200u&oldid=542","sourceDate":"2022-08-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-267-r542"],"url":"https://museum.vlsi.kr/objects/cw-851b45fdf161db73"},{"id":"cw-853008f19ad11827","name":"Xeon Gold 5220T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 5220t"],"fields":[{"key":"Model name","value":"Xeon Gold 5220T","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5220T","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5200,"unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":18,"unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":36,"unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.125,"unit":"MiB","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":576,"unit":"KiB","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":576,"unit":"KiB","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"18x32 KiB","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":18,"unit":"MiB","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"18x1 MiB","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":24.75,"unit":"MiB","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"18x1.375 MiB","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1518-r4970","location":"Intel/xeon gold/5220t · revision 4970 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-853008f19ad11827","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1518-r4970"],"url":"https://museum.vlsi.kr/objects/cw-853008f19ad11827"},{"id":"cw-8539a249ea7b4ddf","name":"Am486DX2-66V8T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2V","year":1994,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx2-66v8t"],"fields":[{"key":"Model name","value":"Am486DX2-66V8T","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-66V8T","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-66V8T","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1994,"unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2V","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":66,"unit":"MHz","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX2V","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8563-r26760","location":"Amd/am486/am486dx2-66v8t · revision 26760 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8539a249ea7b4ddf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8563-r26760"],"url":"https://museum.vlsi.kr/objects/cw-8539a249ea7b4ddf"},{"id":"cw-853bf647c63202ce","name":"K6-2","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":1998,"process":"250 nm","aliases":["Amd microarchitectures k6-2"],"fields":[{"key":"Architecture name","value":"K6-2","unit":"","sourceId":"chipswiki-8756-r27207","location":"Amd/microarchitectures/k6-2 · revision 27207 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-853bf647c63202ce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-2&oldid=27207","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8756-r27207","location":"Amd/microarchitectures/k6-2 · revision 27207 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-853bf647c63202ce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-2&oldid=27207","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8756-r27207","location":"Amd/microarchitectures/k6-2 · revision 27207 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-853bf647c63202ce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-2&oldid=27207","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"June, 1998","unit":"","sourceId":"chipswiki-8756-r27207","location":"Amd/microarchitectures/k6-2 · revision 27207 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-853bf647c63202ce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-2&oldid=27207","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-8756-r27207","location":"Amd/microarchitectures/k6-2 · revision 27207 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-853bf647c63202ce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-2&oldid=27207","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8756-r27207","location":"Amd/microarchitectures/k6-2 · revision 27207 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-853bf647c63202ce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-2&oldid=27207","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"K6","unit":"","sourceId":"chipswiki-8756-r27207","location":"Amd/microarchitectures/k6-2 · revision 27207 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-853bf647c63202ce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-2&oldid=27207","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"K6-III","unit":"","sourceId":"chipswiki-8756-r27207","location":"Amd/microarchitectures/k6-2 · revision 27207 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-01. Not an independent measurement.","entityId":"cw-853bf647c63202ce","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk6-2&oldid=27207","sourceDate":"2017-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8756-r27207"],"url":"https://museum.vlsi.kr/objects/cw-853bf647c63202ce"},{"id":"cw-8552ae9d9f975fb1","name":"Celeron G3900TE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel celeron g3900te"],"fields":[{"key":"Model name","value":"Celeron G3900TE","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G3900TE","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LU","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake S","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 510","unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":950,"unit":"MHz","sourceId":"chipswiki-8030-r25634","location":"Intel/celeron/g3900te · revision 25634 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8552ae9d9f975fb1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8030-r25634","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-8552ae9d9f975fb1"},{"id":"cw-855df98fe53fba89","name":"Tegra Xavier","kind":"sku","entityType":"product-model","subtype":"soc","company":"NVIDIA","year":2018,"architecture":"Carmel","process":"12 nm","aliases":["Nvidia tegra xavier"],"fields":[{"key":"Model name","value":"Xavier","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Nvidia","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Tegra194","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Artificial Intelligence","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 8, 2018","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2018","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Tegra","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Carmel","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Carmel","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9000000000,"unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":350,"unit":"mm²","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":30,"unit":"W","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-4266","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":127.1,"unit":"GiB/s","sourceId":"chipswiki-1578-r5227","location":"Nvidia/tegra/xavier · revision 5227 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-09. Not an independent measurement.","entityId":"cw-855df98fe53fba89","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nvidia%2Ftegra%2Fxavier&oldid=5227","sourceDate":"2019-12-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1578-r5227"],"url":"https://museum.vlsi.kr/objects/cw-855df98fe53fba89"},{"id":"cw-85672fef9dc60c42","name":"Celeron U3405","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P3000","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel celeron u3405"],"fields":[{"key":"Model name","value":"Intel Celeron U3405","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"U3405","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617006201AA","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August, 15 2010","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August, 15 2010","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P3000","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1066.66,"unit":"MHz","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBWX","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":166,"unit":"MHz","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":500,"unit":"MHz","sourceId":"chipswiki-8022-r25604","location":"Intel/celeron/u3405 · revision 25604 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-85672fef9dc60c42","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8022-r25604","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-85672fef9dc60c42"},{"id":"cw-857ac0b2829e08e3","name":"Xeon Gold 5220R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"6200","year":2020,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 5220r"],"fields":[{"key":"Model name","value":"Xeon Gold 5220R","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5220R","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 24, 2020","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":6200,"unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. 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Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake R","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":85,"unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":48,"unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":150,"unit":"W","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":768,"unit":"KiB","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"24x32 KiB","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":24,"unit":"MiB","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"24x1 MiB","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":35.75,"unit":"MiB","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"26x1.375 MiB","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1261-r4094","location":"Intel/xeon gold/5220r · revision 4094 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-28. Not an independent measurement.","entityId":"cw-857ac0b2829e08e3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220r&oldid=4094","sourceDate":"2020-02-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1261-r4094"],"url":"https://museum.vlsi.kr/objects/cw-857ac0b2829e08e3"},{"id":"cw-857cf9c7b663a011","name":"Am486DX2-66SV8B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Am486DX2S","year":1996,"architecture":"80486","process":"500 nm","aliases":["Amd am486 am486dx2-66sv8b"],"fields":[{"key":"Model name","value":"Am486DX2-66SV8B","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am486DX2-66SV8B","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX2-66SV8B","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1995,"unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 1996","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am486","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am486DX2S","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":66,"unit":"MHz","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am486DX2S","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":500,"unit":"nm","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-168","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8565-r26763","location":"Amd/am486/am486dx2-66sv8b · revision 26763 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-857cf9c7b663a011","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8565-r26763"],"url":"https://museum.vlsi.kr/objects/cw-857cf9c7b663a011"},{"id":"cw-85a7ad8f3c8ea00b","name":"Core i9-9980HK","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i9-9000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel core i9 i9-9980hk"],"fields":[{"key":"Model name","value":"Core i9-9980HK","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i9-9980HK","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8068404068910","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFD0","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i9","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i9-9000","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4900,"unit":"MHz","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x256 KiB","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"8x2 MiB","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. Not an independent measurement.","entityId":"cw-85a7ad8f3c8ea00b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i9%2Fi9-9980hk&oldid=1845","sourceDate":"2021-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-759-r1845","location":"Intel/core i9/i9-9980hk · revision 1845 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-05-14. 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Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80617I5580M","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617005487AD","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 26, 2010","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-500","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2666.66,"unit":"MHz","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3333.33,"unit":"MHz","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC28","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC29","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-862ff15a7464df9a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-580m&oldid=25472","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7930-r25472","location":"Intel/core i5/i5-580m · revision 25472 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":800,"unit":"MHz","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8649ef2fd39f802a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-ssp&oldid=25823","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8164-r25823","location":"Cavium/octeon plus/cn5750-800bg1217-ssp · revision 25823 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5850-1000 EXP","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 9, 2006","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8137-r25796","location":"Cavium/octeon plus/cn5850-1000bg1521-exp · revision 25796 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5850-1000bg1521-exp&oldid=25796","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-864c8ec2ad165837","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8137-r25796","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-864c8ec2ad165837"},{"id":"cw-865089e5bc05327f","name":"80286-8/BUC","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Am286 MIL","year":1987,"architecture":"80286","process":"1.5 µm","aliases":["Amd am286 80286-8-buc"],"fields":[{"key":"Model name","value":"80286-8/BUC","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"80286-8/BUC","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"80286-8/BUC","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Military","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1987,"unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 1987","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am286","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am286 MIL","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8 MT/s","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80286,"unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":134000,"unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":73,"unit":"mm²","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"MiB","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CLCC-68","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CLCC","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CLCC-68","unit":"","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-865089e5bc05327f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8613-r26811","location":"Amd/am286/80286-8-buc · revision 26811 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-866320c115ad0ab2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4850&oldid=25069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7699-r25069","location":"Intel/xeon e7/e7-4850 · revision 25069 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-866320c115ad0ab2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4850&oldid=25069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-4850","unit":"","sourceId":"chipswiki-7699-r25069","location":"Intel/xeon e7/e7-4850 · revision 25069 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-866320c115ad0ab2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4850&oldid=25069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615007449AA","unit":"","sourceId":"chipswiki-7699-r25069","location":"Intel/xeon e7/e7-4850 · revision 25069 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-866320c115ad0ab2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4850&oldid=25069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7699-r25069","location":"Intel/xeon e7/e7-4850 · revision 25069 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-866320c115ad0ab2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4850&oldid=25069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7699-r25069","location":"Intel/xeon e7/e7-4850 · revision 25069 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-866320c115ad0ab2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4850&oldid=25069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3V","unit":"","sourceId":"chipswiki-7699-r25069","location":"Intel/xeon e7/e7-4850 · revision 25069 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-866320c115ad0ab2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4850&oldid=25069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7699-r25069","location":"Intel/xeon e7/e7-4850 · revision 25069 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-866320c115ad0ab2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4850&oldid=25069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7699-r25069","location":"Intel/xeon e7/e7-4850 · revision 25069 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-866320c115ad0ab2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4850&oldid=25069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7699-r25069","location":"Intel/xeon e7/e7-4850 · revision 25069 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-866320c115ad0ab2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4850&oldid=25069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7699-r25069","location":"Intel/xeon e7/e7-4850 · revision 25069 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-866320c115ad0ab2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4850&oldid=25069","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7699-r25069","location":"Intel/xeon e7/e7-4850 · revision 25069 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February, 2007","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON Plus","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN58xx","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1000,"unit":"MHz","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x16 KiB","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8124-r25783","location":"Cavium/octeon plus/cn5860-1000bg1521-nsp · revision 25783 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-1000bg1521-nsp&oldid=25783","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8691493725ff97f8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8124-r25783","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-8691493725ff97f8"},{"id":"cw-86b3b3893ab68da7","name":"AM9080ADM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080adm"],"fields":[{"key":"Model name","value":"AMD AM9080ADM","unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080ADM","unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080ADM","unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Military","unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.083,"unit":"MHz","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8465-r26658","location":"Amd/am9080/am9080adm · revision 26658 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86b3b3893ab68da7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8465-r26658"],"url":"https://museum.vlsi.kr/objects/cw-86b3b3893ab68da7"},{"id":"cw-86b54bd8ea4348ce","name":"Celeron 1007U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Celeron 1000","year":2013,"architecture":"Ivy Bridge","process":"22 nm","aliases":["Intel celeron 1007u"],"fields":[{"key":"Model name","value":"Intel Celeron 1007U","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"1007U","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR109","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 20, 2013","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Celeron 1000","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ivy Bridge","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Ivy Bridge","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3805-r11882","location":"Intel/celeron/1007u · revision 11882 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","sourceDate":"2019-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-86b54bd8ea4348ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-13. 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Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":1.986,"unit":"GiB/s","sourceId":"chipswiki-8275-r25935","location":"Cavium/octeon/cn3010-300bg525-cp · revision 25935 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86d2830aff6f90e4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3010-300bg525-cp&oldid=25935","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8275-r25935"],"url":"https://museum.vlsi.kr/objects/cw-86d2830aff6f90e4"},{"id":"cw-86d2a4555b6ad336","name":"Core M3-7Y32","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"m3-7Y","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core m m3-7y32"],"fields":[{"key":"Model name","value":"Core M3-7Y32","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"M3-7Y32","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"HE8067702739830","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR346","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 10, 2017","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core M3","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"m3-7Y","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake Y","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 615","unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-4974-r16096","location":"Intel/core m/m3-7y32 · revision 16096 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-86d2a4555b6ad336","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm3-7y32&oldid=16096","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4974-r16096"],"url":"https://museum.vlsi.kr/objects/cw-86d2a4555b6ad336"},{"id":"cw-86e088f8ac5bea6a","name":"AM9080A-2DM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-2dm"],"fields":[{"key":"Model name","value":"AMD AM9080A-2DM","unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-2DM","unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-2DM","unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Military","unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.632,"unit":"MHz","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8478-r26671","location":"Amd/am9080/am9080a-2dm · revision 26671 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-86e088f8ac5bea6a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2dm&oldid=26671","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8478-r26671"],"url":"https://museum.vlsi.kr/objects/cw-86e088f8ac5bea6a"},{"id":"cw-86f7c504d869676f","name":"EPYC 7272","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"7002","year":2019,"architecture":"Zen 2","process":"7 nm","aliases":["Amd epyc 7272"],"fields":[{"key":"Model name","value":"EPYC 7272","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":7272,"unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000079","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000079WOF","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12x512 KiB","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x16 MiB","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-86f7c504d869676f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7272&oldid=2235","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-855-r2235","location":"Amd/epyc/7272 · revision 2235 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-7260U","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-7200","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3400,"unit":"MHz","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87026fb4e2874275","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-7260u&oldid=25446","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7909-r25446","location":"Intel/core i5/i5-7260u · revision 25446 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E+/350IUZ","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":350,"unit":"MHz","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":7.5,"unit":"W","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.5,"unit":"V","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Embedded","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1000-r2851","location":"Amd/k6-2+/k6-2e+-350iuz · revision 2851 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-350iuz&oldid=2851","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OBGA-349","unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":349,"unit":"","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-871d475c8eeb118e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2FOBGA-349&oldid=91599","sourceDate":"2020-07-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31127-r91599","location":"Template:Packages/amd/OBGA-349 · revision 91599 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. 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Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR06X","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-7958-r25507","location":"Intel/core i5/i5-2475m · revision 25507 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-2475m&oldid=25507","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8723537e17015ea2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7958-r25507","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-8723537e17015ea2"},{"id":"cw-8740883a0e9232ce","name":"i486DX-33","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486DX","year":1990,"architecture":"80486","process":"1 µm","aliases":["Intel 80486 486dx-33"],"fields":[{"key":"Model name","value":"Intel i486DX-33","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. 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Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486DX-33","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX-33","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MA80486DX-33","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MG80486DX-33","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MQ80486DX-33","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"KU80486DX-33","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"SB80486DX-33","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / part number 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 6","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"part number 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 7, 1990","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486DX","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"33 MT/s","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX329","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX412","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX419","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX666","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX668","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX729","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / s-spec 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 6","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"s-spec 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX767","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / s-spec 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 7","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"s-spec 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX810","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / s-spec 8","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 8","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"s-spec 8","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX829","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / s-spec 9","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 9","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"s-spec 9","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-7606-r24783","location":"Intel/80486/486dx-33 · revision 24783 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-18. Not an independent measurement.","entityId":"cw-8740883a0e9232ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-33&oldid=24783","sourceDate":"2017-12-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7606-r24783"],"url":"https://museum.vlsi.kr/objects/cw-8740883a0e9232ce"},{"id":"cw-87534bb7343aab39","name":"FireFlight","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2018,"architecture":"Zen","aliases":["Zhongshan subor fireflight"],"fields":[{"key":"Model name","value":"FireFlight","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"FireFlight","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Console","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 3, 2018","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 3, 2018","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"PCIe 3.0","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"GDDR5","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":143.1,"unit":"GiB/s","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega","unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-2536-r8747","location":"Zhongshan subor/fireflight · revision 8747 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-12. Not an independent measurement.","entityId":"cw-87534bb7343aab39","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Zhongshan%20subor%2Ffireflight&oldid=8747","sourceDate":"2019-05-12","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2536-r8747"],"url":"https://museum.vlsi.kr/objects/cw-87534bb7343aab39"},{"id":"cw-875df4e1dcdfb3ff","name":"EPYC Embedded 3351","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc embedded 3351"],"fields":[{"key":"Model name","value":"EPYC Embedded 3351","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3351,"unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"PE3351BNQCAAF","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC Embedded","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Snowy Owl","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9600000000,"unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":80,"unit":"W","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1152,"unit":"KiB","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12 × 64 KiB","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12 × 32 KiB","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12 × 512 KiB","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 8 MiB","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"85.33 GB/s","unit":"","sourceId":"chipswiki-405-r875","location":"Amd/epyc embedded/3351 · revision 875 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SP4","unit":"","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. 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Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":45,"unit":"mm","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-875df4e1dcdfb3ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-405-r875","chipswiki-31097-r91556"],"url":"https://museum.vlsi.kr/objects/cw-875df4e1dcdfb3ff"},{"id":"cw-87645617171898c1","name":"MSM6800","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2006,"architecture":"ARM9","process":"130 nm","aliases":["Qualcomm msm6xxx msm6800"],"fields":[{"key":"Model name","value":"Qualcomm MSM6800","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6800","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 13, 2005","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April, 2006","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":270,"unit":"MHz","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7654-r24915","location":"Qualcomm/msm6xxx/msm6800 · revision 24915 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87645617171898c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6800&oldid=24915","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7654-r24915"],"url":"https://museum.vlsi.kr/objects/cw-87645617171898c1"},{"id":"cw-8765e03b799f6ecd","name":"AMD-K5-PR75ABR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"SSA/5","year":1996,"architecture":"K5","process":"350 nm","aliases":["Amd k5 amd-k5-pr75abr"],"fields":[{"key":"Model name","value":"AMD-K5-PR75ABR","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K5-PR75ABR","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K5-PR75ABR","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1996,"unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 7, 1996","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K5","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"SSA/5","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":75,"unit":"MHz","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"50 MT/s","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K5","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"SSA/5","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":0,"unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":1,"unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":350,"unit":"nm","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000,"unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":161,"unit":"mm²","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.525,"unit":"V","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SPGA-296","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 5","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8393-r26089","location":"Amd/k5/amd-k5-pr75abr · revision 26089 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8765e03b799f6ecd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk5%2Famd-k5-pr75abr&oldid=26089","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8393-r26089"],"url":"https://museum.vlsi.kr/objects/cw-8765e03b799f6ecd"},{"id":"cw-8786cbee041ad440","name":"Palm Cove","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Intel","year":2018,"process":"10 nm","aliases":["Intel microarchitectures palm cove"],"fields":[{"key":"Architecture name","value":"Palm Cove","unit":"","sourceId":"chipswiki-2549-r8783","location":"Intel/microarchitectures/palm cove · revision 8783 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-09. Not an independent measurement.","entityId":"cw-8786cbee041ad440","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpalm%20cove&oldid=8783","sourceDate":"2019-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2549-r8783","location":"Intel/microarchitectures/palm cove · revision 8783 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-09. Not an independent measurement.","entityId":"cw-8786cbee041ad440","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpalm%20cove&oldid=8783","sourceDate":"2019-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2549-r8783","location":"Intel/microarchitectures/palm cove · revision 8783 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-09. Not an independent measurement.","entityId":"cw-8786cbee041ad440","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpalm%20cove&oldid=8783","sourceDate":"2019-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2018,"unit":"","sourceId":"chipswiki-2549-r8783","location":"Intel/microarchitectures/palm cove · revision 8783 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-09. Not an independent measurement.","entityId":"cw-8786cbee041ad440","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpalm%20cove&oldid=8783","sourceDate":"2019-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-2549-r8783","location":"Intel/microarchitectures/palm cove · revision 8783 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-09. Not an independent measurement.","entityId":"cw-8786cbee041ad440","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpalm%20cove&oldid=8783","sourceDate":"2019-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":2,"unit":"","sourceId":"chipswiki-2549-r8783","location":"Intel/microarchitectures/palm cove · revision 8783 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-09. Not an independent measurement.","entityId":"cw-8786cbee041ad440","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpalm%20cove&oldid=8783","sourceDate":"2019-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-2549-r8783","location":"Intel/microarchitectures/palm cove · revision 8783 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-09. Not an independent measurement.","entityId":"cw-8786cbee041ad440","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpalm%20cove&oldid=8783","sourceDate":"2019-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2549-r8783","location":"Intel/microarchitectures/palm cove · revision 8783 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-09. Not an independent measurement.","entityId":"cw-8786cbee041ad440","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpalm%20cove&oldid=8783","sourceDate":"2019-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-2549-r8783","location":"Intel/microarchitectures/palm cove · revision 8783 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2019-05-09. Not an independent measurement.","entityId":"cw-8786cbee041ad440","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpalm%20cove&oldid=8783","sourceDate":"2019-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2549-r8783","location":"Intel/microarchitectures/palm cove · revision 8783 · {{microarchitecture}} / l3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core","note":"Source-reported parameter; source revision 2019-05-09. Not an independent measurement.","entityId":"cw-8786cbee041ad440","scope":"core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Fpalm%20cove&oldid=8783","sourceDate":"2019-05-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"Skylake","unit":"","sourceId":"chipswiki-2549-r8783","location":"Intel/microarchitectures/palm cove · revision 8783 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-09. 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Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":917,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701148401","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085100","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AV8062701085101","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0FH","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR08X","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0F4","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0V7","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2012,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2012,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":900,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":17,"unit":"W","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":800,"unit":"MHz","sourceId":"chipswiki-7798-r25236","location":"Intel/pentium (2009)/917 · revision 25236 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1023","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1023,"unit":"","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":31,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31339-r92076","location":"Template:Packages/intel/fcbga-1023 · revision 92076 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-878cb4536663fdd5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1023&oldid=92076","sourceDate":"2017-12-11","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7798-r25236","chipswiki-31339-r92076"],"url":"https://museum.vlsi.kr/objects/cw-878cb4536663fdd5"},{"id":"cw-879ca86936e224cf","name":"i486DX-25","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"486DX","year":1989,"architecture":"80486","process":"1 µm","aliases":["Intel 80486 486dx-25"],"fields":[{"key":"Model name","value":"Intel i486DX-25","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i486DX-25","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486-25","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"A80486DX-25","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MA80486DX-25","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MG80486DX-25","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MQ80486DX-25","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 1989","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":80486,"unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"486DX","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":25,"unit":"MHz","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"25 MT/s","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX250","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX300","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX308","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / s-spec 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"s-spec 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX328","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / s-spec 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 4","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"s-spec 4","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX418","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / s-spec 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 5","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"s-spec 5","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX493","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / s-spec 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 6","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"s-spec 6","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SX728","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / s-spec 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 7","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"s-spec 7","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80486,"unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"486DX","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1,"unit":"µm","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":800,"unit":"nm","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1200000,"unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 1","unit":"","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-8091-r25744","location":"Intel/80486/486dx-25 · revision 25744 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-879ca86936e224cf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2F80486%2F486dx-25&oldid=25744","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8091-r25744"],"url":"https://museum.vlsi.kr/objects/cw-879ca86936e224cf"},{"id":"cw-87e910e33307ae73","name":"Am2070","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Ambric","series":"Gen 3","year":null,"architecture":"Ambric","process":"90 nm","aliases":["Ambric am2000 am2070"],"fields":[{"key":"Model name","value":"Am2070","unit":"","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Ambric","unit":"","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am2070","unit":"","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am2070","unit":"","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2008,"unit":"","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am2000","unit":"","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Gen 3","unit":"","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ambric","unit":"","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":560,"unit":"","sourceId":"chipswiki-8661-r26860","location":"Ambric/am2000/am2070 · revision 26860 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87e910e33307ae73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8661-r26860"],"url":"https://museum.vlsi.kr/objects/cw-87e910e33307ae73"},{"id":"cw-87f83ea3e64a76dc","name":"Athlon MP 1600+","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd athlon mp amp1600dms3c"],"fields":[{"key":"Model name","value":"AMD Athlon MP 1600+","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Athlon MP 1600+","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMP1600DMS3C","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 15, 2001","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 15, 2001","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon MP","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1400,"unit":"MHz","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"266 MT/s","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Athlon MP","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"AMD-760MP","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Palomino","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":2,"unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":37500000,"unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":128,"unit":"mm²","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":62.8,"unit":"W","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8457-r26650","location":"Amd/athlon mp/amp1600dms3c · revision 26650 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20mp%2Famp1600dms3c&oldid=26650","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"OPGA-453","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"OPGA","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":453,"unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1.27,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.53,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.942,"unit":"mm","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-87f83ea3e64a76dc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpga-453&oldid=92404","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-31459-r92404","location":"Template:Packages/amd/pga-453 · revision 92404 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-2163IT","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8067303692003","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3ZP","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 7, 2018","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-2000","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake (server)","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DE","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M1","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":24,"unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"GiB","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":75,"unit":"W","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":12,"unit":"MiB","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16.5,"unit":"MiB","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"12x1.375 MiB","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":79.47,"unit":"GiB/s","sourceId":"chipswiki-7154-r22583","location":"Intel/xeon d/d-2163it · revision 22583 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","sourceDate":"2018-02-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-2518","unit":"","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. Not an independent measurement.","entityId":"cw-87fa341ec1134706","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","sourceDate":"2018-02-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":52.5,"unit":"mm","sourceId":"chipswiki-31304-r92006","location":"Template:Packages/intel/fcbga-2518 · revision 92006 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-02-08. 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Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E-2236","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068404174603","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRF7G","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 27, 2019","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E-2200","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4800,"unit":"MHz","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Mehlow","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cannon Point","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake ER","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"U0","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149.6,"unit":"mm²","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":80,"unit":"W","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":12,"unit":"MiB","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-1242-r3963","location":"Intel/xeon e/e-2236 · revision 3963 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-03-13. Not an independent measurement.","entityId":"cw-88195483b1dc0fa5","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","sourceDate":"2020-03-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1242-r3963"],"url":"https://museum.vlsi.kr/objects/cw-88195483b1dc0fa5"},{"id":"cw-8827c12cf815f2c8","name":"UltraSPARC-I 167MHz","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Sun Microsystems","series":"UltraSPARC-I","year":1995,"architecture":"UltraSPARC-I","process":"0.5 µm","aliases":["Sun microsystems ultrasparc stp1030bga-167"],"fields":[{"key":"Model name","value":"UltraSPARC-I 167MHz","unit":"","sourceId":"chipswiki-7639-r24896","location":"Sun microsystems/ultrasparc/stp1030bga-167 · revision 24896 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8827c12cf815f2c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-167&oldid=24896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Sun Microsystems","unit":"","sourceId":"chipswiki-7639-r24896","location":"Sun microsystems/ultrasparc/stp1030bga-167 · revision 24896 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8827c12cf815f2c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-167&oldid=24896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7639-r24896","location":"Sun microsystems/ultrasparc/stp1030bga-167 · revision 24896 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8827c12cf815f2c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-167&oldid=24896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 2, 1995","unit":"","sourceId":"chipswiki-7639-r24896","location":"Sun microsystems/ultrasparc/stp1030bga-167 · revision 24896 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8827c12cf815f2c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-167&oldid=24896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"UltraSPARC","unit":"","sourceId":"chipswiki-7639-r24896","location":"Sun microsystems/ultrasparc/stp1030bga-167 · revision 24896 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8827c12cf815f2c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-167&oldid=24896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"UltraSPARC-I","unit":"","sourceId":"chipswiki-7639-r24896","location":"Sun microsystems/ultrasparc/stp1030bga-167 · revision 24896 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8827c12cf815f2c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-167&oldid=24896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"SPARC V9","unit":"","sourceId":"chipswiki-7639-r24896","location":"Sun microsystems/ultrasparc/stp1030bga-167 · revision 24896 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8827c12cf815f2c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-167&oldid=24896","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-512","unit":"","sourceId":"chipswiki-31351-r92104","location":"Template:Packages/sun microsystems/bga-521 · revision 92104 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8827c12cf815f2c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fsun%20microsystems%2Fbga-521&oldid=92104","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31351-r92104","location":"Template:Packages/sun microsystems/bga-521 · revision 92104 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8827c12cf815f2c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fsun%20microsystems%2Fbga-521&oldid=92104","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":512,"unit":"","sourceId":"chipswiki-31351-r92104","location":"Template:Packages/sun microsystems/bga-521 · revision 92104 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8827c12cf815f2c8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fsun%20microsystems%2Fbga-521&oldid=92104","sourceDate":"2017-11-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7639-r24896","chipswiki-31351-r92104"],"url":"https://museum.vlsi.kr/objects/cw-8827c12cf815f2c8"},{"id":"cw-88481e9208930d0b","name":"Duron 600 (Spitfire)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2000,"architecture":"K7","process":"180 nm","aliases":["Amd duron d600aut1b"],"fields":[{"key":"Model name","value":"Duron 600","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 600","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D600AUT1B","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"D0600AUT1B","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 5, 2000","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 19, 2000","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Spitfire","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":3,"unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25000000,"unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":100,"unit":"mm²","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.6,"unit":"V","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":27.4,"unit":"W","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8441-r26149","location":"Amd/duron/d600aut1b · revision 26149 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-88481e9208930d0b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8441-r26149"],"url":"https://museum.vlsi.kr/objects/cw-88481e9208930d0b"},{"id":"cw-8895687896c8f436","name":"A11 Bionic","kind":"sku","entityType":"product-model","subtype":"soc","company":"Apple","year":2017,"architecture":"Monsoon","process":"10 nm","aliases":["Apple ax a11"],"fields":[{"key":"Model name","value":"A11 Bionic","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Apple","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"A11 Bionic","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 12, 2017","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 22, 2017","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ax","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.2-A","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Monsoon","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Monsoon","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Mistral","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4300000000,"unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":87.66,"unit":"mm²","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":6,"unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-873-r2281","location":"Apple/ax/a11 · revision 2281 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-04. Not an independent measurement.","entityId":"cw-8895687896c8f436","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","sourceDate":"2021-01-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-873-r2281"],"url":"https://museum.vlsi.kr/objects/cw-8895687896c8f436"},{"id":"cw-890c57ed32db6170","name":"Ryzen 7 PRO 5850U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 7 pro 5850u"],"fields":[{"key":"Model name","value":"Ryzen 7 PRO 5850U","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5850U","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000289","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 16, 2021","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 16, 2021","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. 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Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. 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Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. 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Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4-4266","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-21. 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Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. 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Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":2000,"unit":"MHz","sourceId":"chipswiki-429-r906","location":"Amd/ryzen 7/pro 5850u · revision 906 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-21. Not an independent measurement.","entityId":"cw-890c57ed32db6170","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","sourceDate":"2022-03-21","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-429-r906"],"url":"https://museum.vlsi.kr/objects/cw-890c57ed32db6170"},{"id":"cw-892b5b3c2cb5a3a3","name":"Xeon D-1528","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"D-1500","year":2015,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon d d-1528"],"fields":[{"key":"Model name","value":"Xeon D-1528","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"D-1528","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"GG8067402569500","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2DL","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 1, 2015","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 1, 2015","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon D","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"D-1500","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1900,"unit":"MHz","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2500,"unit":"MHz","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grangeville","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell DE","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":6,"unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"V2","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-892b5b3c2cb5a3a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","sourceDate":"2019-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3740-r11449","location":"Intel/xeon d/d-1528 · revision 11449 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-01. 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Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x8 KiB","unit":"","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8938d5d4dbc18daa","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-scp&oldid=25856","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8197-r25856","location":"Cavium/octeon/cn3860-500bg1521-scp · revision 25856 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-620LE","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004455AB","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2010","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1999.99,"unit":"MHz","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2799.99,"unit":"MHz","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBXH","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":266,"unit":"MHz","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":566,"unit":"MHz","sourceId":"chipswiki-7855-r25355","location":"Intel/core i7/i7-620le · revision 25355 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-620le&oldid=25355","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-89df8113e1895ac2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7855-r25355","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-89df8113e1895ac2"},{"id":"cw-8a0d83a913a8e199","name":"Ryzen 5 PRO 5650G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"5000","year":2021,"architecture":"Zen 3","process":"7 nm","aliases":["Amd ryzen 5 pro 5650g"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 5650G","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 5650G","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000255","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2021","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3900,"unit":"MHz","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4400,"unit":"MHz","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 3","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cezanne","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":25,"unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":80,"unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x16 MiB","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":47.68,"unit":"GiB/s","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1900,"unit":"MHz","sourceId":"chipswiki-610-r1432","location":"Amd/ryzen 5/pro 5650g · revision 1432 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-13. Not an independent measurement.","entityId":"cw-8a0d83a913a8e199","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","sourceDate":"2021-09-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-610-r1432"],"url":"https://museum.vlsi.kr/objects/cw-8a0d83a913a8e199"},{"id":"cw-8a16c7165fa6f137","name":"Am2045","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Ambric","series":"Gen 1","year":2007,"architecture":"Ambric","process":"130 nm","aliases":["Ambric am2000 am2045"],"fields":[{"key":"Model name","value":"Am2045","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Ambric","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am2045","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am2045","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am2045A","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 10, 2006","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2007","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am2000","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Gen 1","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Ambric","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":117000000,"unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":344,"unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-868","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA-868","unit":"","sourceId":"chipswiki-8663-r26862","location":"Ambric/am2000/am2045 · revision 26862 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a16c7165fa6f137","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8663-r26862"],"url":"https://museum.vlsi.kr/objects/cw-8a16c7165fa6f137"},{"id":"cw-8a2b6f207851d0ce","name":"Ryzen 7 PRO 1700X","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Ryzen PRO","year":null,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 7 pro 1700x"],"fields":[{"key":"Model name","value":"Ryzen 7 PRO 1700X","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 1700X","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD17XBBAM88AE","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 29, 2017","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Ryzen PRO","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Summit Ridge","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":95,"unit":"W","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":768,"unit":"KiB","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x64 KiB","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x8 MiB","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-1210-r3780","location":"Amd/ryzen 7/pro 1700x · revision 3780 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","sourceDate":"2020-04-12","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-04-12. Not an independent measurement.","entityId":"cw-8a2b6f207851d0ce","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1210-r3780","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-8a2b6f207851d0ce"},{"id":"cw-8a6268f1b5faf3a2","name":"Ryzen Embedded R1505G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"R1000","year":2019,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen embedded r1505g"],"fields":[{"key":"Model name","value":"Ryzen Embedded R1505G","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"R1505G","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YE1505C4T2OFG","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 16, 2019","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 16, 2019","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"R1000","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2400,"unit":"MHz","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3300,"unit":"MHz","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Banded Kestrel","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1000,"unit":"MHz","sourceId":"chipswiki-924-r2548","location":"Amd/ryzen embedded/r1505g · revision 2548 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8a6268f1b5faf3a2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-924-r2548","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-8a6268f1b5faf3a2"},{"id":"cw-8a9b1eb2d0f03041","name":"AM9080A-2DI","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-2di"],"fields":[{"key":"Model name","value":"AMD AM9080A-2DI","unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AM9080A-2DI","unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AM9080A-2DI","unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Industrial","unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.632,"unit":"MHz","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"Side Brazed CerDIP","unit":"","sourceId":"chipswiki-8480-r26673","location":"Amd/am9080/am9080a-2di · revision 26673 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8a9b1eb2d0f03041","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-2di&oldid=26673","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8480-r26673"],"url":"https://museum.vlsi.kr/objects/cw-8a9b1eb2d0f03041"},{"id":"cw-8aa4a37ff46a0ac7","name":"Ryzen 7 PRO 2700U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000U","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 7 pro 2700u"],"fields":[{"key":"Model name","value":"Ryzen 7 PRO 2700U","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 2700U","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 8, 2018","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 8, 2018","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"2000U","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 10","unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":10,"unit":"","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1300,"unit":"MHz","sourceId":"chipswiki-5234-r17148","location":"Amd/ryzen 7/pro 2700u · revision 17148 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","sourceDate":"2018-07-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FP5","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1140,"unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":"0.7-1.0 mm","unit":"","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":35,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":25,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.38,"unit":"mm","sourceId":"chipswiki-31111-r91577","location":"Template:Packages/amd/socket fp5 · revision 91577 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-18. Not an independent measurement.","entityId":"cw-8aa4a37ff46a0ac7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20fp5&oldid=91577","sourceDate":"2020-09-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5234-r17148","chipswiki-31111-r91577"],"url":"https://museum.vlsi.kr/objects/cw-8aa4a37ff46a0ac7"},{"id":"cw-8abce57fff703bc5","name":"K8","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"AMD","year":2003,"process":"130 nm","aliases":["Amd microarchitectures k8"],"fields":[{"key":"Architecture name","value":"K8","unit":"","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":"September 23, 2003","unit":"","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":65,"unit":"nm","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / process 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 3","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"process 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":1,"unit":"","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":3,"unit":"","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture predecessor","value":"K7","unit":"","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / predecessor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"K9","unit":"","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"K10","unit":"","sourceId":"chipswiki-547-r1129","location":"Amd/microarchitectures/k8 · revision 1129 · {{microarchitecture}} / successor 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"successor 2","note":"Source-reported parameter; source revision 2022-01-04. Not an independent measurement.","entityId":"cw-8abce57fff703bc5","scope":"successor 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fmicroarchitectures%2Fk8&oldid=1129","sourceDate":"2022-01-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-547-r1129"],"url":"https://museum.vlsi.kr/objects/cw-8abce57fff703bc5"},{"id":"cw-8ac097203f0db330","name":"Kirin 810","kind":"sku","entityType":"product-model","subtype":"soc","company":"HiSilicon","series":"800","year":2019,"architecture":"Cortex-A76","process":"7 nm","aliases":["Hisilicon kirin 810"],"fields":[{"key":"Model name","value":"Kirin 810","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"HiSilicon","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":810,"unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 21, 2019","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 21, 2019","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Kirin","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2270,"unit":"MHz","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1880,"unit":"MHz","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A76","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A76","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A55","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 1)","value":256,"unit":"KiB","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 1)","value":128,"unit":"KiB","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 1)","value":"2x64 KiB","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 1)","value":128,"unit":"KiB","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 1)","value":"2x64 KiB","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 1)","value":1,"unit":"MiB","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 1)","value":"2x512 KiB","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache — Cache (section 2)","value":384,"unit":"KiB","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache — Cache (section 2)","value":192,"unit":"KiB","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization — Cache (section 2)","value":"6x32 KiB","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache — Cache (section 2)","value":192,"unit":"KiB","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization — Cache (section 2)","value":"6x32 KiB","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache — Cache (section 2)","value":768,"unit":"KiB","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization — Cache (section 2)","value":"6x128 KiB","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 2)","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"Cache (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-4266","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.78,"unit":"GiB/s","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G52","unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":850,"unit":"MHz","sourceId":"chipswiki-584-r1342","location":"Hisilicon/kirin/810 · revision 1342 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-10-25. Not an independent measurement.","entityId":"cw-8ac097203f0db330","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Hisilicon%2Fkirin%2F810&oldid=1342","sourceDate":"2021-10-25","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-584-r1342"],"url":"https://museum.vlsi.kr/objects/cw-8ac097203f0db330"},{"id":"cw-8b36e53208e67c67","name":"Core i7-660LM","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-600","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i7 i7-660lm"],"fields":[{"key":"Model name","value":"Intel Core i7-660LM","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-660LM","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004857AA","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2010","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 13, 2010","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-600","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2266.66,"unit":"MHz","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3066.66,"unit":"MHz","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBSW","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7845-r25342","location":"Intel/core i7/i7-660lm · revision 25342 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-660lm&oldid=25342","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b36e53208e67c67","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7845-r25342","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-8b36e53208e67c67"},{"id":"cw-8b3bad9cff627b95","name":"CN5750-800 SP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN57xx","year":2007,"architecture":"cnMIPS","process":"90 nm","aliases":["Cavium octeon plus cn5750-800bg1217-sp"],"fields":[{"key":"Model name","value":"Cavium CN5750-800 SP","unit":"","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN5750-800 SP","unit":"","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN57xx","unit":"","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12x32 KiB","unit":"","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12x16 KiB","unit":"","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8165-r25824","location":"Cavium/octeon plus/cn5750-800bg1217-sp · revision 25824 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5750-800bg1217-sp&oldid=25824","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1217","unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1217,"unit":"","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":40,"unit":"mm","sourceId":"chipswiki-31460-r92405","location":"Template:Packages/cavium/fcbga-1217 · revision 92405 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b3bad9cff627b95","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1217&oldid=92405","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8165-r25824","chipswiki-31460-r92405"],"url":"https://museum.vlsi.kr/objects/cw-8b3bad9cff627b95"},{"id":"cw-8b63964cb7ff2bc8","name":"Pentium G4560T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"G4500","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel pentium (2009) g4560t"],"fields":[{"key":"Model name","value":"Pentium G4560T","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4560T","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8067703016117","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR35T","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":92,"unit":"°C","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 610","unit":"","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b63964cb7ff2bc8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2Fg4560t&oldid=25218","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7783-r25218","location":"Intel/pentium (2009)/g4560t · revision 25218 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. 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Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EM–33KC\\W","unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":33,"unit":"MHz","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"8.25 MT/s","unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PQFP-100","unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PQFP","unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"PQFP-100","unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14652-r44713","location":"Amd/am186ex/am186em–33kc\\w · revision 44713 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-8b6647cb930a7a8a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14652-r44713"],"url":"https://museum.vlsi.kr/objects/cw-8b6647cb930a7a8a"},{"id":"cw-8b720705ebf526bc","name":"Xeon E5-2630L v4","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E5-2000","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel xeon e5 e5-2630l v4"],"fields":[{"key":"Model name","value":"Xeon E5-2630L v4","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E5-2630L v4","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066002033202","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 20, 2016","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E5","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E5-2000","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1800,"unit":"MHz","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2900,"unit":"MHz","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":2,"unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2P2","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Grantley EP 2S","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"C610 Series","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell EP","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":"4F","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3200000000,"unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246.24,"unit":"mm²","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1536,"unit":"GiB","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.82,"unit":"V","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":55,"unit":"W","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-2011-v3","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCLGA","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011-v3","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x2.5 MiB","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-7740-r25117","location":"Intel/xeon e5/e5-2630l v4 · revision 25117 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8b720705ebf526bc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e5%2Fe5-2630l%20v4&oldid=25117","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7740-r25117"],"url":"https://museum.vlsi.kr/objects/cw-8b720705ebf526bc"},{"id":"cw-8b7d771ddf55e6e0","name":"Celeron G4950","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4000","year":2019,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel celeron g4950"],"fields":[{"key":"Model name","value":"Celeron G4950","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G4950","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403378012","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3YM","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 23, 2019","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54,"unit":"W","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 610","unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-2852-r9572","location":"Intel/celeron/g4950 · revision 9572 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-05-07. Not an independent measurement.","entityId":"cw-8b7d771ddf55e6e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg4950&oldid=9572","sourceDate":"2019-05-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-2852-r9572"],"url":"https://museum.vlsi.kr/objects/cw-8b7d771ddf55e6e0"},{"id":"cw-8c0586d7d0088fdb","name":"CN3840-400 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3840-400bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3840-400 EXP","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3840-400 EXP","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3840-400BG1521-EXP","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x8 KiB","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8220-r25879","location":"Cavium/octeon/cn3840-400bg1521-exp · revision 25879 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-400bg1521-exp&oldid=25879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c0586d7d0088fdb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8220-r25879","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-8c0586d7d0088fdb"},{"id":"cw-8c3f58f87c20d98e","name":"P8086B","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"P8086","year":1982,"architecture":"8086","process":"3 µm","aliases":["Amd am8086 p8086b"],"fields":[{"key":"Model name","value":"AMD P8086B","unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P8086B","unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"P8086B","unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1982,"unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am8086","unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P8086","unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":5,"unit":"MHz","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8086,"unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8086,"unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":3,"unit":"µm","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":29000,"unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":33,"unit":"mm²","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"PDIP-40","unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PDIP","unit":"","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8491-r26684","location":"Amd/am8086/p8086b · revision 26684 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c3f58f87c20d98e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fp8086b&oldid=26684","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8491-r26684"],"url":"https://museum.vlsi.kr/objects/cw-8c3f58f87c20d98e"},{"id":"cw-8c4cf704a7981934","name":"ThunderX1","kind":"microarchitecture","entityType":"architecture","subtype":"microarchitecture","company":"Cavium","year":2014,"process":"28 nm","aliases":["Cavium microarchitectures thunderx1"],"fields":[{"key":"Architecture name","value":"ThunderX1","unit":"","sourceId":"chipswiki-3908-r12392","location":"Cavium/microarchitectures/thunderx1 · revision 12392 · {{microarchitecture}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-01. Not an independent measurement.","entityId":"cw-8c4cf704a7981934","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fthunderx1&oldid=12392","sourceDate":"2019-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-3908-r12392","location":"Cavium/microarchitectures/thunderx1 · revision 12392 · {{microarchitecture}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-01. Not an independent measurement.","entityId":"cw-8c4cf704a7981934","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fthunderx1&oldid=12392","sourceDate":"2019-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-3908-r12392","location":"Cavium/microarchitectures/thunderx1 · revision 12392 · {{microarchitecture}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-01. Not an independent measurement.","entityId":"cw-8c4cf704a7981934","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fthunderx1&oldid=12392","sourceDate":"2019-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Introduction","value":2014,"unit":"","sourceId":"chipswiki-3908-r12392","location":"Cavium/microarchitectures/thunderx1 · revision 12392 · {{microarchitecture}} / introduction","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-01. Not an independent measurement.","entityId":"cw-8c4cf704a7981934","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fthunderx1&oldid=12392","sourceDate":"2019-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-3908-r12392","location":"Cavium/microarchitectures/thunderx1 · revision 12392 · {{microarchitecture}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-01. Not an independent measurement.","entityId":"cw-8c4cf704a7981934","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fthunderx1&oldid=12392","sourceDate":"2019-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture core count","value":24,"unit":"","sourceId":"chipswiki-3908-r12392","location":"Cavium/microarchitectures/thunderx1 · revision 12392 · {{microarchitecture}} / cores","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-01. Not an independent measurement.","entityId":"cw-8c4cf704a7981934","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fthunderx1&oldid=12392","sourceDate":"2019-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superscalar","unit":"","sourceId":"chipswiki-3908-r12392","location":"Cavium/microarchitectures/thunderx1 · revision 12392 · {{microarchitecture}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-01. Not an independent measurement.","entityId":"cw-8c4cf704a7981934","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fthunderx1&oldid=12392","sourceDate":"2019-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU execution type","value":"Superpipeline","unit":"","sourceId":"chipswiki-3908-r12392","location":"Cavium/microarchitectures/thunderx1 · revision 12392 · {{microarchitecture}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-02-01. Not an independent measurement.","entityId":"cw-8c4cf704a7981934","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fthunderx1&oldid=12392","sourceDate":"2019-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU decode width","value":"4?","unit":"","sourceId":"chipswiki-3908-r12392","location":"Cavium/microarchitectures/thunderx1 · revision 12392 · {{microarchitecture}} / decode","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-01. Not an independent measurement.","entityId":"cw-8c4cf704a7981934","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fthunderx1&oldid=12392","sourceDate":"2019-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.1","unit":"","sourceId":"chipswiki-3908-r12392","location":"Cavium/microarchitectures/thunderx1 · revision 12392 · {{microarchitecture}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-01. Not an independent measurement.","entityId":"cw-8c4cf704a7981934","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fthunderx1&oldid=12392","sourceDate":"2019-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-3908-r12392","location":"Cavium/microarchitectures/thunderx1 · revision 12392 · {{microarchitecture}} / l2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"socket","note":"Source-reported parameter; source revision 2019-02-01. Not an independent measurement.","entityId":"cw-8c4cf704a7981934","scope":"socket","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fthunderx1&oldid=12392","sourceDate":"2019-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture successor","value":"Vulcan","unit":"","sourceId":"chipswiki-3908-r12392","location":"Cavium/microarchitectures/thunderx1 · revision 12392 · {{microarchitecture}} / successor","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-02-01. Not an independent measurement.","entityId":"cw-8c4cf704a7981934","scope":"architecture","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fmicroarchitectures%2Fthunderx1&oldid=12392","sourceDate":"2019-02-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3908-r12392"],"url":"https://museum.vlsi.kr/objects/cw-8c4cf704a7981934"},{"id":"cw-8c512563a2ccdec4","name":"K6-2+/533ACZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Mobile","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2+-533acz"],"fields":[{"key":"Model name","value":"K6-2+/533ACZ","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2+/533ACZ","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2+/533ACZ","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":533,"unit":"MHz","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":18,"unit":"W","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 5, 2000","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Mobile","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-996-r2842","location":"Amd/k6-2+/k6-2+-533acz · revision 2842 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2%2B-533acz&oldid=2842","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":321,"unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":2.54,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.3,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super Socket 7","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-27. Not an independent measurement.","entityId":"cw-8c512563a2ccdec4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-996-r2842","chipswiki-31126-r91598"],"url":"https://museum.vlsi.kr/objects/cw-8c512563a2ccdec4"},{"id":"cw-8c518720fc2f581b","name":"AMD-K6/300AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Desktop K6","year":1998,"architecture":"K6","process":"250 nm","aliases":["Amd k6 amd-k6 300afr"],"fields":[{"key":"Model name","value":"AMD-K6/300AFR","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"AMD-K6/300AFR","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6/300AFR","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 1998","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 5, 1998","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Desktop K6","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Little Foot","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":250,"unit":"nm","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8800000,"unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":68,"unit":"mm²","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket 7","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c518720fc2f581b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6%2Famd-k6%2F300afr&oldid=25970","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8284-r25970","location":"Amd/k6/amd-k6/300afr · revision 25970 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1.5,"unit":"MiB","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x256 KiB","unit":"","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. 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Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"6x2 MiB","unit":"","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. 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Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-655-r1590","location":"Intel/core i7/i7-9750h · revision 1590 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. Not an independent measurement.","entityId":"cw-8c571da3691c1f96","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-9750h&oldid=1590","sourceDate":"2021-08-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-08-01. 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Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"m5-6Y57","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. 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Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. 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Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core m5","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"m-6Y","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1100,"unit":"MHz","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2800,"unit":"MHz","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-08-28. 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Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Skylake","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake Y","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":78,"unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":1750000000,"unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":98.57,"unit":"mm²","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":4.5,"unit":"W","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":5,"unit":"°C","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":27.81,"unit":"GiB/s","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 515","unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":900,"unit":"MHz","sourceId":"chipswiki-4981-r16103","location":"Intel/core m/m5-6y57 · revision 16103 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-08-28. Not an independent measurement.","entityId":"cw-8c58e7d783e9a9a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20m%2Fm5-6y57&oldid=16103","sourceDate":"2018-08-28","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4981-r16103"],"url":"https://museum.vlsi.kr/objects/cw-8c58e7d783e9a9a3"},{"id":"cw-8c6b7231122c7675","name":"Core i7-4850HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","year":2013,"architecture":"Haswell","process":"22 nm","aliases":["Intel core i7 i7-4850hq"],"fields":[{"key":"Model name","value":"Intel Core i7-4850HQ","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-4850HQ","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8064701509800","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 2, 2013","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 4, 2013","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR18H","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Shark Bay","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":22,"unit":"nm","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":47,"unit":"W","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7867-r25370","location":"Intel/core i7/i7-4850hq · revision 25370 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-4850hq&oldid=25370","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1364","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1364,"unit":"","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.7,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.4,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":32,"unit":"mm","sourceId":"chipswiki-31462-r92407","location":"Template:Packages/intel/fcbga-1364 · revision 92407 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8c6b7231122c7675","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1364&oldid=92407","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7867-r25370","chipswiki-31462-r92407"],"url":"https://museum.vlsi.kr/objects/cw-8c6b7231122c7675"},{"id":"cw-8ca47d507fcf66de","name":"ThunderX2 CN9965","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","year":2018,"architecture":"Vulcan","process":"16 nm","aliases":["Cavium thunderx2 cn9965"],"fields":[{"key":"Model name","value":"ThunderX2 CN9965","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN9965","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9965-2500LG4077-Y21-G","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9965-2400LG4077-Y21-G","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9965-2300LG4077-Y21-G","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9965-2200LG4077-Y21-G","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / part number 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 4","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"part number 4","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9965-2100LG4077-Y21-G","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / part number 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 5","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"part number 5","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9965-2000LG4077-Y21-G","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / part number 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 6","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"part number 6","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN9965-1800LG4077-Y21-G","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / part number 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 7","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"part number 7","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 7, 2018","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 7, 2018","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"ThunderX2","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1800,"unit":"MHz","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":2000,"unit":"MHz","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":2100,"unit":"MHz","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 4","value":2200,"unit":"MHz","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / frequency 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 4","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"Multiple clock domains; raw parameter frequency 4","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 5","value":2300,"unit":"MHz","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / frequency 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 5","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"Multiple clock domains; raw parameter frequency 5","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 6","value":2400,"unit":"MHz","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / frequency 6","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 6","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"Multiple clock domains; raw parameter frequency 6","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 7","value":2500,"unit":"MHz","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / frequency 7","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 7","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"Multiple clock domains; raw parameter frequency 7","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8.1","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Vulcan","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":16,"unit":"nm","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":20,"unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":40,"unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1.25,"unit":"MiB","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":640,"unit":"KiB","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":640,"unit":"KiB","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"20x32 KiB","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":5,"unit":"MiB","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"20x256 KiB","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":20,"unit":"MiB","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"20x1 MiB","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-4334-r13947","location":"Cavium/thunderx2/cn9965 · revision 13947 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-12-04. Not an independent measurement.","entityId":"cw-8ca47d507fcf66de","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Fthunderx2%2Fcn9965&oldid=13947","sourceDate":"2018-12-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4334-r13947"],"url":"https://museum.vlsi.kr/objects/cw-8ca47d507fcf66de"},{"id":"cw-8caa52a14055c3c4","name":"CN3120-550 CP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3120-550bg868-cp"],"fields":[{"key":"Model name","value":"Cavium CN3120-550 CP","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3120-550 CP","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3120-550BG868-CP","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 1, 2006","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":550,"unit":"MHz","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":80,"unit":"KiB","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x8 KiB","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8241-r25901","location":"Cavium/octeon/cn3120-550bg868-cp · revision 25901 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3120-550bg868-cp&oldid=25901","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8caa52a14055c3c4","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8241-r25901","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-8caa52a14055c3c4"},{"id":"cw-8cfdd40852d3c759","name":"Xeon E3-1270 v6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1200 v6","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel xeon e3 e3-1270 v6"],"fields":[{"key":"Model name","value":"Xeon E3-1270 v6","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1270 v6","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8067702870648","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80677E31270V6","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR326","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 28, 2017","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 28, 2017","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1200 v6","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3800,"unit":"MHz","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4200,"unit":"MHz","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake DT","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":72,"unit":"W","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8cfdd40852d3c759","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7765-r25155","location":"Intel/xeon e3/e3-1270 v6 · revision 25155 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1995,"unit":"","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":40,"unit":"MHz","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv3","unit":"","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM7","unit":"","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM710A","unit":"","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.5,"unit":"µm","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":570295,"unit":"","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":34,"unit":"mm²","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":8,"unit":"KiB","sourceId":"chipswiki-7624-r24879","location":"Vti/vl86cx/vy86c710a · revision 24879 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-144","unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":144,"unit":"","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.5,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":20,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":20,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.6,"unit":"mm","sourceId":"chipswiki-31401-r92231","location":"Template:Packages/vti/tqfp-144 · revision 92231 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d291639ce93064b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","sourceDate":"2017-09-10","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7624-r24879","chipswiki-31401-r92231"],"url":"https://museum.vlsi.kr/objects/cw-8d291639ce93064b"},{"id":"cw-8d31e21de61b79a3","name":"Xeon Platinum 9222","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"9200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon platinum 9222"],"fields":[{"key":"Model name","value":"Xeon Platinum 9222","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":9222,"unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Platinum","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":9200,"unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Walker Pass","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake AP","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":32,"unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":64,"unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"2 TiB","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":250,"unit":"W","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":2,"unit":"MiB","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":1,"unit":"MiB","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":1,"unit":"MiB","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"32x32 KiB","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":32,"unit":"MiB","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"32x1 MiB","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":71.5,"unit":"MiB","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"52x1.375 MiB","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":12,"unit":"","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":262.26,"unit":"GiB/s","sourceId":"chipswiki-3703-r11250","location":"Intel/xeon platinum/9222 · revision 11250 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-04-04. Not an independent measurement.","entityId":"cw-8d31e21de61b79a3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F9222&oldid=11250","sourceDate":"2019-04-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3703-r11250"],"url":"https://museum.vlsi.kr/objects/cw-8d31e21de61b79a3"},{"id":"cw-8d67f9f11f3dceff","name":"Xeon E7-4807","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E7-4800","year":2011,"architecture":"Westmere","process":"32 nm","aliases":["Intel xeon e7 e7-4807"],"fields":[{"key":"Model name","value":"Xeon E7-4807","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E7-4807","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80615006432AB","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 5, 2011","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E7","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E7-4800","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1866.66,"unit":"MHz","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4.8,"unit":"GT/s","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLC3L","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Boxboro","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Boxboro","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Westmere EX","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":47,"unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A2","unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":2600000000,"unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.35,"unit":"V","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":95,"unit":"W","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8d67f9f11f3dceff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e7%2Fe7-4807&oldid=25072","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-7702-r25072","location":"Intel/xeon e7/e7-4807 · revision 25072 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-6320","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201926904","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80662I36320","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-6000","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3900,"unit":"MHz","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":51,"unit":"W","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7977-r25554","location":"Intel/core i3/i3-6320 · revision 25554 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6320&oldid=25554","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCLGA-1151","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"LGA","unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1151,"unit":"","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.914,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":4.4,"unit":"mm","sourceId":"chipswiki-31379-r92181","location":"Template:Packages/intel/fclga-1151 · revision 92181 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8dc6e2bd86508eaf","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","sourceDate":"2017-10-26","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7977-r25554","chipswiki-31379-r92181"],"url":"https://museum.vlsi.kr/objects/cw-8dc6e2bd86508eaf"},{"id":"cw-8de50c2df474b1ba","name":"Ryzen Embedded V2718","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"V2000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen embedded v2718"],"fields":[{"key":"Model name","value":"Ryzen Embedded V2718","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. 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Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"V2718","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000242","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. 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Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"V2000","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. 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Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8 × 32 KiB","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8 × 32 KiB","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8 × 512 KiB","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2 × 4 MiB","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":63.58,"unit":"GiB/s","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1600,"unit":"MHz","sourceId":"chipswiki-880-r2291","location":"Amd/ryzen embedded/v2718 · revision 2291 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-8de50c2df474b1ba","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-880-r2291"],"url":"https://museum.vlsi.kr/objects/cw-8de50c2df474b1ba"},{"id":"cw-8de7d3766fe34931","name":"Core i7-6950X Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6900","year":2016,"architecture":"Broadwell","process":"14 nm","aliases":["Intel core i7ee i7-6950x"],"fields":[{"key":"Model name","value":"Core i7-6950X Extreme Edition","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6950X","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80671I76950X","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BXC80671I76950X","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8067102055800","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / part number 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 3","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"part number 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2PA","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 31, 2016","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6900","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Broadwell","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Wellsburg","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Broadwell E","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"M0","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":3400000000,"unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":246,"unit":"mm²","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":20,"unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GiB","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":140,"unit":"W","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":96,"unit":"°C","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA-2011 v3","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":320,"unit":"KiB","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":320,"unit":"KiB","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"10x32 KiB","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2.5,"unit":"MiB","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"10x256 KiB","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":25,"unit":"MiB","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"10x2.5 MiB","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{cache info}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"20-way set associative","unit":"","sourceId":"chipswiki-3785-r11761","location":"Intel/core i7ee/i7-6950x · revision 11761 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-03-24. Not an independent measurement.","entityId":"cw-8de7d3766fe34931","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-6950x&oldid=11761","sourceDate":"2019-03-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3785-r11761"],"url":"https://museum.vlsi.kr/objects/cw-8de7d3766fe34931"},{"id":"cw-8de81f7d04e6d395","name":"CN3860-500 NSP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3860-500bg1521-nsp"],"fields":[{"key":"Model name","value":"Cavium CN3860-500 NSP","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3860-500 NSP","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3860-500BG1521-NSP","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x8 KiB","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8198-r25857","location":"Cavium/octeon/cn3860-500bg1521-nsp · revision 25857 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-500bg1521-nsp&oldid=25857","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8de81f7d04e6d395","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8198-r25857","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-8de81f7d04e6d395"},{"id":"cw-8df978faf15174df","name":"QorIQ P1023","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Freescale","series":"P1","year":null,"architecture":"e500","process":"45 nm","aliases":["Freescale qoriq p1023"],"fields":[{"key":"Model name","value":"QorIQ P1023","unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Freescale","unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"P1023","unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"QorIQ","unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"P1","unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"Power ISA v2.03","unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"e500","unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"e500 v2","unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Freescale%2Fqoriq%2Fp1023&oldid=25755","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8096-r25755","location":"Freescale/qoriq/p1023 · revision 25755 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-457&oldid=92173","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TE-PBGA","unit":"","sourceId":"chipswiki-31377-r92173","location":"Template:Packages/freescale/te-pbga-457 · revision 92173 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-457&oldid=92173","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31377-r92173","location":"Template:Packages/freescale/te-pbga-457 · revision 92173 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-457&oldid=92173","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":19,"unit":"mm","sourceId":"chipswiki-31377-r92173","location":"Template:Packages/freescale/te-pbga-457 · revision 92173 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-457&oldid=92173","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":19,"unit":"mm","sourceId":"chipswiki-31377-r92173","location":"Template:Packages/freescale/te-pbga-457 · revision 92173 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8df978faf15174df","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Ffreescale%2Fte-pbga-457&oldid=92173","sourceDate":"2017-10-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8096-r25755","chipswiki-31377-r92173"],"url":"https://museum.vlsi.kr/objects/cw-8df978faf15174df"},{"id":"cw-8e168baf07ad714f","name":"Core i3-330M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-300","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i3 i3-330m"],"fields":[{"key":"Model name","value":"Intel Core i3-330M","unit":"","sourceId":"chipswiki-603-r1408","location":"Intel/core i3/i3-330m · revision 1408 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330m&oldid=1408","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-603-r1408","location":"Intel/core i3/i3-330m · revision 1408 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330m&oldid=1408","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-603-r1408","location":"Intel/core i3/i3-330m · revision 1408 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. 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Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330m&oldid=1408","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004122AG","unit":"","sourceId":"chipswiki-603-r1408","location":"Intel/core i3/i3-330m · revision 1408 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-09-16. 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Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330m&oldid=1408","sourceDate":"2021-09-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-603-r1408","location":"Intel/core i3/i3-330m · revision 1408 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-09-16. 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Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket — package module 1","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 1","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"package module 1","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package — package module 2","value":"BGA-1288","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type — package module 2","value":"BGA","unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins — package module 2","value":1288,"unit":"","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch — package module 2","value":0.7,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length — package module 2","value":34,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width — package module 2","value":28,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height — package module 2","value":2.1,"unit":"mm","sourceId":"chipswiki-31577-r92963","location":"Template:Packages/intel/bga-1288 · revision 92963 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"package module 2","note":"Source-reported parameter; source revision 2021-09-16. Not an independent measurement.","entityId":"cw-8e168baf07ad714f","scope":"package module 2","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","sourceDate":"2016-12-02","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-603-r1408","chipswiki-31578-r92969","chipswiki-31577-r92963"],"url":"https://museum.vlsi.kr/objects/cw-8e168baf07ad714f"},{"id":"cw-8e5ec39175cce8bd","name":"Godson-2D","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Loongson","series":"Godson 2","year":2006,"architecture":"GS464","process":"130 nm","aliases":["Loongson godson 2 2d"],"fields":[{"key":"Model name","value":"Godson-2D","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Loongson","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"STMicroelectronics","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"2D","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November, 2004","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2006,"unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Godson 2","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Godson 2","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":700,"unit":"MHz","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"GS464","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"GS464","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8e5ec39175cce8bd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2d&oldid=24977","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-7682-r24977","location":"Loongson/godson 2/2d · revision 24977 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 1600","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD160BBBM6IAE","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 29, 2017","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Ryzen PRO","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Summit Ridge","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B1","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4800000000,"unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":576,"unit":"KiB","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":384,"unit":"KiB","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x64 KiB","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":16,"unit":"MiB","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x8 MiB","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-7353-r23748","location":"Amd/ryzen 5/pro 1600 · revision 23748 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","sourceDate":"2018-01-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-17. Not an independent measurement.","entityId":"cw-8e833915cdaa884b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7353-r23748","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-8e833915cdaa884b"},{"id":"cw-8e8cc99ae69eec64","name":"Celeron B815","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"800","year":2012,"architecture":"Sandy Bridge","process":"32 nm","aliases":["Intel celeron b815"],"fields":[{"key":"Model name","value":"Celeron B815","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"B815","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062701159901","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR0HZ","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January, 2012","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January, 2012","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":800,"unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"Q0","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":504000000,"unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":131,"unit":"mm²","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Sandy Bridge)","unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-6948-r21635","location":"Intel/celeron/b815 · revision 21635 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","sourceDate":"2018-03-17","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. Not an independent measurement.","entityId":"cw-8e8cc99ae69eec64","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-03-17. 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Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000080","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-100000080WOF","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2021-01-09. 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Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 7, 2019","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":7002,"unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Rome","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":49,"unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / process 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"process 2","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"process 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"4 TiB","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":120,"unit":"W","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8x512 KiB","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":64,"unit":"MiB","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x16 MiB","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":8,"unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":8,"unit":"","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":190.7,"unit":"GiB/s","sourceId":"chipswiki-853-r2233","location":"Amd/epyc/7252 · revision 2233 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-09. Not an independent measurement.","entityId":"cw-8e9ccf2c3336e23f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","sourceDate":"2021-01-09","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-853-r2233"],"url":"https://museum.vlsi.kr/objects/cw-8e9ccf2c3336e23f"},{"id":"cw-8ebb02692dbf5a51","name":"Xeon E3-1240 v6","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1200 v6","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel xeon e3 e3-1240 v6"],"fields":[{"key":"Model name","value":"Xeon E3-1240 v6","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1240 v6","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80677E31240V6","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8067702870649","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR327","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Workstation","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 28, 2017","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 28, 2017","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1200 v6","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake DT","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":72,"unit":"W","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1866","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-7769-r25162","location":"Intel/xeon e3/e3-1240 v6 · revision 25162 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8ebb02692dbf5a51","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7769-r25162"],"url":"https://museum.vlsi.kr/objects/cw-8ebb02692dbf5a51"},{"id":"cw-8ee20b097bc42681","name":"Core i7-8705G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-8000","year":2018,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-8705g"],"fields":[{"key":"Model name","value":"Core i7-8705G","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-8705G","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2018","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2018","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-8000","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3100,"unit":"MHz","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4100,"unit":"MHz","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake G","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 1)","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","alternatives":[{"value":"DDR4-2400","sourceId":"chipswiki-5289-r17295","reason":"Intel/core i7/i7-8705g · revision 17295 · {{memory controller}} / type 2. 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Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 1)","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller / HBM 2 (section 2)","value":"HBM2","unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units — Graphics / Integrated graphics (section 1)","value":24,"unit":"","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-8ee20b097bc42681","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8705g&oldid=17295","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock — Graphics / Integrated graphics (section 1)","value":1100,"unit":"MHz","sourceId":"chipswiki-5289-r17295","location":"Intel/core i7/i7-8705g · revision 17295 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2330E","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FF8062700849000","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR02V","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1333","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":19.87,"unit":"GiB/s","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 3000","unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":650,"unit":"MHz","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-8014-r25595","location":"Intel/core i3/i3-2330e · revision 25595 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA988B","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":37.5,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.552,"unit":"mm","sourceId":"chipswiki-31411-r92269","location":"Template:Packages/intel/pga-988b · revision 92269 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8f37019859469421","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fpga-988b&oldid=92269","sourceDate":"2017-08-20","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8014-r25595","chipswiki-31411-r92269"],"url":"https://museum.vlsi.kr/objects/cw-8f37019859469421"},{"id":"cw-8f37bdbd65e79934","name":"Athlon PRO 300GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"PRO 300","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd athlon pro 300ge"],"fields":[{"key":"Model name","value":"Athlon PRO 300GE","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 300GE","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD300BC6M2OFH","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 30, 2019","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Athlon","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"PRO 300","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3400,"unit":"MHz","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x64 KiB","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x512 KiB","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 1)","value":"DDR4-2666","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 1)","value":64,"unit":"GiB","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 1)","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 1)","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 1)","value":39.74,"unit":"GiB/s","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 3","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Graphics (section 2)","value":"DDR4-2933","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics (section 2)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Graphics (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics (section 2)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Graphics (section 2)","value":64,"unit":"GiB","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics (section 2)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Graphics (section 2)","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics (section 2)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Graphics (section 2)","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics (section 2)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Graphics (section 2)","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics (section 2)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Features (section 3)","value":"DDR4-2933","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 3)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Features (section 3)","value":"Yes","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 3)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Features (section 3)","value":64,"unit":"GiB","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 3)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Features (section 3)","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 3)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Features (section 3)","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 3)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Features (section 3)","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 3)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 3)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Features (section 4)","value":"DDR4-2933","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 4)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 4)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Features (section 4)","value":"Yes","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 4)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 4)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Features (section 4)","value":64,"unit":"GiB","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 4)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 4)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Features (section 4)","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 4)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 4)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Features (section 4)","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 4)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 4)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Features (section 4)","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 4)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 4)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Features (section 5)","value":"DDR4-2933","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 5)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 5)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Features (section 5)","value":"Yes","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 5)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 5)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Features (section 5)","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 5)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 5)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Features (section 5)","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 5)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 5)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Features (section 5)","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 5)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 5)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Features (section 6)","value":"DDR4-2933","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 6)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 6)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Features (section 6)","value":"Yes","unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 6)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 6)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Features (section 6)","value":64,"unit":"GiB","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 6)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 6)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Features (section 6)","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 6)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 6)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Features (section 6)","value":2,"unit":"","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 6)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 6)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Features (section 6)","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-549-r1136","location":"Amd/athlon/pro 300ge · revision 1136 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Features (section 6)","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"Features (section 6)","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","sourceDate":"2022-01-02","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-01-02. Not an independent measurement.","entityId":"cw-8f37bdbd65e79934","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-549-r1136","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-8f37bdbd65e79934"},{"id":"cw-8f50410b229ac435","name":"Ryzen 7 3780U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2019,"architecture":"Zen+","process":"12 nm","aliases":["Amd ryzen 7 3780u"],"fields":[{"key":"Model name","value":"Ryzen 7 3780U","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3780U","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 2019","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 2019","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 7","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen+","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Picasso","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":12,"unit":"nm","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4940000000,"unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4 × 64 KiB","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4 × 32 KiB","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4 × 512 KiB","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1 × 4 MiB","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 8","unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":11,"unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1400,"unit":"MHz","sourceId":"chipswiki-921-r2545","location":"Amd/ryzen 7/3780u · revision 2545 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-10-18. Not an independent measurement.","entityId":"cw-8f50410b229ac435","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","sourceDate":"2020-10-18","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-921-r2545"],"url":"https://museum.vlsi.kr/objects/cw-8f50410b229ac435"},{"id":"cw-8f5eb19e4900d71c","name":"Core i7-6700HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6700hq"],"fields":[{"key":"Model name","value":"Core i7-6700HQ","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6700HQ","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8066202194635","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2FQ","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 1, 2015","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 27, 2015","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2600,"unit":"MHz","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3500,"unit":"MHz","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake H","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics 530","unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":24,"unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-3974-r12661","location":"Intel/core i7/i7-6700hq · revision 12661 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6700hq&oldid=12661","sourceDate":"2019-01-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1440,"unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. 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Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.49,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-01-16. Not an independent measurement.","entityId":"cw-8f5eb19e4900d71c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-3974-r12661","chipswiki-31464-r92410"],"url":"https://museum.vlsi.kr/objects/cw-8f5eb19e4900d71c"},{"id":"cw-8f70ee2c4a5e6ffe","name":"Alchemy Au1200-333MGD","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","year":2005,"architecture":"Au1","aliases":["Alchemy au1200-333mgd"],"fields":[{"key":"Model name","value":"Alchemy Au1200-333MGD","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1200-333MGD","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1200-333MGD","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2005","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 2005","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":333,"unit":"MHz","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":512,"unit":"MiB","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.2,"unit":"V","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":"1500 mW","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":32,"unit":"KiB","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR-400","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-533","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"1.332 GB/s","unit":"","sourceId":"chipswiki-457-r938","location":"Alchemy/au1200-333mgd · revision 938 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-19. Not an independent measurement.","entityId":"cw-8f70ee2c4a5e6ffe","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","sourceDate":"2022-03-19","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-457-r938"],"url":"https://museum.vlsi.kr/objects/cw-8f70ee2c4a5e6ffe"},{"id":"cw-8f99260d95a57e7b","name":"MLU200","kind":"sku","entityType":"product-model","subtype":"sku","company":"Cambricon","year":null,"aliases":["Cambricon mlu mlu200"],"fields":[{"key":"Model name","value":"MLU200","unit":"","sourceId":"chipswiki-5647-r18543","location":"Cambricon/mlu/mlu200 · revision 18543 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-8f99260d95a57e7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu200&oldid=18543","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cambricon","unit":"","sourceId":"chipswiki-5647-r18543","location":"Cambricon/mlu/mlu200 · revision 18543 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-8f99260d95a57e7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu200&oldid=18543","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-5647-r18543","location":"Cambricon/mlu/mlu200 · revision 18543 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-8f99260d95a57e7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu200&oldid=18543","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MLU200","unit":"","sourceId":"chipswiki-5647-r18543","location":"Cambricon/mlu/mlu200 · revision 18543 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-8f99260d95a57e7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu200&oldid=18543","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-5647-r18543","location":"Cambricon/mlu/mlu200 · revision 18543 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-8f99260d95a57e7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu200&oldid=18543","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 7, 2017","unit":"","sourceId":"chipswiki-5647-r18543","location":"Cambricon/mlu/mlu200 · revision 18543 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-8f99260d95a57e7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu200&oldid=18543","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MLU","unit":"","sourceId":"chipswiki-5647-r18543","location":"Cambricon/mlu/mlu200 · revision 18543 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-8f99260d95a57e7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu200&oldid=18543","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MLUv100","unit":"","sourceId":"chipswiki-5647-r18543","location":"Cambricon/mlu/mlu200 · revision 18543 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-8f99260d95a57e7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu200&oldid=18543","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5647-r18543","location":"Cambricon/mlu/mlu200 · revision 18543 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-05-27. Not an independent measurement.","entityId":"cw-8f99260d95a57e7b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cambricon%2Fmlu%2Fmlu200&oldid=18543","sourceDate":"2018-05-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5647-r18543"],"url":"https://museum.vlsi.kr/objects/cw-8f99260d95a57e7b"},{"id":"cw-8fa8719e170e09c1","name":"Core i7-965 Extreme Edition","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Core i7-900","year":2008,"architecture":"Nehalem","process":"45 nm","aliases":["Intel core i7ee i7-965"],"fields":[{"key":"Model name","value":"Core i7-965 Extreme Edition","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-965","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AT80601000918AA","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX80601965","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 17, 2008","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 17, 2008","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7EE","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Core i7-900","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3467,"unit":"MHz","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"QPI","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":6.4,"unit":"GT/s","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBCJ","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Nehalem","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"X58","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Bloomfield","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D0","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":731000000,"unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":263,"unit":"mm²","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":24,"unit":"GiB","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":130,"unit":"W","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"LGA1366","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-7821-r25276","location":"Intel/core i7ee/i7-965 · revision 25276 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-8fa8719e170e09c1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7ee%2Fi7-965&oldid=25276","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7821-r25276"],"url":"https://museum.vlsi.kr/objects/cw-8fa8719e170e09c1"},{"id":"cw-8fe06a2a59f4f57f","name":"Core i5-8305G","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-8000","year":2018,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i5 i5-8305g"],"fields":[{"key":"Model name","value":"Core i5-8305G","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-8305G","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 7, 2018","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 7, 2018","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i5-8000","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2800,"unit":"MHz","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake G","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":6,"unit":"MiB","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x1.5 MiB","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 1)","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","alternatives":[{"value":"DDR4-2400","sourceId":"chipswiki-5292-r17298","reason":"Intel/core i5/i5-8305g · revision 17298 · {{memory controller}} / type 2. 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Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 1)","value":64,"unit":"GiB","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 1)","value":1,"unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 1)","value":2,"unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 1)","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 1)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Memory controller (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller / HBM 2 (section 2)","value":"HBM2","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Memory controller / HBM 2 (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller / HBM 2 (section 2)","value":4,"unit":"GiB","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Memory controller / HBM 2 (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller / HBM 2 (section 2)","value":166.9,"unit":"GiB/s","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller / HBM 2 (section 2)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Memory controller / HBM 2 (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model — Graphics / Integrated graphics (section 1)","value":"HD Graphics 630","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units — Graphics / Integrated graphics (section 1)","value":24,"unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count — Graphics / Integrated graphics (section 1)","value":3,"unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock — Graphics / Integrated graphics (section 1)","value":350,"unit":"MHz","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Integrated graphics (section 1)","note":"Source-reported parameter; source revision 2018-07-15. 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Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Graphics / Integrated graphics (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model — Graphics / Discrete graphics (section 2)","value":"Radeon RX Vega M GL","unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units — Graphics / Discrete graphics (section 2)","value":20,"unit":"","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-15. Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock — Graphics / Discrete graphics (section 2)","value":931,"unit":"MHz","sourceId":"chipswiki-5292-r17298","location":"Intel/core i5/i5-8305g · revision 17298 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Graphics / Discrete graphics (section 2)","note":"Source-reported parameter; source revision 2018-07-15. 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Not an independent measurement.","entityId":"cw-8fe06a2a59f4f57f","scope":"Graphics / Discrete graphics (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-8305g&oldid=17298","sourceDate":"2018-07-15","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5292-r17298"],"url":"https://museum.vlsi.kr/objects/cw-8fe06a2a59f4f57f"},{"id":"cw-900d070d031a7d49","name":"CN3110-400 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3100","year":2006,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3110-400bg868-exp"],"fields":[{"key":"Model name","value":"Cavium CN3110-400 EXP","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3110-400 EXP","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3110-400BG868-EXP","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 30, 2006","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3100","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":40,"unit":"KiB","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":8,"unit":"KiB","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x8 KiB","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":256,"unit":"KiB","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x256 KiB","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Cache (section 1)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Cache (section 1)","value":"Yes","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Cache (section 1)","value":4,"unit":"GiB","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Cache (section 1)","value":1,"unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Cache (section 1)","value":4.97,"unit":"GiB/s","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Cache (section 1)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"Cache (section 1)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type — Memory controller (section 2)","value":"DDR2-667","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC — Memory controller (section 2)","value":"Yes","unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory — Memory controller (section 2)","value":2,"unit":"GiB","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels — Memory controller (section 2)","value":1,"unit":"","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth — Memory controller (section 2)","value":1.24,"unit":"GiB/s","sourceId":"chipswiki-8264-r25924","location":"Cavium/octeon/cn3110-400bg868-exp · revision 25924 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Memory controller (section 2)","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"Memory controller (section 2)","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3110-400bg868-exp&oldid=25924","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"HSBGA-868","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":868,"unit":"","sourceId":"chipswiki-31467-r92415","location":"Template:Packages/cavium/hsbga-868 · revision 92415 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-900d070d031a7d49","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Fhsbga-868&oldid=92415","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8264-r25924","chipswiki-31467-r92415"],"url":"https://museum.vlsi.kr/objects/cw-900d070d031a7d49"},{"id":"cw-902a8c1f70a3fcdd","name":"EPYC Embedded 3301","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"3000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd epyc embedded 3301"],"fields":[{"key":"Model name","value":"EPYC Embedded 3301","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":3301,"unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 21, 2018","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"EPYC Embedded","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3000,"unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3000,"unit":"MHz","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Snowy Owl","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B2","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9600000000,"unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":213,"unit":"mm²","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":12,"unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":95,"unit":"°C","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1152,"unit":"KiB","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":768,"unit":"KiB","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"12 × 64 KiB","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":384,"unit":"KiB","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"12 × 32 KiB","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":6,"unit":"MiB","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"12 × 512 KiB","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":32,"unit":"MiB","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4 × 8 MiB","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2666","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"85.33 GB/s","unit":"","sourceId":"chipswiki-406-r876","location":"Amd/epyc embedded/3301 · revision 876 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3301&oldid=876","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"SP4","unit":"","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FC-OBGA","unit":"","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.8,"unit":"mm","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":45,"unit":"mm","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":45,"unit":"mm","sourceId":"chipswiki-31097-r91556","location":"Template:Packages/amd/package sp4 · revision 91556 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-04-06. Not an independent measurement.","entityId":"cw-902a8c1f70a3fcdd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","sourceDate":"2022-04-06","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-406-r876","chipswiki-31097-r91556"],"url":"https://museum.vlsi.kr/objects/cw-902a8c1f70a3fcdd"},{"id":"cw-9042f6a9e6c657ff","name":"Pentium Gold G5500T","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5000","year":2018,"architecture":"Coffee Lake","process":"14 nm","aliases":["Intel pentium gold g5500t"],"fields":[{"key":"Model name","value":"Pentium Gold G5500T","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"G5500T","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8068403377713","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR3YE","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Pentium Gold","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5000,"unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake S","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":158,"unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"B0","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":126,"unit":"mm²","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":88,"unit":"°C","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"UHD Graphics 630","unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-6449-r20184","location":"Intel/pentium gold/g5500t · revision 20184 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-9042f6a9e6c657ff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20gold%2Fg5500t&oldid=20184","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-6449-r20184"],"url":"https://museum.vlsi.kr/objects/cw-9042f6a9e6c657ff"},{"id":"cw-9072036f6a311f8b","name":"Core i7-6785R","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6785r"],"fields":[{"key":"Model name","value":"Core i7-6785R","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6785R","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 22, 2016","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 22, 2016","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3300,"unit":"MHz","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3900,"unit":"MHz","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":65,"unit":"W","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Pro Graphics 580","unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":72,"unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":350,"unit":"MHz","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1150,"unit":"MHz","sourceId":"chipswiki-7838-r25331","location":"Intel/core i7/i7-6785r · revision 25331 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6785r&oldid=25331","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1440","unit":"","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-9072036f6a311f8b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31464-r92410","location":"Template:Packages/intel/fcbga-1440 · revision 92410 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"V2748","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. 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Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. 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Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen Embedded","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"V2000","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2900,"unit":"MHz","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4250,"unit":"MHz","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Grey Hawk","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":512,"unit":"KiB","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8 × 32 KiB","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8 × 32 KiB","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":4,"unit":"MiB","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"8 × 512 KiB","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2 × 4 MiB","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":63.58,"unit":"GiB/s","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 7","unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":7,"unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1600,"unit":"MHz","sourceId":"chipswiki-879-r2290","location":"Amd/ryzen embedded/v2748 · revision 2290 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-01-01. Not an independent measurement.","entityId":"cw-9084a8b7b50379fd","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","sourceDate":"2021-01-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-879-r2290"],"url":"https://museum.vlsi.kr/objects/cw-9084a8b7b50379fd"},{"id":"cw-90853665a582cc3e","name":"Core i3-370M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i3-300","year":2010,"architecture":"Westmere","process":"32 nm","aliases":["Intel core i3 i3-370m"],"fields":[{"key":"Model name","value":"Intel Core i3-370M","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-370M","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN80617004119AL","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CP80617004119AL","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 22, 2010","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 22, 2010","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-300","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2399.99,"unit":"MHz","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 1.0","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":2.5,"unit":"GT/s","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":1,"unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBTX","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLBUK","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Westmere","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Calpella","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Ibex Peak","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Arrandale","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":37,"unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"K0","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":382000000,"unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":105,"unit":"°C","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":3,"unit":"MiB","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":15.88,"unit":"GiB/s","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"HD Graphics (Ironlake)","unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":12,"unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":667,"unit":"MHz","sourceId":"chipswiki-7991-r25571","location":"Intel/core i3/i3-370m · revision 25571 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-370m&oldid=25571","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"rPGA-988A","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"rPGA","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":988,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":1,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":36,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":35,"unit":"mm","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":2.12,"unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket-G1","unit":"","sourceId":"chipswiki-31578-r92969","location":"Template:Packages/intel/rpga-988a · revision 92969 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90853665a582cc3e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","sourceDate":"2016-12-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7991-r25571","chipswiki-31578-r92969"],"url":"https://museum.vlsi.kr/objects/cw-90853665a582cc3e"},{"id":"cw-9086ef1e474b4cff","name":"ARMADA 628","kind":"sku","entityType":"product-model","subtype":"soc","company":"Marvell","series":"600","year":2011,"architecture":"Sheeva PJ4","process":"55 nm","aliases":["Marvell armada 628"],"fields":[{"key":"Model name","value":"ARMADA 628","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Marvell","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":628,"unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"88AP628","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 23, 2010","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March, 2011","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"ARMADA 600","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":600,"unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":1500,"unit":"MHz","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":624,"unit":"MHz","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv6","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sheeva PJ4","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"ARMADA","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sheeva PJ4","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":55,"unit":"nm","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":3,"unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":3,"unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":192,"unit":"KiB","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":96,"unit":"KiB","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"3x32 KiB","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":96,"unit":"KiB","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"3x32 KiB","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3-1066","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":2,"unit":"GiB","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":7.942,"unit":"GiB/s","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"GC1000","unit":"","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":500,"unit":"MHz","sourceId":"chipswiki-7293-r23416","location":"Marvell/armada/628 · revision 23416 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-01-24. Not an independent measurement.","entityId":"cw-9086ef1e474b4cff","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Marvell%2Farmada%2F628&oldid=23416","sourceDate":"2018-01-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-7293-r23416"],"url":"https://museum.vlsi.kr/objects/cw-9086ef1e474b4cff"},{"id":"cw-909718911086242d","name":"Celeron N3060","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"N3000","year":2016,"architecture":"Airmont","process":"14 nm","aliases":["Intel celeron n3060"],"fields":[{"key":"Model name","value":"Intel Celeron N3060","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"N3060","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"FH8066501715929","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2KN","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 15, 2016","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 15, 2016","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"N3000","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1600,"unit":"MHz","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":2480,"unit":"MHz","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"IDI","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Airmont","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Braswell","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D1","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":8,"unit":"GiB","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":6,"unit":"W","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"BGA1170","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{chip}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":48,"unit":"KiB","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x24 KiB","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":0,"unit":"KiB","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{cache info}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"No L3$","unit":"","sourceId":"chipswiki-4362-r14101","location":"Intel/celeron/n3060 · revision 14101 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-11-24. Not an independent measurement.","entityId":"cw-909718911086242d","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3060&oldid=14101","sourceDate":"2018-11-24","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4362-r14101"],"url":"https://museum.vlsi.kr/objects/cw-909718911086242d"},{"id":"cw-909860b537d24898","name":"Helio X20 M (MT6797M)","kind":"sku","entityType":"product-model","subtype":"soc","company":"MediaTek","series":"Helio X","year":2016,"architecture":"Cortex-A53","process":"20 nm","aliases":["Mediatek helio mt6797m"],"fields":[{"key":"Model name","value":"MediaTek Helio X20 M","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"MediaTek","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Helio X20 M","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MT6797M","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MTK6797M","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 12, 2015","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 16, 2016","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Helio","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Helio X","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2000,"unit":"MHz","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1850,"unit":"MHz","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 3","value":1400,"unit":"MHz","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / frequency 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 3","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"Multiple clock domains; raw parameter frequency 3","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 4 AXI","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A53","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A72","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":20,"unit":"nm","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":10,"unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":10,"unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":6,"unit":"GiB","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","alternatives":[{"value":"8 GiB","sourceId":"chipswiki-1571-r5177","reason":"Mediatek/helio/mt6797m · revision 5177 · {{memory controller}} / max mem. Different source value or unit convention; retained value is unchanged."}],"entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"conflicting"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"14.93 GB/s (13.90 GiB/s)","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T880","unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":4,"unit":"","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":780,"unit":"MHz","sourceId":"chipswiki-1571-r5177","location":"Mediatek/helio/mt6797m · revision 5177 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-14. Not an independent measurement.","entityId":"cw-909860b537d24898","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Mediatek%2Fhelio%2Fmt6797m&oldid=5177","sourceDate":"2019-12-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1571-r5177"],"url":"https://museum.vlsi.kr/objects/cw-909860b537d24898"},{"id":"cw-90b498094c1cea50","name":"MSM6280","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Qualcomm","series":"MSM","year":2005,"architecture":"ARM9","process":"90 nm","aliases":["Qualcomm msm6xxx msm6280"],"fields":[{"key":"Model name","value":"Qualcomm MSM6280","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Qualcomm","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"IBM","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / manufacturer 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"manufacturer 2","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"manufacturer 2","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MSM6280","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 13, 2004","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September, 2005","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"MSM6xxx","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"MSM","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":270,"unit":"MHz","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"AMBA 2","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"ARM9","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"MSM6xxx","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"ARM926EJ-S","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":90,"unit":"nm","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CSP-409","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CSP","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x16 KiB","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1138-r3423","location":"Qualcomm/msm6xxx/msm6280 · revision 3423 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-05-14. Not an independent measurement.","entityId":"cw-90b498094c1cea50","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Qualcomm%2Fmsm6xxx%2Fmsm6280&oldid=3423","sourceDate":"2020-05-14","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1138-r3423"],"url":"https://museum.vlsi.kr/objects/cw-90b498094c1cea50"},{"id":"cw-90e19f3fd57b6734","name":"Atom Z550","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"Z500","year":2009,"architecture":"Bonnell","process":"45 nm","aliases":["Intel atom z550"],"fields":[{"key":"Model name","value":"Atom Z550","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Z550","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AC80566UE041DW","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SLGPT","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 8, 2009","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 8, 2009","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Atom","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Z500","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1999.99,"unit":"MHz","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"533.33 MT/s","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-32","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Bonnell","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Menlow","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Poulsbo","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Silverthorne","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":28,"unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":45,"unit":"nm","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":47212207,"unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":24.18,"unit":"mm²","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":2.4,"unit":"W","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":90,"unit":"°C","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":56,"unit":"KiB","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":24,"unit":"KiB","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x24 KiB","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"6-way set associative","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x512 KiB","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8061-r25697","location":"Intel/atom/z550 · revision 25697 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-441","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"FCBGA","unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":441,"unit":"","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":13,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":14,"unit":"mm","sourceId":"chipswiki-31513-r92656","location":"Template:Packages/intel/fcbga-441 · revision 92656 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90e19f3fd57b6734","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","sourceDate":"2017-04-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8061-r25697","chipswiki-31513-r92656"],"url":"https://museum.vlsi.kr/objects/cw-90e19f3fd57b6734"},{"id":"cw-90e5780886342b2c","name":"Am186EDLV–20VC\\W","kind":"sku","entityType":"product-model","subtype":"sku","company":"AMD","series":"Am186ED","year":1997,"architecture":"80186","aliases":["Amd am186ex am186edlv–20vc\\w"],"fields":[{"key":"Model name","value":"Am186EDLV–20VC\\W","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EDLV–20VC\\W","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EDLV–20VC\\W","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186ED","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14675-r44736","location":"Amd/am186ex/am186edlv–20vc\\w · revision 44736 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-90e5780886342b2c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14675-r44736"],"url":"https://museum.vlsi.kr/objects/cw-90e5780886342b2c"},{"id":"cw-90f2c83efdf156d3","name":"Xeon Gold 5218N","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"5200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon gold 5218n"],"fields":[{"key":"Model name","value":"Xeon Gold 5218N","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"5218N","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504289900","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFD9","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Gold","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":5200,"unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2300,"unit":"MHz","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L0","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L1","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":4,"unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":105,"unit":"W","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-90f2c83efdf156d3","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":119.21,"unit":"GiB/s","sourceId":"chipswiki-1522-r4974","location":"Intel/xeon gold/5218n · revision 4974 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. 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Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-2330M","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04J","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR04L","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June, 2011","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June, 2011","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-2000","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2200,"unit":"MHz","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Sandy Bridge","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Cougar Point","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Sandy Bridge M","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":42,"unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":32,"unit":"nm","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":624000000,"unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":149,"unit":"mm²","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-90fd2943e63b8eab","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330m&oldid=25594","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1.5 MiB","unit":"","sourceId":"chipswiki-8013-r25594","location":"Intel/core i3/i3-2330m · revision 25594 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8646-r26845","location":"Amd/am186/ig80186-3 · revision 26845 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912117a14fc63fc2","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8646-r26845"],"url":"https://museum.vlsi.kr/objects/cw-912117a14fc63fc2"},{"id":"cw-912538b102e37bc1","name":"Core i7-6870HQ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-6000","year":2016,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i7 i7-6870hq"],"fields":[{"key":"Model name","value":"Core i7-6870HQ","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-6870HQ","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2QX","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 2, 2016","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-6000","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2700,"unit":"MHz","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":45,"unit":"W","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-912538b102e37bc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7834-r25325","location":"Intel/core i7/i7-6870hq · revision 25325 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Am186EMLV–20VC\\W","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Am186EMLV–20VC\\W","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1997,"unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186Ex","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186EM","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":20,"unit":"MHz","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"5 MT/s","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Am186","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":3.3,"unit":"V","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":100,"unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / pin count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"I/O lines","value":32,"unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / io lines","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"TQFP-100","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"TQFP","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"TQFP-100","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{mcu}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-14661-r44722","location":"Amd/am186ex/am186emlv–20vc\\w · revision 44722 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-06-30. Not an independent measurement.","entityId":"cw-912927542993febb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","sourceDate":"2017-06-30","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-14661-r44722"],"url":"https://museum.vlsi.kr/objects/cw-912927542993febb"},{"id":"cw-914781685401d3cc","name":"CN3840-500 SCP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3840-500bg1521-scp"],"fields":[{"key":"Model name","value":"Cavium CN3840-500 SCP","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3840-500 SCP","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3840-500BG1521-SCP","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"September 13, 2004","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 1, 2005","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":500,"unit":"MHz","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":320,"unit":"KiB","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"8x32 KiB","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"8x8 KiB","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8215-r25874","location":"Cavium/octeon/cn3840-500bg1521-scp · revision 25874 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-500bg1521-scp&oldid=25874","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-914781685401d3cc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8215-r25874","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-914781685401d3cc"},{"id":"cw-9155689a5a4460f0","name":"Alchemy Au1000-266MCI","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Alchemy","year":2001,"architecture":"Au1","process":"180 nm","aliases":["Alchemy au1000-266mci"],"fields":[{"key":"Model name","value":"Alchemy Au1000-266MCI","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Au1000-266MCI","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"Au1000-266MCI","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 13, 2000","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"February 2001","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Alchemy","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266,"unit":"MHz","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS32","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Au1","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"DA","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HA","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HB","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HC","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"HD","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / core stepping 5","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 5","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"core stepping 5","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-9155689a5a4460f0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-487-r971","location":"Alchemy/au1000-266mci · revision 971 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Alchemy","unit":"","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. 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Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":16,"unit":"KiB","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":16,"unit":"KiB","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1 × 16 KiB","unit":"","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"SDR-133","unit":"","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"0.500 GB/s","unit":"","sourceId":"chipswiki-478-r962","location":"Alchemy/au1500-500mbc · revision 962 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-03-16. Not an independent measurement.","entityId":"cw-915b2543fcc8369f","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","sourceDate":"2022-03-16","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-478-r962"],"url":"https://museum.vlsi.kr/objects/cw-915b2543fcc8369f"},{"id":"cw-9162c8f0a7129420","name":"K6-2E+/400ACR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2+ Embedded","year":2000,"architecture":"K6-III","process":"0.18 µm","aliases":["Amd k6-2+ k6-2e+-400acr"],"fields":[{"key":"Model name","value":"K6-2E+/400ACR","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E+/400ACR","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E+/400ACR","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":16.5,"unit":"W","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2,"unit":"V","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"September 25, 2000","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2+","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2+ Embedded","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"100 MT/s","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-III","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":13,"unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":4,"unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":5,"unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":6,"unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / core stepping 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 3","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"core stepping 3","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":7,"unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / core stepping 4","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 4","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"core stepping 4","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.18,"unit":"µm","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":64,"unit":"KiB","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":128,"unit":"KiB","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x128 KiB","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1001-r2852","location":"Amd/k6-2+/k6-2e+-400acr · revision 2852 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-400acr&oldid=2852","sourceDate":"2020-07-26","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":321,"unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":2.54,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":49.5,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":3.3,"unit":"mm","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super Socket 7","unit":"","sourceId":"chipswiki-31126-r91598","location":"Template:Packages/amd/super socket 7 · revision 91598 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-07-26. Not an independent measurement.","entityId":"cw-9162c8f0a7129420","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsuper%20socket%207&oldid=91598","sourceDate":"2020-07-27","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1001-r2852","chipswiki-31126-r91598"],"url":"https://museum.vlsi.kr/objects/cw-9162c8f0a7129420"},{"id":"cw-91c1e7cb9395b114","name":"Celeron 3965Y","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"3900","year":null,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel celeron 3965y"],"fields":[{"key":"Model name","value":"Celeron 3965Y","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"3965Y","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR34E","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 2017","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Celeron","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":3900,"unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1300,"unit":"MHz","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake Y","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"H0","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":2,"unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91c1e7cb9395b114","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x1 MiB","unit":"","sourceId":"chipswiki-8034-r25665","location":"Intel/celeron/3965y · revision 25665 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"MG80186-3","unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"MG80186-3","unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":1984,"unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1984,"unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am186","unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Am186","unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":8,"unit":"MHz","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"2 MT/s","unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":80186,"unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":80186,"unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":1.5,"unit":"µm","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":55000,"unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":16,"unit":"bit","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":1,"unit":"MiB","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-68","unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"CPGA-68","unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{cache info}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":0,"unit":"KiB","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x0 KiB","unit":"","sourceId":"chipswiki-8636-r26835","location":"Amd/am186/mg80186-3 · revision 26835 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91e7a1543867d55a","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8636-r26835"],"url":"https://museum.vlsi.kr/objects/cw-91e7a1543867d55a"},{"id":"cw-91eb8d782e93cbdc","name":"Duron 950 (Camaro)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Mobile","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhm0950aqs1b"],"fields":[{"key":"Model name","value":"Duron 950","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 950","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHM0950AQS1B","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 12, 2001","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 12, 2001","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Mobile","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":950,"unit":"MHz","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.45,"unit":"V","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":25,"unit":"W","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8412-r26120","location":"Amd/duron/dhm0950aqs1b · revision 26120 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-91eb8d782e93cbdc","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8412-r26120"],"url":"https://museum.vlsi.kr/objects/cw-91eb8d782e93cbdc"},{"id":"cw-91f44ae965ea282b","name":"Core i7-7660U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i7-7600","year":2017,"architecture":"Kaby Lake","process":"14 nm","aliases":["Intel core i7 i7-7660u"],"fields":[{"key":"Model name","value":"Core i7-7660U","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i7-7660U","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR368","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 3, 2017","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i7","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i7-7600","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2500,"unit":"MHz","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Kaby Lake","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Kaby Lake U","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"J1","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-1866","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{memory controller}} / type 3","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 3","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"type 3","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics 640","unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":48,"unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":300,"unit":"MHz","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1100,"unit":"MHz","sourceId":"chipswiki-4728-r15166","location":"Intel/core i7/i7-7660u · revision 15166 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","sourceDate":"2018-10-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1356","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1356,"unit":"","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pitch","value":0.65,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package pitch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":42,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31463-r92408","location":"Template:Packages/intel/fcbga-1356 · revision 92408 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-10-04. Not an independent measurement.","entityId":"cw-91f44ae965ea282b","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1356&oldid=92408","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-4728-r15166","chipswiki-31463-r92408"],"url":"https://museum.vlsi.kr/objects/cw-91f44ae965ea282b"},{"id":"cw-923722a17f56c69c","name":"Ryzen 5 PRO 2400GE","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"2000","year":2018,"architecture":"Zen","process":"14 nm","aliases":["Amd ryzen 5 pro 2400ge"],"fields":[{"key":"Model name","value":"Ryzen 5 PRO 2400GE","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"GlobalFoundries","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"PRO 2400GE","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"YD240BC6FBMPK","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May 10, 2018","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May 10, 2018","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":2000,"unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3800,"unit":"MHz","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Promontory","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Raven Ridge","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":1,"unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4950000000,"unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":209.78,"unit":"mm²","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":35,"unit":"W","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":256,"unit":"KiB","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x64 KiB","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x512 KiB","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"1x4 MiB","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2933","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":43.71,"unit":"GiB/s","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon RX Vega 11","unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":11,"unit":"","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1250,"unit":"MHz","sourceId":"chipswiki-1814-r6072","location":"Amd/ryzen 5/pro 2400ge · revision 6072 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","sourceDate":"2019-10-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"µOPGA-1331","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"PGA","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1331,"unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket AM4","unit":"","sourceId":"chipswiki-31477-r92441","location":"Template:Packages/amd/socket am4 · revision 92441 · {{#subobject:package}} / socket","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-10-03. Not an independent measurement.","entityId":"cw-923722a17f56c69c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","sourceDate":"2017-06-08","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1814-r6072","chipswiki-31477-r92441"],"url":"https://museum.vlsi.kr/objects/cw-923722a17f56c69c"},{"id":"cw-925826e914e92ba9","name":"CN3830-400 EXP","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Cavium","series":"CN3800","year":2005,"architecture":"cnMIPS","process":"130 nm","aliases":["Cavium octeon cn3830-400bg1521-exp"],"fields":[{"key":"Model name","value":"Cavium CN3830-400 EXP","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Cavium","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3830-400 EXP","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CN3830-400BG1521-EXP","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Networking","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"August 22, 2005","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":400,"unit":"MHz","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"MIPS64","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"cnMIPS","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"cnMIPS","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":160,"unit":"KiB","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x8 KiB","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8229-r25888","location":"Cavium/octeon/cn3830-400bg1521-exp · revision 25888 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3830-400bg1521-exp&oldid=25888","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-925826e914e92ba9","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8229-r25888","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-925826e914e92ba9"},{"id":"cw-9280fd469e3e2bcb","name":"Ryzen 5 4600U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"4000","year":2020,"architecture":"Zen 2","process":"7 nm","aliases":["Amd ryzen 5 4600u"],"fields":[{"key":"Model name","value":"Ryzen 5 4600U","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"4600U","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"100-000000105","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"January 6, 2020","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Ryzen 5","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4000,"unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / turbo frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Zen 2","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Renoir","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":23,"unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":96,"unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"A1","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":7,"unit":"nm","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9800000000,"unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":156,"unit":"mm²","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":6,"unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":12,"unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":384,"unit":"KiB","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":192,"unit":"KiB","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":192,"unit":"KiB","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"6x32 KiB","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":3,"unit":"MiB","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"6x512 KiB","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x4 MiB","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-3200","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4x-4266","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"68.27 GB/s","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Radeon Vega 6","unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":6,"unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":4,"unit":"","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. Not an independent measurement.","entityId":"cw-9280fd469e3e2bcb","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","sourceDate":"2021-06-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1500,"unit":"MHz","sourceId":"chipswiki-691-r1686","location":"Amd/ryzen 5/4600u · revision 1686 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2021-06-03. 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Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i5-4670R","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CL8064701508403","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"June 2, 2013","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"June 4, 2013","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3700,"unit":"MHz","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 2.0","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":5,"unit":"GT/s","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR18M","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Haswell","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":46,"unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"C0","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bits","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-92c12cb23f470178","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-4670r&oldid=25486","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"12-way set associative","unit":"","sourceId":"chipswiki-7939-r25486","location":"Intel/core i5/i5-4670r · revision 25486 · {{cache info}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"CN3860-600 SCP","unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"OCTEON","unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"CN3800","unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":600,"unit":"MHz","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":16,"unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":16,"unit":"GiB","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":640,"unit":"KiB","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x8 KiB","unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x1 MiB","unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8194-r25853","location":"Cavium/octeon/cn3860-600bg1521-scp · revision 25853 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93158e3981f5a506","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8194-r25853","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-93158e3981f5a506"},{"id":"cw-933df3b8ea34e390","name":"Duron 1200 (Morgan)","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"Duron Desktop","year":2001,"architecture":"K7","process":"180 nm","aliases":["Amd duron dhd1200amt1b"],"fields":[{"key":"Model name","value":"Duron 1200","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Duron 1200","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"DHD1200AMT1B","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Desktop","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 15, 2001","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 15, 2001","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Duron","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Duron Desktop","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1200,"unit":"MHz","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"200 MT/s","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K7","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Morgan","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":7,"unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":0,"unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":180,"unit":"nm","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":25180000,"unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":105.68,"unit":"mm²","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.75,"unit":"V","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":54.7,"unit":"W","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-453","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Socket A","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":64,"unit":"KiB","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{cache info}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x64 KiB","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{cache info}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-8426-r26134","location":"Amd/duron/dhd1200amt1b · revision 26134 · {{cache info}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-933df3b8ea34e390","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8426-r26134"],"url":"https://museum.vlsi.kr/objects/cw-933df3b8ea34e390"},{"id":"cw-93898419169d4839","name":"K6-2E/266AFR","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Desktop","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2e-266afr"],"fields":[{"key":"Model name","value":"K6-2E/266AFR","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2E/266AFR","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2E/266AFR","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"May, 1999","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"May, 1999","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Desktop","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":266.66,"unit":"MHz","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"66.66 MT/s","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":2.2,"unit":"V","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8329-r26024","location":"Amd/k6-2/k6-2e-266afr · revision 26024 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93898419169d4839","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2e-266afr&oldid=26024","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8329-r26024"],"url":"https://museum.vlsi.kr/objects/cw-93898419169d4839"},{"id":"cw-939a80ae23d715e0","name":"NNP-I 1300","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"NNP-I","year":2019,"architecture":"Spring Hill","process":"10 nm","aliases":["Nervana nnp nnp-i 1300"],"fields":[{"key":"Model name","value":"NNP-I 1300","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"NNP-I 1300","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"November 12, 2019","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"November 12, 2019","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"NNP","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"NNP-I","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Spring Hill","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":8500000000,"unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":239,"unit":"mm²","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":24,"unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":75,"unit":"W","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-4200","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":"67.2 GB/s","unit":"","sourceId":"chipswiki-1354-r4482","location":"Nervana/nnp/nnp-i 1300 · revision 4482 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2020-02-01. Not an independent measurement.","entityId":"cw-939a80ae23d715e0","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Nervana%2Fnnp%2Fnnp-i%201300&oldid=4482","sourceDate":"2020-02-01","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1354-r4482"],"url":"https://museum.vlsi.kr/objects/cw-939a80ae23d715e0"},{"id":"cw-939c0dd5767648af","name":"Baikal-M","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Arm","series":"Baikal","year":2017,"architecture":"Cortex-A57","process":"28 nm","aliases":["Baikal baikal-m"],"fields":[{"key":"Model name","value":"Baikal-M","unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"ARM Holdings","unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"Baikal-M","unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"Jan 28, 2016","unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2017,"unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Baikal","unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2000,"unit":"MHz","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A57","unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A57","unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":28,"unit":"nm","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":128,"unit":"GB","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","alternatives":[{"value":"128 GiB","sourceId":"chipswiki-1584-r5281","reason":"Baikal/baikal-m · revision 5281 · {{memory controller}} / max mem. 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Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-T628","unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":8,"unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU base clock","value":850,"unit":"MHz","sourceId":"chipswiki-1584-r5281","location":"Baikal/baikal-m · revision 5281 · {{integrated graphics}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-03. Not an independent measurement.","entityId":"cw-939c0dd5767648af","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Baikal%2Fbaikal-m&oldid=5281","sourceDate":"2019-12-03","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1584-r5281"],"url":"https://museum.vlsi.kr/objects/cw-939c0dd5767648af"},{"id":"cw-93b6cf94b403e72e","name":"FastMATH 1.5 GHz","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intrinsity","year":2002,"architecture":"FashMATH","process":"130 nm","aliases":["Intrinsity fastmath fastmath-1.5"],"fields":[{"key":"Model name","value":"FastMATH 1.5 GHz","unit":"","sourceId":"chipswiki-7690-r24985","location":"Intrinsity/fastmath/fastmath-1.5 · revision 24985 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93b6cf94b403e72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-1.5&oldid=24985","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intrinsity","unit":"","sourceId":"chipswiki-7690-r24985","location":"Intrinsity/fastmath/fastmath-1.5 · revision 24985 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93b6cf94b403e72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-1.5&oldid=24985","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"TSMC","unit":"","sourceId":"chipswiki-7690-r24985","location":"Intrinsity/fastmath/fastmath-1.5 · revision 24985 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93b6cf94b403e72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-1.5&oldid=24985","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"FastMATH-1.5","unit":"","sourceId":"chipswiki-7690-r24985","location":"Intrinsity/fastmath/fastmath-1.5 · revision 24985 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93b6cf94b403e72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-1.5&oldid=24985","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Embedded","unit":"","sourceId":"chipswiki-7690-r24985","location":"Intrinsity/fastmath/fastmath-1.5 · revision 24985 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93b6cf94b403e72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-1.5&oldid=24985","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":2001,"unit":"","sourceId":"chipswiki-7690-r24985","location":"Intrinsity/fastmath/fastmath-1.5 · revision 24985 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93b6cf94b403e72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-1.5&oldid=24985","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":2002,"unit":"","sourceId":"chipswiki-7690-r24985","location":"Intrinsity/fastmath/fastmath-1.5 · revision 24985 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93b6cf94b403e72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-1.5&oldid=24985","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"FastMATH","unit":"","sourceId":"chipswiki-7690-r24985","location":"Intrinsity/fastmath/fastmath-1.5 · revision 24985 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93b6cf94b403e72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-1.5&oldid=24985","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":1500,"unit":"MHz","sourceId":"chipswiki-7690-r24985","location":"Intrinsity/fastmath/fastmath-1.5 · revision 24985 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93b6cf94b403e72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-1.5&oldid=24985","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"RapidIO","unit":"","sourceId":"chipswiki-7690-r24985","location":"Intrinsity/fastmath/fastmath-1.5 · revision 24985 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93b6cf94b403e72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-1.5&oldid=24985","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-7690-r24985","location":"Intrinsity/fastmath/fastmath-1.5 · revision 24985 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-93b6cf94b403e72e","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-1.5&oldid=24985","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":130,"unit":"nm","sourceId":"chipswiki-7690-r24985","location":"Intrinsity/fastmath/fastmath-1.5 · revision 24985 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":256,"unit":"KiB","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x16 KiB","unit":"","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"64-way set associative","unit":"","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":2,"unit":"MiB","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"1x2 MiB","unit":"","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR2-800","unit":"","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":1,"unit":"","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":11.92,"unit":"GiB/s","sourceId":"chipswiki-8116-r25775","location":"Cavium/octeon plus/cn5860-900bg1521-exp · revision 25775 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1521","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"BGA","unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1521,"unit":"","sourceId":"chipswiki-31466-r92414","location":"Template:Packages/cavium/fcbga-1521 · revision 92414 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-93ba9ebb3280ba73","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","sourceDate":"2017-06-23","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8116-r25775","chipswiki-31466-r92414"],"url":"https://museum.vlsi.kr/objects/cw-93ba9ebb3280ba73"},{"id":"cw-93f57135bfa83899","name":"Xeon E3-1280 v5","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"E3-1200 v5","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel xeon e3 e3-1280 v5"],"fields":[{"key":"Model name","value":"Xeon E3-1280 v5","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"E3-1280 v5","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CM8066201921607","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2CL","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SR2LC","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / s-spec 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"s-spec 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"s-spec 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October 19, 2015","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon E3","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"E3-1200 v5","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3700,"unit":"MHz","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":4000,"unit":"MHz","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"DMI 3.0","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface links","value":4,"unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / bus links","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":8,"unit":"GT/s","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Skylake","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Greenlow","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Sunrise Point","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Skylake DT","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":94,"unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"R0","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":122,"unit":"mm²","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":4,"unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"GiB","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":80,"unit":"W","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":256,"unit":"KiB","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":128,"unit":"KiB","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":128,"unit":"KiB","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"4x32 KiB","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":1,"unit":"MiB","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"4x256 KiB","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":8,"unit":"MiB","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"4x2 MiB","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR3L-1600","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2133","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. Not an independent measurement.","entityId":"cw-93f57135bfa83899","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","sourceDate":"2018-04-07","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":31.79,"unit":"GiB/s","sourceId":"chipswiki-6436-r20134","location":"Intel/xeon e3/e3-1280 v5 · revision 20134 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-04-07. 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Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"i3-8109U","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2018","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i3","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"i3-8000","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3000,"unit":"MHz","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3600,"unit":"MHz","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"OPI","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":4,"unit":"GT/s","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Coffee Lake","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"300 series","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Coffee Lake U","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":142,"unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"D0","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":32,"unit":"GiB","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":28,"unit":"W","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction minimum","value":0,"unit":"°C","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / tjunc min","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Thermal junction maximum","value":100,"unit":"°C","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{chip}} / tjunc max","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":128,"unit":"KiB","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":64,"unit":"KiB","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":64,"unit":"KiB","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":4,"unit":"MiB","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"2x2 MiB","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR3-2133","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{memory controller}} / type 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"type 2","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"type 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":1,"unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":35.76,"unit":"GiB/s","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Iris Plus Graphics 655","unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":47,"unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":3,"unit":"","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU boost clock","value":1050,"unit":"MHz","sourceId":"chipswiki-5286-r17292","location":"Intel/core i3/i3-8109u · revision 17292 · {{integrated graphics}} / max frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8109u&oldid=17292","sourceDate":"2018-07-16","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"FCBGA-1528","unit":"","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. 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Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package pins","value":1528,"unit":"","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package pins","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package length","value":46,"unit":"mm","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package length","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package width","value":24,"unit":"mm","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package width","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package height","value":1.3,"unit":"mm","sourceId":"chipswiki-31288-r91954","location":"Template:Packages/intel/fcbga-1528 · revision 91954 · {{#subobject:package}} / package height","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2018-07-16. Not an independent measurement.","entityId":"cw-9447b3c8764379ef","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1528&oldid=91954","sourceDate":"2018-04-04","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-5286-r17292","chipswiki-31288-r91954"],"url":"https://museum.vlsi.kr/objects/cw-9447b3c8764379ef"},{"id":"cw-949de21d291491b7","name":"Core i5-6260U","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"i5-6000","year":2015,"architecture":"Skylake","process":"14 nm","aliases":["Intel core i5 i5-6260u"],"fields":[{"key":"Model name","value":"Core i5-6260U","unit":"","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Core i5","unit":"","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":2,"unit":"","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":4,"unit":"","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":15,"unit":"W","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"2x32 KiB","unit":"","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":512,"unit":"KiB","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"2x256 KiB","unit":"","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"4-way set associative","unit":"","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-949de21d291491b7","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i5%2Fi5-6260u&oldid=25469","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":2,"unit":"","sourceId":"chipswiki-7929-r25469","location":"Intel/core i5/i5-6260u · revision 25469 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Commercial","unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":1975,"unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Am9080","unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":8080,"unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2.083,"unit":"MHz","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"MCS-80","unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":8080,"unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"MCS-80","unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":8080,"unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":4500,"unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"nMOS","unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":14.48,"unit":"mm²","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / die area","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":8,"unit":"bit","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":64,"unit":"KiB","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":5,"unit":"V","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CerDIP-40","unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CerDIP","unit":"","sourceId":"chipswiki-8470-r26663","location":"Amd/am9080/am9080accb · revision 26663 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94a7ae207be954a8","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8470-r26663"],"url":"https://museum.vlsi.kr/objects/cw-94a7ae207be954a8"},{"id":"cw-94b07f745fb19256","name":"AMD-K6-2/300AMZ","kind":"sku","entityType":"product-model","subtype":"cpu","company":"AMD","series":"K6-2 Mobile","year":1999,"architecture":"K6-2","process":"0.25 µm","aliases":["Amd k6-2 k6-2-300amz"],"fields":[{"key":"Model name","value":"K6-2/300AMZ","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"AMD","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"AMD","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":"K6-2/300AMZ","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"AMD-K6-2/300AMZ","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"March 22, 1999","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"K6-2","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"K6-2 Mobile","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":299.99,"unit":"MHz","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface","value":"FSB","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / bus type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Host interface rate","value":"99.99 MT/s","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / bus rate","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"K6-2","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Super 7","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Chomper Extended","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":5,"unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU model ID","value":8,"unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / core model","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":12,"unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":0.25,"unit":"µm","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Transistors","value":9300000,"unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / transistors","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Die area","value":81,"unit":"mm²","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / die size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":32,"unit":"bit","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":1,"unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":1,"unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":4,"unit":"GiB","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core voltage","value":1.9,"unit":"V","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / v core","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package","value":"CPGA-321","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / package 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Package type","value":"CPGA","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / package 0 type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Socket","value":"Super 7","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{chip}} / socket 0","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":32,"unit":"KiB","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{cache info}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{cache info}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{cache info}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":32,"unit":"KiB","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{cache info}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"1x32 KiB","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{cache info}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"2-way set associative","unit":"","sourceId":"chipswiki-8380-r26075","location":"Amd/k6-2/k6-2-300amz · revision 26075 · {{cache info}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. Not an independent measurement.","entityId":"cw-94b07f745fb19256","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-300amz&oldid=26075","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-8380-r26075"],"url":"https://museum.vlsi.kr/objects/cw-94b07f745fb19256"},{"id":"cw-94cfcebe68c36cc1","name":"Xeon Silver 4216","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"4200","year":2019,"architecture":"Cascade Lake","process":"14 nm","aliases":["Intel xeon silver 4216"],"fields":[{"key":"Model name","value":"Xeon Silver 4216","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Intel","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Intel","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":4216,"unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"CD8069504213901","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / part number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Part number","value":"BX806954216","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / part number 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"part number 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"part number 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"S-spec","value":"SRFBB","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / s-spec","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Server","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"April 2, 2019","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Xeon Silver","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":4200,"unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":2100,"unit":"MHz","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Boost clock","value":3200,"unit":"MHz","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / turbo frequency1","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"one active core","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"one active core","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"x86-64","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cascade Lake","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Platform","value":"Purley","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / platform","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Chipset","value":"Lewisburg","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / chipset","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cascade Lake SP","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU family ID","value":6,"unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / core family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L0","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / core stepping","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Stepping","value":"L1","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / core stepping 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core stepping 2","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"core stepping 2","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":14,"unit":"nm","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":16,"unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":32,"unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":"1 TiB","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / max memory","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":2,"unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Listed TDP","value":100,"unit":"W","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{chip}} / tdp","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 cache","value":1,"unit":"MiB","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l1 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction cache","value":512,"unit":"KiB","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l1i cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l1i break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 instruction associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l1i desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data cache","value":512,"unit":"KiB","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l1d cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data organization","value":"16x32 KiB","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l1d break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L1 data associativity","value":"8-way set associative","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l1d desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 cache","value":16,"unit":"MiB","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l2 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 organization","value":"16x1 MiB","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l2 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L2 associativity","value":"16-way set associative","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l2 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 cache","value":22,"unit":"MiB","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l3 cache","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 organization","value":"16x1.375 MiB","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l3 break","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"L3 associativity","value":"11-way set associative","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{cache size}} / l3 desc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"DDR4-2400","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"Yes","unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":2,"unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":6,"unit":"","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory bandwidth","value":107.3,"unit":"GiB/s","sourceId":"chipswiki-1443-r4883","location":"Intel/xeon silver/4216 · revision 4883 · {{memory controller}} / max bandwidth","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2019-12-29. Not an independent measurement.","entityId":"cw-94cfcebe68c36cc1","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20silver%2F4216&oldid=4883","sourceDate":"2019-12-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-1443-r4883"],"url":"https://museum.vlsi.kr/objects/cw-94cfcebe68c36cc1"},{"id":"cw-94e4b674962c6874","name":"Exynos 9610","kind":"sku","entityType":"product-model","subtype":"soc","company":"Samsung","series":"Exynos 9","year":2018,"architecture":"Cortex-A73","process":"10 nm","aliases":["Samsung exynos 9610"],"fields":[{"key":"Model name","value":"Exynos 9610","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Designer","value":"Samsung","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / designer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Foundry","value":"Samsung","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / manufacturer","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Model number","value":9610,"unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / model number","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Mobile","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Announcement date","value":"March 22, 2018","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / first announced","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Release date","value":"October, 2018","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / first launched","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Product family","value":"Exynos","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / family","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Series","value":"Exynos 9","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / series","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency","value":2300,"unit":"MHz","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"Multiple clock domains; raw parameter frequency","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU clock — frequency 2","value":1700,"unit":"MHz","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / frequency 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"Multiple clock domains; raw parameter frequency 2","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"Multiple clock domains; raw parameter frequency 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"ISA","value":"ARMv8","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / isa","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Architecture","value":"Cortex-A73","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / microarch","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A73","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / core name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Core name","value":"Cortex-A53","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / core name 2","evidenceClass":"third-party-report","confidence":"medium","state":"known","variant":"core name 2","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"core name 2","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process","value":10,"unit":"nm","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / process","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Process technology","value":"CMOS","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / technology","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"CPU word size","value":64,"unit":"bit","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / word size","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Cores","value":8,"unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / core count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Threads","value":8,"unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / thread count","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum CPU sockets","value":1,"unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{chip}} / max cpus","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory type","value":"LPDDR4X-3200","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{memory controller}} / type","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory ECC","value":"No","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{memory controller}} / ecc","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Maximum memory","value":6,"unit":"GiB","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{memory controller}} / max mem","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory controllers","value":4,"unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{memory controller}} / controllers","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Memory channels","value":4,"unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{memory controller}} / channels","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU model","value":"Mali-G72","unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{integrated graphics}} / gpu","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"GPU execution units","value":3,"unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{integrated graphics}} / execution units","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Display count","value":2,"unit":"","sourceId":"chipswiki-327-r649","location":"Samsung/exynos/9610 · revision 649 · {{integrated graphics}} / max displays","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2022-06-29. Not an independent measurement.","entityId":"cw-94e4b674962c6874","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9610&oldid=649","sourceDate":"2022-06-29","retrievedAt":"2026-09-11","researchState":"sourced"}],"sources":["chipswiki-327-r649"],"url":"https://museum.vlsi.kr/objects/cw-94e4b674962c6874"},{"id":"cw-953f3d485f840b4c","name":"AM9080A-1DI","kind":"sku","entityType":"product-model","subtype":"cpu","company":"Intel","series":"8080","year":1975,"architecture":"8080","aliases":["Amd am9080 am9080a-1di"],"fields":[{"key":"Model name","value":"AMD AM9080A-1DI","unit":"","sourceId":"chipswiki-8487-r26680","location":"Amd/am9080/am9080a-1di · revision 26680 · {{chip}} / name","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-953f3d485f840b4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1di&oldid=26680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Market","value":"Industrial","unit":"","sourceId":"chipswiki-8487-r26680","location":"Amd/am9080/am9080a-1di · revision 26680 · {{chip}} / market","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Not an independent measurement.","entityId":"cw-953f3d485f840b4c","scope":"product-model","sourceUrl":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080a-1di&oldid=26680","sourceDate":"2017-12-13","retrievedAt":"2026-09-11","researchState":"sourced"},{"key":"Base clock","value":3.125,"unit":"MHz","sourceId":"chipswiki-8487-r26680","location":"Amd/am9080/am9080a-1di · revision 26680 · {{chip}} / frequency","evidenceClass":"third-party-report","confidence":"medium","state":"known","note":"Source-reported parameter; source revision 2017-12-13. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1200-333mgf"],"contentSha256":"70a410db99b97d31b79cd33c0b46ea4914ab84b95f3b7095dd77d99b3af5f36d"},{"id":"chipswiki-457-r938","title":"Alchemy Au1200-333MGD — ChipsWiki, revision 938","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1200-333mgd&oldid=938","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1200-333mgd"],"contentSha256":"a2a8834973853df31c6a732e2a10c99e7c407e18ed35df572da8d58e31eae444"},{"id":"chipswiki-472-r953","title":"Alchemy Au1100-333MBI — ChipsWiki, revision 953","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbi&oldid=953","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1100-333mbi"],"contentSha256":"1f89bc933333afa401aff69b74b19493564667752caeea4d0ceee3f3feb59d7e"},{"id":"chipswiki-474-r955","title":"Alchemy Au1100-333MBD — ChipsWiki, revision 955","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbd&oldid=955","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1100-333mbd"],"contentSha256":"07971124584a469d04d6a0470bf8fab741aae1c700a03142f6d8886ff9c43c85"},{"id":"chipswiki-475-r956","title":"Alchemy Au1100-333MBC — ChipsWiki, revision 956","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1100-333mbc&oldid=956","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1100-333mbc"],"contentSha256":"e759190d21f3cf7272a09d5ea9e0a345a72e41fbc1da78e1a5cd42667b8c81e5"},{"id":"chipswiki-487-r971","title":"Alchemy Au1000-266MCI — ChipsWiki, revision 971","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1000-266mci&oldid=971","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1000-266mci"],"contentSha256":"8e38637c7b1f87b559b741be451fecf245b36b67d02574c5d7e5d44661b94542"},{"id":"chipswiki-840-r2209","title":"ARM1 — ChipsWiki, revision 2209","url":"https://chipswiki.org/index.php?title=Acorn%2Fmicroarchitectures%2Farm1&oldid=2209","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Acorn/microarchitectures/arm1"],"contentSha256":"8efdb2f9bf295195522e8b1cff77d0d3785b54ff2684e033ecf0aaa44bd78b68"},{"id":"chipswiki-442-r923","title":"Alchemy Au1250-500MGF — ChipsWiki, revision 923","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-500mgf&oldid=923","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1250-500mgf"],"contentSha256":"7a9cba8189043f99cbf0bf9680b0d7d878a9a7c3dad38dec15b8943c590b34c4"},{"id":"chipswiki-445-r926","title":"Alchemy Au1250-400MGD — ChipsWiki, revision 926","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1250-400mgd&oldid=926","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1250-400mgd"],"contentSha256":"6c88d5b4a305d18ccaf828323aa704c9eb054b3409f6b6ee9f93edd3373c7f03"},{"id":"chipswiki-446-r927","title":"Alchemy Au1210-400MGF — ChipsWiki, revision 927","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1210-400mgf&oldid=927","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1210-400mgf"],"contentSha256":"55b88474b6d7c8fa991a7c05d67d1bc48359ed570d6bebb657a26362859cbb23"},{"id":"chipswiki-460-r941","title":"Alchemy Au1550-500MBD — ChipsWiki, revision 941","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-500mbd&oldid=941","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1550-500mbd"],"contentSha256":"623825c5df66ab5aa542cf2d9fae6948fe2da26c8d31e4ddd888e05e83c2751b"},{"id":"chipswiki-462-r943","title":"Alchemy Au1550-400MBD — ChipsWiki, revision 943","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbd&oldid=943","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1550-400mbd"],"contentSha256":"d8e327826be7d391a7add44320728da5d1e3f5243bc855c5157a4f2a4687409f"},{"id":"chipswiki-463-r944","title":"Alchemy Au1550-400MBC — ChipsWiki, revision 944","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1550-400mbc&oldid=944","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1550-400mbc"],"contentSha256":"e76e113e1e0e1bc2bedcef1317f2b2842ddf1610eba1e8c5425f4457823b631a"},{"id":"chipswiki-477-r961","title":"Alchemy Au1500-500MBD — ChipsWiki, revision 961","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbd&oldid=961","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1500-500mbd"],"contentSha256":"a0c47feb673dea0e580f0d7a9d58beb7fda3d024709dcc2d466c79f3d2999369"},{"id":"chipswiki-478-r962","title":"Alchemy Au1500-500MBC — ChipsWiki, revision 962","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-500mbc&oldid=962","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1500-500mbc"],"contentSha256":"3fb49c6efdbd8fe0e346acf90f67208023ef0c9a12826425d30acc5e6b0ccccc"},{"id":"chipswiki-479-r963","title":"Alchemy Au1500-400MBD — ChipsWiki, revision 963","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-400mbd&oldid=963","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1500-400mbd"],"contentSha256":"2b0e0c9e848e5e8e5034ea0428ee3ea39e46dffa3583f67289cee5f5a1cda45a"},{"id":"chipswiki-484-r968","title":"Alchemy Au1500-333MBC — ChipsWiki, revision 968","url":"https://chipswiki.org/index.php?title=Alchemy%2Fau1500-333mbc&oldid=968","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Alchemy/au1500-333mbc"],"contentSha256":"55eeeffacec9001cbf62a76bf1e2b3be985e3f6b5bd81c401040439c60189bc8"},{"id":"chipswiki-3788-r11780","title":"A4-9120C — ChipsWiki, revision 11780","url":"https://chipswiki.org/index.php?title=Amd%2Fa4%2Fa4-9120c&oldid=11780","publisher":"ChipsWiki / WikiChip contributors","published":"2019-03-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/a4/a4-9120c"],"contentSha256":"3c9bb50e45f8c1bab81d9ee2a784008cdafa78e052496184cfa2993b2dfd16c4"},{"id":"chipswiki-4039-r12917","title":"A6-9220C — ChipsWiki, revision 12917","url":"https://chipswiki.org/index.php?title=Amd%2Fa6%2Fa6-9220c&oldid=12917","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/a6/a6-9220c"],"contentSha256":"a29f83c734a2612a1cad48a5c0621fee962304ffa651010f06028a34fd9c659c"},{"id":"chipswiki-8658-r26857","title":"80186/BUC — ChipsWiki, revision 26857","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-buc&oldid=26857","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/80186-buc"],"contentSha256":"6fad23ae8907a8181a5702274b0652cacc23677f0e81ea399db7d14117ec1c98"},{"id":"chipswiki-8659-r26858","title":"80186-6/BZC — ChipsWiki, revision 26858","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-6-bzc&oldid=26858","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/80186-6-bzc"],"contentSha256":"5d963e912d0ca98368b4eb984319c78f733c0f3200deb427bd7e447283847d5c"},{"id":"chipswiki-8661-r26860","title":"Am2070 — ChipsWiki, revision 26860","url":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2070&oldid=26860","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ambric/am2000/am2070"],"contentSha256":"2c80f1e25efd6f6ebad1d4a06bf23d7dc4f3b20cc2669d8cb183cf69a0603dcf"},{"id":"chipswiki-8663-r26862","title":"Am2045 — ChipsWiki, revision 26862","url":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2045&oldid=26862","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ambric/am2000/am2045"],"contentSha256":"c2394ecfe40b116aca106b22726140026c38f40f3b4add6683360966fa56741e"},{"id":"chipswiki-8664-r26863","title":"Am2035 — ChipsWiki, revision 26863","url":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2035&oldid=26863","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ambric/am2000/am2035"],"contentSha256":"b0e6a203e2e9b1b7b1b5491b5b492954cf8688621adcfadaadef21a0e0067549"},{"id":"chipswiki-8666-r26865","title":"Am2024 — ChipsWiki, revision 26865","url":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2024&oldid=26865","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ambric/am2000/am2024"],"contentSha256":"60ed2870f5bb43487422ca00444707087ac4057708111d951de060b0f1d0e3bb"},{"id":"chipswiki-8668-r26867","title":"Am2012 — ChipsWiki, revision 26867","url":"https://chipswiki.org/index.php?title=Ambric%2Fam2000%2Fam2012&oldid=26867","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ambric/am2000/am2012"],"contentSha256":"9aa3f6067a2b5e725406e2b7379ae28debe3bcafdb1d8048e0ae47090fea7c53"},{"id":"chipswiki-8633-r26832","title":"MR80186-6 — ChipsWiki, revision 26832","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-6&oldid=26832","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/mr80186-6"],"contentSha256":"2a786231e21a6d11782642b482bd3ec707cdbec83ccbd95f7261eccdb4e5dcfd"},{"id":"chipswiki-8634-r26833","title":"MR80186-3 — ChipsWiki, revision 26833","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmr80186-3&oldid=26833","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/mr80186-3"],"contentSha256":"20cc8dc2be6dd23ce2e28f6fdbd9a7e6e35a9cd5e3607006b38bb1b3ac23a4fb"},{"id":"chipswiki-8636-r26835","title":"MG80186-3 — ChipsWiki, revision 26835","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fmg80186-3&oldid=26835","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/mg80186-3"],"contentSha256":"929eaf597d7435a7c8bbfb8d82f0d2527a97c884d4a479309fe9fc1dc714c05f"},{"id":"chipswiki-8645-r26844","title":"IG80186-6 — ChipsWiki, revision 26844","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-6&oldid=26844","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/ig80186-6"],"contentSha256":"b7f101550510d5711af87f5427294690f9ef4b4377d451cb03bd1e58658dcdaa"},{"id":"chipswiki-8646-r26845","title":"IG80186-3 — ChipsWiki, revision 26845","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fig80186-3&oldid=26845","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/ig80186-3"],"contentSha256":"8f7692e4388e1047704a06149fce325369842ae4ce28474e6962f7156ba63671"},{"id":"chipswiki-8648-r26847","title":"IC80186-3 — ChipsWiki, revision 26847","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fic80186-3&oldid=26847","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/ic80186-3"],"contentSha256":"d8ae93e8adcdfb3dcf4908db5cdca522a42af8e5e207aace2b74f162ea65f17c"},{"id":"chipswiki-8651-r26850","title":"CG80186-3 — ChipsWiki, revision 26850","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2Fcg80186-3&oldid=26850","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/cg80186-3"],"contentSha256":"b72d65381cb0e552036d6c505dfdad76cd5512018e975fc9c6effce2ad33010b"},{"id":"chipswiki-8657-r26856","title":"80186/BZC — ChipsWiki, revision 26856","url":"https://chipswiki.org/index.php?title=Amd%2Fam186%2F80186-bzc&oldid=26856","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186/80186-bzc"],"contentSha256":"3a72f1f79d4e4bfd4cfc26326598e91228d2d567a20a46b4449a8993c6db44ff"},{"id":"chipswiki-14689-r44750","title":"Am186CC-40KC\\W — ChipsWiki, revision 44750","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-40kc%5Cw&oldid=44750","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186cc-40kc%5Cw"],"contentSha256":"47dbe224f2a2dd4e0b7d0c2c0a69eb3ff9d26a6a2e883666ddc2a3e9822cbf2e"},{"id":"chipswiki-14690-r44751","title":"Am186CC-25KI\\W — ChipsWiki, revision 44751","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-25ki%5Cw&oldid=44751","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186cc-25ki%5Cw"],"contentSha256":"f74071cd8674dfc79b56e1dd4b338b37d55825d2810dfd8401912e79133016dd"},{"id":"chipswiki-14639-r44700","title":"Am186ER–40KI\\W — ChipsWiki, revision 44700","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340ki%5Cw&oldid=44700","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9340ki%5Cw"],"contentSha256":"640eb21863bd6fee597afbec51c8cb5702f5d9fd9f9f6ba13c80c02b2557a9f5"},{"id":"chipswiki-14640-r44701","title":"Am186ER–40KC\\W — ChipsWiki, revision 44701","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340kc%5Cw&oldid=44701","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9340kc%5Cw"],"contentSha256":"3dc9bbfc4b7c205c6942997295d3e00c77081a996a033b44777054deee6deac6"},{"id":"chipswiki-14641-r44702","title":"Am186ER–33VI\\W — ChipsWiki, revision 44702","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333vi%5Cw&oldid=44702","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9333vi%5Cw"],"contentSha256":"63903172f7e519dea17d700a7e567af9e2fa32b5d8c12deba1da7ed82d41d67d"},{"id":"chipswiki-14643-r44704","title":"Am186ER–33KI\\W — ChipsWiki, revision 44704","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9333ki%5Cw&oldid=44704","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9333ki%5Cw"],"contentSha256":"5094d865482ca24878325dbf78689e916e1e1f0faf1f5c0a8a70cabe827f9746"},{"id":"chipswiki-14647-r44708","title":"Am186ER–25KI\\W — ChipsWiki, revision 44708","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9325ki%5Cw&oldid=44708","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9325ki%5Cw"],"contentSha256":"6e3254ec33ce1a4129f062f7b806aed7e7ad79ab34eb3214fd0b1501881054c0"},{"id":"chipswiki-14649-r44710","title":"Am186EM–40VC\\W — ChipsWiki, revision 44710","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9340vc%5Cw&oldid=44710","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186em%E2%80%9340vc%5Cw"],"contentSha256":"516b8267dc8685a1c92dd8a4158535794a2f3a55f519148d867f4c7aeae6396c"},{"id":"chipswiki-14651-r44712","title":"Am186EM–33VC\\W — ChipsWiki, revision 44712","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333vc%5Cw&oldid=44712","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186em%E2%80%9333vc%5Cw"],"contentSha256":"efd67ab519a6cda9cff2c9bb339ffa2f2b12e2a994c3cdb84730993a16684401"},{"id":"chipswiki-14652-r44713","title":"Am186EM–33KC\\W — ChipsWiki, revision 44713","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9333kc%5Cw&oldid=44713","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186em%E2%80%9333kc%5Cw"],"contentSha256":"16616cd9df444cc3ce0f20e94bb6df3f8dd1c96c91b679fc1caca96c323cd0aa"},{"id":"chipswiki-14658-r44719","title":"Am186EM–20KC\\W — ChipsWiki, revision 44719","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186em%E2%80%9320kc%5Cw&oldid=44719","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186em%E2%80%9320kc%5Cw"],"contentSha256":"629d9cf7452ea5351c5d8e37908ef9a2fc33b54228929b5f788b9c5e18506579"},{"id":"chipswiki-14659-r44720","title":"Am186EMLV–25VC\\W — ChipsWiki, revision 44720","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325vc%5Cw&oldid=44720","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186emlv%E2%80%9325vc%5Cw"],"contentSha256":"a337c13ada4018ca03a921f5a7a3a53b8696f48031906514a6a8b02739647014"},{"id":"chipswiki-14660-r44721","title":"Am186EMLV–25KC\\W — ChipsWiki, revision 44721","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9325kc%5Cw&oldid=44721","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186emlv%E2%80%9325kc%5Cw"],"contentSha256":"77409efd228592b65cda14a83ff2becd24bcf6cf7ad662b2838c243512eb8964"},{"id":"chipswiki-14661-r44722","title":"Am186EMLV–20VC\\W — ChipsWiki, revision 44722","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320vc%5Cw&oldid=44722","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186emlv%E2%80%9320vc%5Cw"],"contentSha256":"0414993632c460ed20fd1ffedb3821a55155284f7e30969933fdb973a9adda23"},{"id":"chipswiki-14662-r44723","title":"Am186EMLV–20KC\\W — ChipsWiki, revision 44723","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186emlv%E2%80%9320kc%5Cw&oldid=44723","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186emlv%E2%80%9320kc%5Cw"],"contentSha256":"f8120e65df6971ba6afffa1b46f91728a8e44eccc1353c28b5faacf30881858b"},{"id":"chipswiki-14665-r44726","title":"Am186ED–33VC\\W — ChipsWiki, revision 44726","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9333vc%5Cw&oldid=44726","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186ed%E2%80%9333vc%5Cw"],"contentSha256":"c138d41573556bfe7081d492b2452ca7a01209b178b82e463202e25d6878ae30"},{"id":"chipswiki-14667-r44728","title":"Am186ED–25VC\\W — ChipsWiki, revision 44728","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325vc%5Cw&oldid=44728","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186ed%E2%80%9325vc%5Cw"],"contentSha256":"07bc10b28b2ff2ec2cb21354713080cda92b064ffd513c77787a14509ca2d985"},{"id":"chipswiki-14669-r44730","title":"Am186ED–25KC\\W — ChipsWiki, revision 44730","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9325kc%5Cw&oldid=44730","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186ed%E2%80%9325kc%5Cw"],"contentSha256":"73a241d31fcf12f306674afaa60c74b29153ed4e78217257d0492ff1590b76fa"},{"id":"chipswiki-14672-r44733","title":"Am186ED–20KC\\W — ChipsWiki, revision 44733","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186ed%E2%80%9320kc%5Cw&oldid=44733","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186ed%E2%80%9320kc%5Cw"],"contentSha256":"dd27a0981cbe66b488f097abdc2ac11ebdace8e167706fad1453e81332ad74fd"},{"id":"chipswiki-14674-r44735","title":"Am186EDLV–25KC\\W — ChipsWiki, revision 44735","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9325kc%5Cw&oldid=44735","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186edlv%E2%80%9325kc%5Cw"],"contentSha256":"82e36730b7f42d86b3ab8a8b116c5fafaadd596d32d675382c9d2b5ce2efaf97"},{"id":"chipswiki-14675-r44736","title":"Am186EDLV–20VC\\W — ChipsWiki, revision 44736","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186edlv%E2%80%9320vc%5Cw&oldid=44736","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186edlv%E2%80%9320vc%5Cw"],"contentSha256":"b9360eaf38763070a7a7ddb6ef535c9e0af5642dce0306230e8c83ca36993b97"},{"id":"chipswiki-14677-r44738","title":"Am186CU-50KC\\W — ChipsWiki, revision 44738","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-50kc%5Cw&oldid=44738","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186cu-50kc%5Cw"],"contentSha256":"1824d9b7acf4d6e6418928fa26e99232c9d0e978d5d294605554d1b351f40889"},{"id":"chipswiki-14679-r44740","title":"Am186CU-40KC\\W — ChipsWiki, revision 44740","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-40kc%5Cw&oldid=44740","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186cu-40kc%5Cw"],"contentSha256":"9f402af858c00648ca4223302fab5aef30dd4d9d9b64a3e88ed3567db5a607cf"},{"id":"chipswiki-14680-r44741","title":"Am186CU-25KI\\W — ChipsWiki, revision 44741","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25ki%5Cw&oldid=44741","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186cu-25ki%5Cw"],"contentSha256":"6176b12ba0926e0b34a200ecdb6954b79489b7adcbe43913fb8b4f1af6015106"},{"id":"chipswiki-14681-r44742","title":"Am186CU-25KC\\W — ChipsWiki, revision 44742","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cu-25kc%5Cw&oldid=44742","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186cu-25kc%5Cw"],"contentSha256":"c70c0678e372b57d081afa4670e9dde9d8728745bfdf85b5298adbd09845f211"},{"id":"chipswiki-14685-r44746","title":"Am186CH-25KI\\W — ChipsWiki, revision 44746","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186ch-25ki%5Cw&oldid=44746","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186ch-25ki%5Cw"],"contentSha256":"06c0afcb1e4cbe10976aafd4b1f1a4406553df0471516b9dd14e61467b8f39ae"},{"id":"chipswiki-14687-r44748","title":"Am186CC-50KC\\W — ChipsWiki, revision 44748","url":"https://chipswiki.org/index.php?title=Amd%2Fam186cx%2Fam186cc-50kc%5Cw&oldid=44748","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186cx/am186cc-50kc%5Cw"],"contentSha256":"20bde447f6c942b6c4df6062d4baa3a8023f97716c27ac10f56b647ebb311adc"},{"id":"chipswiki-8587-r26785","title":"N80L286-20 — ChipsWiki, revision 26785","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fn80l286-20&oldid=26785","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/n80l286-20"],"contentSha256":"790ad4edbd4b2ad77391cac9d7319c7025b46dea5aeba7cdd8b7c430e94d5854"},{"id":"chipswiki-8606-r26804","title":"C80286-10 — ChipsWiki, revision 26804","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2Fc80286-10&oldid=26804","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/c80286-10"],"contentSha256":"195e54c3b17a8bfc6f93219a97e8080a267edbe2d3a610739cc75ea0c50fbfa5"},{"id":"chipswiki-8613-r26811","title":"80286-8/BUC — ChipsWiki, revision 26811","url":"https://chipswiki.org/index.php?title=Amd%2Fam286%2F80286-8-buc&oldid=26811","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am286/80286-8-buc"],"contentSha256":"58d2a5ad5b5f0ea41104b0ce3c6fd2225c22e38f18b2102a8c8c501da58fb4a2"},{"id":"chipswiki-14618-r44679","title":"Am186ES–40VC\\W — ChipsWiki, revision 44679","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340vc%5Cw&oldid=44679","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186es%E2%80%9340vc%5Cw"],"contentSha256":"990e614fc75a3e65283a1fdc30fd6e7d51e138104311a4b1bbd77d48e3d5926b"},{"id":"chipswiki-14619-r44680","title":"Am186ES–40KC\\W — ChipsWiki, revision 44680","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9340kc%5Cw&oldid=44680","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186es%E2%80%9340kc%5Cw"],"contentSha256":"b768aa8605dc37619f4b752de4d192d9ad2a74af95e527cfc1c8e1ee202f9146"},{"id":"chipswiki-14622-r44683","title":"Am186ES–25VC\\W — ChipsWiki, revision 44683","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325vc%5Cw&oldid=44683","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186es%E2%80%9325vc%5Cw"],"contentSha256":"683c86759912dcb06924f2737663c1bf48b4dd8c2980c43050a83c2fe5c9ca03"},{"id":"chipswiki-14623-r44684","title":"Am186ES–25KI\\W — ChipsWiki, revision 44684","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9325ki%5Cw&oldid=44684","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186es%E2%80%9325ki%5Cw"],"contentSha256":"87041cea60d2a195d682600b32f0863386322859f38a94c015c77540770b3172"},{"id":"chipswiki-14627-r44688","title":"Am186ES–20KC\\W — ChipsWiki, revision 44688","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186es%E2%80%9320kc%5Cw&oldid=44688","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186es%E2%80%9320kc%5Cw"],"contentSha256":"68b58a11e0faeb538583470a698000223aa6f68e894c4b3f3cc4491021426eab"},{"id":"chipswiki-14628-r44689","title":"Am186ESLV–25VC\\W — ChipsWiki, revision 44689","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186eslv%E2%80%9325vc%5Cw&oldid=44689","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186eslv%E2%80%9325vc%5Cw"],"contentSha256":"bd7af1f2af5f517953011be3f35255eed7e3ef3b2d72600f36884a9a6c944d8e"},{"id":"chipswiki-14634-r44695","title":"Am186ER–50VC\\W — ChipsWiki, revision 44695","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350vc%5Cw&oldid=44695","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9350vc%5Cw"],"contentSha256":"0998d37215e389bc2c83405c4dcfac9c6d2d25dafa15ef4a8ee00e529f97a762"},{"id":"chipswiki-14636-r44697","title":"Am186ER–50KC\\W — ChipsWiki, revision 44697","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9350kc%5Cw&oldid=44697","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9350kc%5Cw"],"contentSha256":"226fd122baf0465971c6cd9ded90c977800a5a7f9fdc58b9a6ecc5488a77470f"},{"id":"chipswiki-14638-r44699","title":"Am186ER–40VC\\W — ChipsWiki, revision 44699","url":"https://chipswiki.org/index.php?title=Amd%2Fam186ex%2Fam186er%E2%80%9340vc%5Cw&oldid=44699","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am186ex/am186er%E2%80%9340vc%5Cw"],"contentSha256":"44e67dfaef9feb40f69588e23d21d990305867abc375eb48ba9518d6c3b10c8f"},{"id":"chipswiki-8543-r26739","title":"Am486DXL2-80 — ChipsWiki, revision 26739","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl2-80&oldid=26739","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dxl2-80"],"contentSha256":"41a4822c5e7bc0d310ff9d21962f77c40ef0af81209162dd06d3398e03836203"},{"id":"chipswiki-8545-r26741","title":"Am486DXL-40 — ChipsWiki, revision 26741","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dxl-40&oldid=26741","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dxl-40"],"contentSha256":"574d91e214752507e771339bf292ef70f9230b146abc96dca5b2e0d619dcb308"},{"id":"chipswiki-8553-r26749","title":"Am486DX4-120 — ChipsWiki, revision 26749","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-120&oldid=26749","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx4-120"],"contentSha256":"9aef3763deb0decd26e281968ffccb12fb16745e6e2b750ef856046b75941f2f"},{"id":"chipswiki-8554-r26750","title":"Am486DX4-100V8T — ChipsWiki, revision 26750","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v8t&oldid=26750","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx4-100v8t"],"contentSha256":"3f9041c1a574eccbbd17b4380faebd154442117e89d8dd2a90d37c95fb2c4255"},{"id":"chipswiki-8555-r26751","title":"Am486DX4-100V16B — ChipsWiki, revision 26751","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100v16b&oldid=26751","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx4-100v16b"],"contentSha256":"1b032c57f023aae053095c64100d38e959ac4eb1a286743d5f146f7140b84a1b"},{"id":"chipswiki-8556-r26752","title":"Am486DX4-100SV8B — ChipsWiki, revision 26752","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv8b&oldid=26752","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx4-100sv8b"],"contentSha256":"bb54fb33f97c0b84dc25cd0f570ec8486276975ae48c7b2666d6c7801aa94d61"},{"id":"chipswiki-8557-r26753","title":"Am486DX4-100SV16B — ChipsWiki, revision 26753","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100sv16b&oldid=26753","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx4-100sv16b"],"contentSha256":"b6d255926b7cb2e1a5283ee94c9611d39f4f00a6786b8b51883401c83c21c1f5"},{"id":"chipswiki-8558-r26754","title":"Am486DX4-100NV8T — ChipsWiki, revision 26754","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx4-100nv8t&oldid=26754","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx4-100nv8t"],"contentSha256":"68900098a91247e790e285656bd8478fdb87582702e7333e837426f7d24dfcdc"},{"id":"chipswiki-8563-r26760","title":"Am486DX2-66V8T — ChipsWiki, revision 26760","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66v8t&oldid=26760","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx2-66v8t"],"contentSha256":"04d0dc9ee0c11603d4b99e75dcfacb365082b0e9c5aa1037ea89275f87727254"},{"id":"chipswiki-8565-r26763","title":"Am486DX2-66SV8B — ChipsWiki, revision 26763","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66sv8b&oldid=26763","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx2-66sv8b"],"contentSha256":"91f501f3482582927c01f8609de5a528c387620e82d755c7df3223b11d4b5202"},{"id":"chipswiki-8567-r26765","title":"Am486DX2-66 — ChipsWiki, revision 26765","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-66&oldid=26765","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx2-66"],"contentSha256":"41fd14d7e19743ca4515d8c3e5f001f4480ef9ca21e1e276e6a936f9e52f1cf7"},{"id":"chipswiki-8572-r26770","title":"Am486DX2-100 — ChipsWiki, revision 26770","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx2-100&oldid=26770","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx2-100"],"contentSha256":"02dec20c2bd0fa47fc603dfb56927d1074cd4c72a5e0ed4d1e1f670527a0606e"},{"id":"chipswiki-8575-r26773","title":"Am486DX-25 — ChipsWiki, revision 26773","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486dx-25&oldid=26773","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486dx-25"],"contentSha256":"07b1f4f68ae848bcedd64b7a7f80d2f996197e057b7d1b9f587a809e1f9c3ade"},{"id":"chipswiki-8576-r26774","title":"Am486DE2-66 — ChipsWiki, revision 26774","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486de2-66v8t&oldid=26774","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486de2-66v8t"],"contentSha256":"c81ff267aa8d0a55313537a5a0144c21ea3ca4dc916335d2b0dcd9cc47c07c26"},{"id":"chipswiki-8497-r26690","title":"N8086-2 — ChipsWiki, revision 26690","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-2&oldid=26690","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/n8086-2"],"contentSha256":"b7cc7f0a2aea4f1e9bfb7c96ba6b07da40c45de02ca9101e3bbd122b616d96bb"},{"id":"chipswiki-8498-r26691","title":"N8086-1 — ChipsWiki, revision 26691","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fn8086-1&oldid=26691","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/n8086-1"],"contentSha256":"9f0b248bc03ca79e514d1ffc63f8da0babd6ec4f1c3fed33ef98f54c8d2aa2c1"},{"id":"chipswiki-8502-r26695","title":"MD8086 — ChipsWiki, revision 26695","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fmd8086&oldid=26695","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/md8086"],"contentSha256":"61411e5e59bb36af777a80ad82d9cc8934f54dc05ef232112751a69fd9972021"},{"id":"chipswiki-8505-r26698","title":"J8086-2 — ChipsWiki, revision 26698","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-2&oldid=26698","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/j8086-2"],"contentSha256":"02e6c98798d12e3d8e4fca8cfd34c733f5e7df70292bc49bc701481d72f0329f"},{"id":"chipswiki-8506-r26699","title":"J8086-1B — ChipsWiki, revision 26699","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1b&oldid=26699","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/j8086-1b"],"contentSha256":"fa8b8af43bb7def11f0fd013bb6320b6073661a6c94716fddcdf8bbf44b05404"},{"id":"chipswiki-8507-r26700","title":"J8086-1 — ChipsWiki, revision 26700","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fj8086-1&oldid=26700","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/j8086-1"],"contentSha256":"0b87658bf9a0fff2ff1bbe4a6d31bca28a50b9683e9262f91d0bb4fb1e3d2d56"},{"id":"chipswiki-8512-r26705","title":"ID8086 — ChipsWiki, revision 26705","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fid8086&oldid=26705","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/id8086"],"contentSha256":"c489adbc3c1c4181c5c4410fdfed55e5d0a14483b6c412c4f8d01a490954e446"},{"id":"chipswiki-8513-r26706","title":"D8086B — ChipsWiki, revision 26706","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086b&oldid=26706","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/d8086b"],"contentSha256":"12cd6df4c392f01cc2cd85e89c41c6892d467d5dbf3409ba1fb6aa8129209e34"},{"id":"chipswiki-8515-r26708","title":"D8086-2 — ChipsWiki, revision 26708","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-2&oldid=26708","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/d8086-2"],"contentSha256":"d99343eaf455bf6e0dcb8974fad00a676d917d86bba4b1b3c85bb8fc58e5972c"},{"id":"chipswiki-8517-r26710","title":"D8086-1 — ChipsWiki, revision 26710","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086-1&oldid=26710","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/d8086-1"],"contentSha256":"67ae071ce13a69f619b58c0d5da91501a6e839f8c6ab4f21355ebb666985652f"},{"id":"chipswiki-8518-r26711","title":"D8086 — ChipsWiki, revision 26711","url":"https://chipswiki.org/index.php?title=Amd%2Fam8086%2Fd8086&oldid=26711","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am8086/d8086"],"contentSha256":"14a564d840f560df44db4c8d5cf9a93c5615c96c753fca541f76bf86501d49b5"},{"id":"chipswiki-8524-r26719","title":"AMD-X5-133SFY — ChipsWiki, revision 26719","url":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sfy&oldid=26719","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am5x86/amd-x5-133sfy"],"contentSha256":"9c87864f5885c5f5f6b2876b5f2479723d1900c58098e8c29615e58fe9f313e9"},{"id":"chipswiki-8527-r26722","title":"AMD-X5-133SDY — ChipsWiki, revision 26722","url":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdy&oldid=26722","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am5x86/amd-x5-133sdy"],"contentSha256":"d52eb637bc02b281dc43388127592f8f5b6f182ccd3aef025b25cbd12412b23c"},{"id":"chipswiki-8528-r26723","title":"AMD-X5-133SDW — ChipsWiki, revision 26723","url":"https://chipswiki.org/index.php?title=Amd%2Fam5x86%2Famd-x5-133sdw&oldid=26723","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am5x86/amd-x5-133sdw"],"contentSha256":"af74c290a7650541387dd149a56e431d4cc4882a11417974acdcf1ad533ccff7"},{"id":"chipswiki-8536-r26732","title":"Am486SX2-66 — ChipsWiki, revision 26732","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx2-66&oldid=26732","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486sx2-66"],"contentSha256":"5aecacf5bb7c208fac89a122257f456a985a7225521574bd280946ebca2cc19a"},{"id":"chipswiki-8538-r26734","title":"Am486SX-40 — ChipsWiki, revision 26734","url":"https://chipswiki.org/index.php?title=Amd%2Fam486%2Fam486sx-40&oldid=26734","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am486/am486sx-40"],"contentSha256":"d657d7db9476cae5489908182d9626f06a832507194c874cea1d407aa09edfa6"},{"id":"chipswiki-187-r375","title":"Athlon 3000G — ChipsWiki, revision 375","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F3000g&oldid=375","publisher":"ChipsWiki / WikiChip contributors","published":"2022-09-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon/3000g"],"contentSha256":"e19828a6834fc7f86161924c684d08b2475615d18b8d380d096423d5b80d1bc1"},{"id":"chipswiki-549-r1136","title":"Athlon PRO 300GE — ChipsWiki, revision 1136","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2Fpro%20300ge&oldid=1136","publisher":"ChipsWiki / WikiChip contributors","published":"2022-01-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon/pro_300ge"],"contentSha256":"227ca2d06d3da7445720747155a0e27143b3fe3d6c40c1775adf8f8f49580ab2"},{"id":"chipswiki-31477-r92441","title":"Template:Packages/amd/socket am4 — revision 92441","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20am4&oldid=92441","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2Fsocket_am4"],"contentSha256":"bb3fd846c7d67fda0ede67b082fec9ef39213f59bdd43493b5cafad816366aa4"},{"id":"chipswiki-1102-r3264","title":"Athlon 300U — ChipsWiki, revision 3264","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F300u&oldid=3264","publisher":"ChipsWiki / WikiChip contributors","published":"2020-06-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon/300u"],"contentSha256":"147ad9ecb2b2fbdf3f13e47fc9623dc48c768b1e24220c135361516757e8ead8"},{"id":"chipswiki-1395-r4696","title":"Athlon Gold 3150U — ChipsWiki, revision 4696","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%20gold%2F3150u&oldid=4696","publisher":"ChipsWiki / WikiChip contributors","published":"2020-01-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon/pro_200ge"],"contentSha256":"1b680ec48ac531744f90f3f314d1cfd664bbe0b36caae71f2fe28fa856b61d78"},{"id":"chipswiki-2537-r8749","title":"Athlon 240GE — ChipsWiki, revision 8749","url":"https://chipswiki.org/index.php?title=Amd%2Fathlon%2F240ge&oldid=8749","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-12","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/athlon/240ge"],"contentSha256":"167869c627537ba16785c73e6ff1d12811fc102365b917a3f47da90d678d3873"},{"id":"chipswiki-8464-r26657","title":"AM9080APC — ChipsWiki, revision 26657","url":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080apc&oldid=26657","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am9080/am9080apc"],"contentSha256":"f122ba0d336cba1c55f9f5543e0d60044b38dab7ae6c8085087f4b71e31189f1"},{"id":"chipswiki-8465-r26658","title":"AM9080ADM — ChipsWiki, revision 26658","url":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adm&oldid=26658","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am9080/am9080adm"],"contentSha256":"3f5b83aae7b2d30536f966420b872ebe077a87e450f2b542b91f98618230d0f3"},{"id":"chipswiki-8466-r26659","title":"AM9080ADIB — ChipsWiki, revision 26659","url":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adib&oldid=26659","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am9080/am9080adib"],"contentSha256":"71154f6f8f1a4860f29e4e8befcbf6be280599f79f4850f260768141f133a390"},{"id":"chipswiki-8467-r26660","title":"AM9080ADI — ChipsWiki, revision 26660","url":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adi&oldid=26660","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am9080/am9080adi"],"contentSha256":"7fdef1c922900d9eb733069ac62d470aae8d75226ee8cc6c948ab93d7b82617a"},{"id":"chipswiki-8468-r26661","title":"AM9080ADCB — ChipsWiki, revision 26661","url":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080adcb&oldid=26661","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am9080/am9080adcb"],"contentSha256":"e98b2b0db2dec4a6d19cabc03deaa6d5e1d51a30f2157c9bfc158da54a950e4f"},{"id":"chipswiki-8470-r26663","title":"AM9080ACCB — ChipsWiki, revision 26663","url":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080accb&oldid=26663","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/am9080/am9080accb"],"contentSha256":"135aa04a4518071d5b35c19116088caffd5f0a517a6033f7f88dd7f96b230cec"},{"id":"chipswiki-8471-r26664","title":"AM9080ACC — ChipsWiki, revision 26664","url":"https://chipswiki.org/index.php?title=Amd%2Fam9080%2Fam9080acc&oldid=26664","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dm700avs1b"],"contentSha256":"f2bcc35f37a506690395ed44375bcacb410f5fbb5612bfc43626d6cd6fbc2b42"},{"id":"chipswiki-8406-r26114","title":"Mobile Duron 650 (Spitfire) — ChipsWiki, revision 26114","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm650avs1b&oldid=26114","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dm650avs1b"],"contentSha256":"d84aff9a9de343ac92286172488acb2bf5ad3c26f19e73c35d9007215a0d029c"},{"id":"chipswiki-8407-r26115","title":"Mobile Duron 600 (Spitfire) — ChipsWiki, revision 26115","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdm600avs1b&oldid=26115","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dm600avs1b"],"contentSha256":"efd0facddff54fe62ed51be9832e02e5b52e6c5e1f20b3ea32355e0e63d0b56f"},{"id":"chipswiki-8408-r26116","title":"Duron 1300 (Camaro) — ChipsWiki, revision 26116","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1300alq1b&oldid=26116","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhm1300alq1b"],"contentSha256":"131720bcfd0a715330d918930339bc39325a57aba6a6676a79f26946d820dea8"},{"id":"chipswiki-8409-r26117","title":"Duron 1200 (Camaro) — ChipsWiki, revision 26117","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1200aqq1b&oldid=26117","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhm1200aqq1b"],"contentSha256":"91e68caa536d5681b3ed7b682d2363b7ffc8852347a5cc100f59e485537b91de"},{"id":"chipswiki-8411-r26119","title":"Duron 1000 (Camaro) — ChipsWiki, revision 26119","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm1000avs1b&oldid=26119","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhm1000avs1b"],"contentSha256":"116d61d90d44be5cfeb1d990c6ce5a556da7a314bd5905ab4ae999b3ded4f0be"},{"id":"chipswiki-8412-r26120","title":"Duron 950 (Camaro) — ChipsWiki, revision 26120","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0950aqs1b&oldid=26120","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhm0950aqs1b"],"contentSha256":"de4518ae4ee1d934aabcfdeb7a63bdfa435f6250ef5e6ef4d890bb6e68fa6765"},{"id":"chipswiki-8413-r26121","title":"Duron 900 (Camaro) — ChipsWiki, revision 26121","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0900aqs1b&oldid=26121","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhm0900aqs1b"],"contentSha256":"23827918f0cc4258550143c48ed8566aead71db7a03a81c7715bc4369f9f5e21"},{"id":"chipswiki-8416-r26124","title":"Duron 850 (Camaro) — ChipsWiki, revision 26124","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0850als1b&oldid=26124","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhm0850als1b"],"contentSha256":"0e5bd6ea589b0b22defea689f96b5df0c3f49e016b9ddf9548082e48cbe5b968"},{"id":"chipswiki-8417-r26125","title":"Duron 800 (Camaro) — ChipsWiki, revision 26125","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800avs1bm&oldid=26125","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhm0800avs1bm"],"contentSha256":"61ab3051f63fd1a36ffbaf167f34c62b62db377d3cb843e6a28f1911987300e4"},{"id":"chipswiki-8418-r26126","title":"Duron 800 (Camaro) — ChipsWiki, revision 26126","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhm0800als1b&oldid=26126","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhm0800als1b"],"contentSha256":"3922538cb40a742f2ffe318dd46dca9c4fb3e8280d3cd0b855a6c4143be01fee"},{"id":"chipswiki-8420-r26128","title":"Duron 950 (Morgan) — ChipsWiki, revision 26128","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd950amt1b&oldid=26128","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhd950amt1b"],"contentSha256":"6f86c14a5cecc4fa06a43331049025efa9544c8317d6d89c207b34d291f24eb7"},{"id":"chipswiki-8423-r26131","title":"Duron 1600 (Applebred) — ChipsWiki, revision 26131","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1600dlv1c&oldid=26131","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhd1600dlv1c"],"contentSha256":"379db81ec2d08d917d28392df00e1002d07ca374b44ae269bd8ca5f5864ecc82"},{"id":"chipswiki-8426-r26134","title":"Duron 1200 (Morgan) — ChipsWiki, revision 26134","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1200amt1b&oldid=26134","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhd1200amt1b"],"contentSha256":"dcd42e260ef4d6f9973adf8e537356f4d69bf487c3ab16148790849d93460891"},{"id":"chipswiki-8427-r26135","title":"Duron 1100 (Morgan) — ChipsWiki, revision 26135","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fdhd1100amt1b&oldid=26135","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/dhd1100amt1b"],"contentSha256":"690ae3dcd937e0841dafcc0f687603b2a1c02fb45e893129e6342842dbeb9332"},{"id":"chipswiki-8432-r26140","title":"Duron 800 (Spitfire) — ChipsWiki, revision 26140","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800avs1b&oldid=26140","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d800avs1b"],"contentSha256":"ec5256e35fc294d11b5b42eac3a0e27abfbf18fe2fef6351d29e5019c04f8954"},{"id":"chipswiki-8433-r26141","title":"Duron 800 (Spitfire) — ChipsWiki, revision 26141","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd800aut1b&oldid=26141","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d800aut1b"],"contentSha256":"b4850711dd654101684425b5204a7ac5208b23c6eff2d740b9c4be08aa5e05c5"},{"id":"chipswiki-8434-r26142","title":"Duron 750 (Spitfire) — ChipsWiki, revision 26142","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd750aut1b&oldid=26142","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d750aut1b"],"contentSha256":"28118cc2809cc42c8b7fc1345dd310bfbae5324374651bfb182417052a693e74"},{"id":"chipswiki-8436-r26144","title":"Duron 700 (Spitfire) — ChipsWiki, revision 26144","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700avs1b&oldid=26144","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d700avs1b"],"contentSha256":"30a2d422fc1bd43a7c5af8a79161078cd4c8e4bbeaf684aca21f57c342088e4c"},{"id":"chipswiki-8437-r26145","title":"Duron 700 (Spitfire) — ChipsWiki, revision 26145","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd700aut1b&oldid=26145","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d700aut1b"],"contentSha256":"d5e95752addafa94bbdbb44a8111034382269996a54aff2c9c7e6faa99281ee0"},{"id":"chipswiki-8439-r26147","title":"Duron 650 (Spitfire) — ChipsWiki, revision 26147","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd650aut1b&oldid=26147","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d650aut1b"],"contentSha256":"ab5d6c86c9ef992504ec3e819a2ed41b48c3ea9d433b112beb174337012635da"},{"id":"chipswiki-8441-r26149","title":"Duron 600 (Spitfire) — ChipsWiki, revision 26149","url":"https://chipswiki.org/index.php?title=Amd%2Fduron%2Fd600aut1b&oldid=26149","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/duron/d600aut1b"],"contentSha256":"39f686fcf258a3245db7119061f36e340d63436db4f34188f5ce7acaaa6e128e"},{"id":"chipswiki-221-r452","title":"EPYC 7232P — ChipsWiki, revision 452","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7232p&oldid=452","publisher":"ChipsWiki / WikiChip contributors","published":"2022-08-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7232p"],"contentSha256":"ad9049a90d6dc8a4e4468fae77d8e9f7f8cd567222a6abe7f8943891cf5c0339"},{"id":"chipswiki-276-r560","title":"EPYC 7532 — ChipsWiki, revision 560","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7532&oldid=560","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7532"],"contentSha256":"9720b72636e5071faa648a288fdde3f578fa62196fc4f675477ce8d7e9ecad68"},{"id":"chipswiki-415-r887","title":"Embedded G-Series T56E — ChipsWiki, revision 887","url":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft56e&oldid=887","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/embedded/t56e"],"contentSha256":"e9e75f6232c84d642a78253bb234cc2f8449799b752019c5b99812eae85d13ac"},{"id":"chipswiki-416-r888","title":"Embedded G-Series T52R — ChipsWiki, revision 888","url":"https://chipswiki.org/index.php?title=Amd%2Fembedded%2Ft52r&oldid=888","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/embedded/t52r"],"contentSha256":"6a4a4ac7ef4f5d42ad67233a352ea43fa0ff856aa8f87b24cb7d47dc01daa7a0"},{"id":"chipswiki-31468-r92417","title":"Template:Packages/amd/socket sp3 — revision 92417","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fsocket%20sp3&oldid=92417","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-20","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2Fsocket_sp3"],"contentSha256":"aa7769590c72cab44b532bbe05da8b6123f5b0eebea5f7384076e7fe7d710e06"},{"id":"chipswiki-680-r1668","title":"EPYC 7452 — ChipsWiki, revision 1668","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7452&oldid=1668","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7452"],"contentSha256":"766d0716445be17032006bf78203bb7796c3d053c3b4c44e5e3c6f7e6fc4b1fb"},{"id":"chipswiki-729-r1750","title":"EPYC 7313 — ChipsWiki, revision 1750","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313&oldid=1750","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7313"],"contentSha256":"6decbfab172fc1b7c46bf1272fb0dafb0a876df8327cb17dba1e8a57d09bb846"},{"id":"chipswiki-735-r1756","title":"EPYC 7543 — ChipsWiki, revision 1756","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7543&oldid=1756","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7543"],"contentSha256":"0415ba5d2cf0ad430d4bc6b0762b29740a7132ce04593c4acf3d7e80dc85d04c"},{"id":"chipswiki-749-r1790","title":"EPYC 75F3 — ChipsWiki, revision 1790","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F75f3&oldid=1790","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/75f3"],"contentSha256":"7d2b5767c9c7e55a634807efda8b8be3c12849f31a1f625f250373a0db32103c"},{"id":"chipswiki-753-r1795","title":"EPYC 7313P — ChipsWiki, revision 1795","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7313p&oldid=1795","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7313p"],"contentSha256":"4e9d459a11d05171918d4d1d3cdd2e27f4bdb01d774f77923fe0f240c4ba3bf8"},{"id":"chipswiki-853-r2233","title":"EPYC 7252 — ChipsWiki, revision 2233","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7252&oldid=2233","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7252"],"contentSha256":"3b3af5fedf0876944523f0c48aefb4bfb12f29e3f57bcd126496f38cbb97251a"},{"id":"chipswiki-854-r2234","title":"EPYC 7262 — ChipsWiki, revision 2234","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7262&oldid=2234","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7302p"],"contentSha256":"7558fae3768cfecb3fb7197743706cf9578951630a65978396ae603cb5300999"},{"id":"chipswiki-865-r2249","title":"EPYC 7552 — ChipsWiki, revision 2249","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7552&oldid=2249","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7371"],"contentSha256":"5bd632c739fbf4c99eecf41d484c826c8dedf209dca6ca63d13fd0ce25bfa5c6"},{"id":"chipswiki-4355-r14056","title":"EPYC 7501 — ChipsWiki, revision 14056","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7501&oldid=14056","publisher":"ChipsWiki / WikiChip contributors","published":"2018-11-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7501"],"contentSha256":"0700626ae11d6c5ba252fee1885030c55cf4497c667089ad4c69918070a97efd"},{"id":"chipswiki-5071-r16543","title":"EPYC 7351 — ChipsWiki, revision 16543","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7351&oldid=16543","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7351"],"contentSha256":"e5172c03ba5338a647177e8bd298a4e9419aceeedb3a6ec47d40a680125c37b8"},{"id":"chipswiki-5075-r16548","title":"EPYC 7451 — ChipsWiki, revision 16548","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7451&oldid=16548","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7451"],"contentSha256":"2062cc333602c4cf2e5204b6667b60dcf5cb75e99e641988e6630560b82ae3ef"},{"id":"chipswiki-44-r96984","title":"EPYC 7763 — ChipsWiki, revision 96984","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7763&oldid=96984","publisher":"ChipsWiki / WikiChip contributors","published":"2022-10-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7763"],"contentSha256":"c093e11dcea4272875ec0d3ace82e3e6ccd5b01ad8852377661c056df2fccdea"},{"id":"chipswiki-31097-r91556","title":"Template:Packages/amd/package sp4 — revision 91556","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4&oldid=91556","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Famd%2Fpackage_sp4"],"contentSha256":"08de060f40ba925f1f768975406f2684ec6cb2cd6f7e56d153460f19791d76ef"},{"id":"chipswiki-404-r874","title":"EPYC Embedded 3401 — ChipsWiki, revision 874","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3401&oldid=874","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc_embedded/3401"],"contentSha256":"3cb929a22d965b1a912d804dfd8e46e31fe292dd3f30687cb694c73a35969183"},{"id":"chipswiki-405-r875","title":"EPYC Embedded 3351 — ChipsWiki, revision 875","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%20embedded%2F3351&oldid=875","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc_embedded/3255"],"contentSha256":"a4fa5c3a9399343d98fd2e95ade7e1689f8d9a0fb0d25c51475db0a0ff60cac2"},{"id":"chipswiki-31098-r91557","title":"Template:Packages/amd/package sp4r2 — revision 91557","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Famd%2Fpackage%20sp4r2&oldid=91557","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc_embedded/3201"],"contentSha256":"370a5baa82395b94fefdde772a6824866f85a7ad451d50767def447bf0d5ca74"},{"id":"chipswiki-555-r1152","title":"EPYC 7662 — ChipsWiki, revision 1152","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7662&oldid=1152","publisher":"ChipsWiki / WikiChip contributors","published":"2021-12-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/epyc/7662"],"contentSha256":"0978af9e40e1df7d108790f5f5a4c16cfe3a255a2d76032882ce664120f666ea"},{"id":"chipswiki-737-r1758","title":"EPYC 7663 — ChipsWiki, revision 1758","url":"https://chipswiki.org/index.php?title=Amd%2Fepyc%2F7663&oldid=1758","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2+/k6-2e+-400itz"],"contentSha256":"61996cfa18461803337c40b26313a0c7bc423acacbe2710433f31ac017ccb74f"},{"id":"chipswiki-1006-r2857","title":"K6-2E+/450APZ — ChipsWiki, revision 2857","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2B%2Fk6-2e%2B-450apz&oldid=2857","publisher":"ChipsWiki / WikiChip contributors","published":"2020-07-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2+/k6-2e+-450apz"],"contentSha256":"9e8e944e6632f3b3cc67d0751f9a37531bfb99676335ae3684e612c01425ddb3"},{"id":"chipswiki-4124-r13094","title":"K6-2/200AFR — ChipsWiki, revision 13094","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-200afr&oldid=13094","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-05","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/k6-2/k6-2-300afr"],"contentSha256":"a73af64d5b060b09efcca407e23ec6e23619fd6f9151ab55c3404f57fecfac83"},{"id":"chipswiki-8384-r26079","title":"AMD-K6-2/266ANZ — ChipsWiki, revision 26079","url":"https://chipswiki.org/index.php?title=Amd%2Fk6-2%2Fk6-2-266anz&oldid=26079","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/pro_2200ge"],"contentSha256":"8a0827eb9a01b11aab26f199c2617d87480d396cff9dfe35a05971cf0683a974"},{"id":"chipswiki-1245-r3997","title":"Ryzen 3 2200GE — ChipsWiki, revision 3997","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2200ge&oldid=3997","publisher":"ChipsWiki / WikiChip contributors","published":"2020-03-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/2200ge"],"contentSha256":"e0cb1b251a5c2435a5d580c9053a4f7643e84b2f16cd37d98a6a897e8d153ef6"},{"id":"chipswiki-1406-r4746","title":"Ryzen 3 3300U — ChipsWiki, revision 4746","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F3300u&oldid=4746","publisher":"ChipsWiki / WikiChip contributors","published":"2020-01-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/3300u"],"contentSha256":"1798194682655c7103953be2cf8f58b7c89aedff2c11f890b2bb68fa45b02066"},{"id":"chipswiki-4248-r13714","title":"Ryzen 3 2300X — ChipsWiki, revision 13714","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2F2300x&oldid=13714","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/2300x"],"contentSha256":"6f0ff01c67e700850b58a9de62498599308441bd6f1432aba402c1c4c9514ef1"},{"id":"chipswiki-6283-r19492","title":"Ryzen 3 PRO 2300U — ChipsWiki, revision 19492","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%203%2Fpro%202300u&oldid=19492","publisher":"ChipsWiki / WikiChip contributors","published":"2018-05-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_3/pro_2300u"],"contentSha256":"1e5b4b6519ca5cd52cf779cb89598eed32fd15d4929519f470d1fbe9d3c4f3b6"},{"id":"chipswiki-349-r737","title":"Ryzen 5 PRO 3400G — ChipsWiki, revision 737","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400g&oldid=737","publisher":"ChipsWiki / WikiChip contributors","published":"2022-05-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_3400g"],"contentSha256":"10ff2e7ca0fc3c1c031f6dde8f6a99687c7fc7c84e96635fb67ec87b06d4c20e"},{"id":"chipswiki-504-r1002","title":"Ryzen 5 3500X — ChipsWiki, revision 1002","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500x&oldid=1002","publisher":"ChipsWiki / WikiChip contributors","published":"2022-02-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/3500x"],"contentSha256":"cfcb1c0d00d6469a5416c41f66a388481173edb2ac88978effff5b476f512d07"},{"id":"chipswiki-542-r1114","title":"Ryzen 5 4500U — ChipsWiki, revision 1114","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4500u&oldid=1114","publisher":"ChipsWiki / WikiChip contributors","published":"2022-01-11","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/4500u"],"contentSha256":"3cec2a41bb143672b8fa4987908ea3bd0c74fd725adfdec7ee6c70e85766eaf2"},{"id":"chipswiki-595-r1390","title":"Ryzen 5 3500U — ChipsWiki, revision 1390","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3500u&oldid=1390","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/3500u"],"contentSha256":"267b033df20e6d4248152f7db84f82ada7ba8054fa90f4d40f5f9eceec76f33d"},{"id":"chipswiki-609-r1431","title":"Ryzen 5 PRO 5650GE — ChipsWiki, revision 1431","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650ge&oldid=1431","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_5650ge"],"contentSha256":"9f5a3fa5930619e4f4f0ad53df66c096d73b7e5f94500ec1a8a31eb0bdfa2a97"},{"id":"chipswiki-610-r1432","title":"Ryzen 5 PRO 5650G — ChipsWiki, revision 1432","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650g&oldid=1432","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_5650g"],"contentSha256":"e4112d9926ae9aed1e5ce01c1fcf8256655d0f623fa02b5ec1e4d2f5dd6c8db7"},{"id":"chipswiki-691-r1686","title":"Ryzen 5 4600U — ChipsWiki, revision 1686","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F4600u&oldid=1686","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/4600u"],"contentSha256":"357f931f66b9603fa90fdc046a316a5cdadcc5e7207cfc9a58d66f5668b87c59"},{"id":"chipswiki-714-r1721","title":"Ryzen 5 5600H — ChipsWiki, revision 1721","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F5600h&oldid=1721","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/5600h"],"contentSha256":"16c84c40349ba63de57126dee1c8070259c9917703fc18f4a8b99ead619ce783"},{"id":"chipswiki-717-r1724","title":"Ryzen 5 PRO 5650U — ChipsWiki, revision 1724","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%205650u&oldid=1724","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_5650u"],"contentSha256":"7c0bdd52d92088742cbcd6be4b8d45aeda00d70882a14445089d813ebf753aab"},{"id":"chipswiki-755-r1798","title":"Ryzen 5 3550H — ChipsWiki, revision 1798","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2F3550h&oldid=1798","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/3550h"],"contentSha256":"e03b865e4190716e565c7f152b0df46fc8e2c286966de523c30d68ac0f9466df"},{"id":"chipswiki-1547-r5052","title":"Ryzen 5 PRO 3600 — ChipsWiki, revision 5052","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203600&oldid=5052","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_3600"],"contentSha256":"64b341942e7756a6613c46c0f67b0b3d1fdec0ac948cc8e6e58c1e020d9221ee"},{"id":"chipswiki-1552-r5093","title":"Ryzen 5 PRO 3400GE — ChipsWiki, revision 5093","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%203400ge&oldid=5093","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_3400ge"],"contentSha256":"c14754b063ab6da5e87aade5c8dc3b715a70e3f2771afb8a64ca2884107ac524"},{"id":"chipswiki-1814-r6072","title":"Ryzen 5 PRO 2400GE — ChipsWiki, revision 6072","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202400ge&oldid=6072","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_2400ge"],"contentSha256":"a6560e5d2edf77c702a0baa3a01d2c6d5c524ede2de2a3b52a34dfc2f7d618f9"},{"id":"chipswiki-4912-r15849","title":"Ryzen 5 PRO 2600 — ChipsWiki, revision 15849","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202600&oldid=15849","publisher":"ChipsWiki / WikiChip contributors","published":"2018-09-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_2600"],"contentSha256":"e4f84854b0753d5d461ba1259ae6caec54daff804d5a1f13bb1834fc5155c0a0"},{"id":"chipswiki-6282-r19481","title":"Ryzen 5 PRO 2500U — ChipsWiki, revision 19481","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%202500u&oldid=19481","publisher":"ChipsWiki / WikiChip contributors","published":"2018-05-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_2500u"],"contentSha256":"32de99b7898d07dcfa8b3e37b048abf4ec47e86ac271afe435ec7e034413a07a"},{"id":"chipswiki-7353-r23748","title":"Ryzen 5 PRO 1600 — ChipsWiki, revision 23748","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%205%2Fpro%201600&oldid=23748","publisher":"ChipsWiki / WikiChip contributors","published":"2018-01-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_5/pro_1600"],"contentSha256":"8288248acd0480cf5687f98855bc4a8adf85bcbb10092af111f36e1a01f14d16"},{"id":"chipswiki-87-r97044","title":"Ryzen 7 5700U — ChipsWiki, revision 97044","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5700u&oldid=97044","publisher":"ChipsWiki / WikiChip contributors","published":"2022-10-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/5700u"],"contentSha256":"f115681f4e6c01f0bb67d71ee9600f0bf7633296d3e171137e36ee73c54b0c13"},{"id":"chipswiki-429-r906","title":"Ryzen 7 PRO 5850U — ChipsWiki, revision 906","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205850u&oldid=906","publisher":"ChipsWiki / WikiChip contributors","published":"2022-03-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/pro_5850u"],"contentSha256":"6c4f7dffa3c2ff174f312fc91e414633a736d09295b1d586186232e258d92da2"},{"id":"chipswiki-607-r1429","title":"Ryzen 7 PRO 5750GE — ChipsWiki, revision 1429","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750ge&oldid=1429","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/pro_5750ge"],"contentSha256":"ab1d5d72943003115a8db72467db9b36486d54fac3ac74863c6232f1328f7604"},{"id":"chipswiki-608-r1430","title":"Ryzen 7 PRO 5750G — ChipsWiki, revision 1430","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%205750g&oldid=1430","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/pro_5750g"],"contentSha256":"dfc8a6a6ea7647feabb0ad90425931d9ce78abb46ee2be1265eef33f2b4d2f10"},{"id":"chipswiki-687-r1681","title":"Ryzen 9 4900H — ChipsWiki, revision 1681","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900h&oldid=1681","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_9/4900h"],"contentSha256":"d9e134e04d09fc4d98ee8a0f545af41d3eb31807167682bd9bcc0d0c8f122678"},{"id":"chipswiki-688-r1682","title":"Ryzen 9 4900HS — ChipsWiki, revision 1682","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F4900hs&oldid=1682","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_9/4900hs"],"contentSha256":"a0a1fa0e184a9084ab3ead0d3df936fdbd86e0bc8ed22270a2ff523fbf71a2ff"},{"id":"chipswiki-701-r1701","title":"Ryzen 7 4700G — ChipsWiki, revision 1701","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700g&oldid=1701","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/4700g"],"contentSha256":"02df491431683a2ef0adb1044256131e869317c102b2c73d53a1f5ae209c07e6"},{"id":"chipswiki-702-r1702","title":"Ryzen 7 4700GE — ChipsWiki, revision 1702","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F4700ge&oldid=1702","publisher":"ChipsWiki / WikiChip contributors","published":"2021-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/4700ge"],"contentSha256":"fb4c5d426186f65c76dc46bb373e51b3e817c835b9c84aa6389f2a834fd99bff"},{"id":"chipswiki-720-r1730","title":"Ryzen 7 5800U — ChipsWiki, revision 1730","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F5800u&oldid=1730","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/5800u"],"contentSha256":"fdaac086bfe854d291b68e4576f83bc3cd03db1ab3d383789828ea68379d8faf"},{"id":"chipswiki-728-r1749","title":"Ryzen 7 PRO 4750U — ChipsWiki, revision 1749","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%204750u&oldid=1749","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/3750h"],"contentSha256":"5f74451d2d7302ffbc2cef5f7202ff6fac2c3164c75952ef29af921293f268cc"},{"id":"chipswiki-921-r2545","title":"Ryzen 7 3780U — ChipsWiki, revision 2545","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2F3780u&oldid=2545","publisher":"ChipsWiki / WikiChip contributors","published":"2020-10-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/3780u"],"contentSha256":"844cdc6567c97eebe5b72fb04f83ece4f56a1c18b8466c52be73091008a63490"},{"id":"chipswiki-1210-r3780","title":"Ryzen 7 PRO 1700X — ChipsWiki, revision 3780","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%201700x&oldid=3780","publisher":"ChipsWiki / WikiChip contributors","published":"2020-04-12","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/pro_1700x"],"contentSha256":"0b9e6078cfbf1142072ddf91f5668c422802ec00d390bb8c4dcb159c1339e035"},{"id":"chipswiki-1550-r5057","title":"Ryzen 9 3900 — ChipsWiki, revision 5057","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F3900&oldid=5057","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_9/3900"],"contentSha256":"ad35ef03d084ae17ad6adafa62b05d085a19930828bf010e3a25932762210377"},{"id":"chipswiki-4914-r15851","title":"Ryzen 7 PRO 2700 — ChipsWiki, revision 15851","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700&oldid=15851","publisher":"ChipsWiki / WikiChip contributors","published":"2018-09-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_7/pro_2700"],"contentSha256":"84e141c556becf0c6cafbd237e75aa94ef02860d86e3ac07ef344089b00b0712"},{"id":"chipswiki-5234-r17148","title":"Ryzen 7 PRO 2700U — ChipsWiki, revision 17148","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%207%2Fpro%202700u&oldid=17148","publisher":"ChipsWiki / WikiChip contributors","published":"2018-07-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_threadripper/pro_3955wx"],"contentSha256":"dbcae3f75faacc9b34ef640950dfff2e0a2ad446835a5844eb63f4a99c447724"},{"id":"chipswiki-391-r837","title":"Ryzen Threadripper PRO 5995WX — ChipsWiki, revision 837","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205995wx&oldid=837","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_threadripper/pro_5995wx"],"contentSha256":"12475f639646203ced78f337bbfbd3fad287630032aad48a5fbcb4768e1575f4"},{"id":"chipswiki-392-r838","title":"Ryzen Threadripper PRO 5975WX — ChipsWiki, revision 838","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20threadripper%2Fpro%205975wx&oldid=838","publisher":"ChipsWiki / WikiChip contributors","published":"2022-04-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_threadripper/pro_5975wx"],"contentSha256":"4eb82651c4d5c55f5cfa4dbdbc21e6361b4efc74160d7c17da53d1d0fe61ab13"},{"id":"chipswiki-723-r1733","title":"Ryzen 9 5980HS — ChipsWiki, revision 1733","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5980hs&oldid=1733","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_9/5980hs"],"contentSha256":"fd0a8ef304a49bea6df5e16f6cad320bc9c6f3e29b38f46301422ba93cb0aeb8"},{"id":"chipswiki-724-r1738","title":"Ryzen 9 5900 — ChipsWiki, revision 1738","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%209%2F5900&oldid=1738","publisher":"ChipsWiki / WikiChip contributors","published":"2021-05-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_9/5900"],"contentSha256":"1327575e9d876711a2880852a078a232310f5a466d3b19fcba9dcff1fe94d8f1"},{"id":"chipswiki-879-r2290","title":"Ryzen Embedded V2748 — ChipsWiki, revision 2290","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2748&oldid=2290","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_embedded/v2748"],"contentSha256":"0b93200176fa8a3430c3bb11fd4342a29004387ba40ccd77beef1859e4f5d2cd"},{"id":"chipswiki-880-r2291","title":"Ryzen Embedded V2718 — ChipsWiki, revision 2291","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv2718&oldid=2291","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_embedded/v2718"],"contentSha256":"95420dbe1bc1480af9e5e0d614ab35113138e55e5cb21f87dd11b30f9220500d"},{"id":"chipswiki-923-r2547","title":"Ryzen Embedded R1606G — ChipsWiki, revision 2547","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1606g&oldid=2547","publisher":"ChipsWiki / WikiChip contributors","published":"2020-10-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_embedded/r1606g"],"contentSha256":"4e71adc7a4149835fd5419904a2c831126ba59aed6b6fb0125b6374cbc44b1f0"},{"id":"chipswiki-924-r2548","title":"Ryzen Embedded R1505G — ChipsWiki, revision 2548","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fr1505g&oldid=2548","publisher":"ChipsWiki / WikiChip contributors","published":"2020-10-18","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Amd/ryzen_embedded/r1102g"],"contentSha256":"33f089c2d082b452b88cf0f10912020370b2563069141db726ac7862fcaf9604"},{"id":"chipswiki-927-r2551","title":"Ryzen Embedded V1202B — ChipsWiki, revision 2551","url":"https://chipswiki.org/index.php?title=Amd%2Fryzen%20embedded%2Fv1202b&oldid=2551","publisher":"ChipsWiki / WikiChip contributors","published":"2020-10-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Annapurna_labs/alpine/alc12b00"],"contentSha256":"6e65557bbed259628dc34afbe793326ebefb36e2c5889db4f3ea112b634b9ed9"},{"id":"chipswiki-873-r2281","title":"A11 Bionic — ChipsWiki, revision 2281","url":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa11&oldid=2281","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apple/ax/a11"],"contentSha256":"ad3939cbc9c19298b206912884fa0cf7045824d393c63db0552ca163ae15d69b"},{"id":"chipswiki-888-r2320","title":"A12Z Bionic — ChipsWiki, revision 2320","url":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa12z&oldid=2320","publisher":"ChipsWiki / WikiChip contributors","published":"2020-12-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apple/ax/a12z"],"contentSha256":"0378c63a1d2223ee5da82f2ecc16b82c11c1917466ffe2b4dcc517d863e16901"},{"id":"chipswiki-889-r2326","title":"A10X Fusion — ChipsWiki, revision 2326","url":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10x&oldid=2326","publisher":"ChipsWiki / WikiChip contributors","published":"2020-12-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apple/ax/a10x"],"contentSha256":"549c451887305637d8f409031bc2c21a12427c6941a1d6c84447fdfdace5b547"},{"id":"chipswiki-896-r2352","title":"A10 Fusion — ChipsWiki, revision 2352","url":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa10&oldid=2352","publisher":"ChipsWiki / WikiChip contributors","published":"2020-12-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Apple/ax/a10"],"contentSha256":"99ae9f8ec38739792a388327955e58389c5a8da5e4ef07da1df9076db356fa0a"},{"id":"chipswiki-897-r2364","title":"A9 — ChipsWiki, revision 2364","url":"https://chipswiki.org/index.php?title=Apple%2Fax%2Fa9&oldid=2364","publisher":"ChipsWiki / WikiChip contributors","published":"2020-12-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/cortex-a5"],"contentSha256":"4e43ba2898945508cf1cba669874285e539b7e4ecd068fb7c45e84e683972fb4"},{"id":"chipswiki-4152-r13229","title":"ARM11 — ChipsWiki, revision 13229","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm11&oldid=13229","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-31","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/arm11"],"contentSha256":"cc337580c7e2a88195ca232d949d1aef65f7a8efc2c477e43c7379c2a69ef166"},{"id":"chipswiki-13387-r40185","title":"ARM250 — ChipsWiki, revision 40185","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Farm250&oldid=40185","publisher":"ChipsWiki / WikiChip contributors","published":"2017-07-10","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/hunter-elp"],"contentSha256":"301c8bb72fcb630924027dbbd4af2ad1b3c4ebceb7ed2f73c4ce3a2697ce27d6"},{"id":"chipswiki-301-r614","title":"Cortex-X3 — ChipsWiki, revision 614","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-x3&oldid=614","publisher":"ChipsWiki / WikiChip contributors","published":"2022-07-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Arm_holdings/microarchitectures/hayes"],"contentSha256":"0de8a5a414fc1f981f7c1c15b86c5b6f332e885332b988a8a85bb6e6f4ac26c4"},{"id":"chipswiki-850-r2224","title":"Cortex-M55 — ChipsWiki, revision 2224","url":"https://chipswiki.org/index.php?title=Arm%20holdings%2Fmicroarchitectures%2Fcortex-m55&oldid=2224","publisher":"ChipsWiki / WikiChip contributors","published":"2021-01-12","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3120-550bg868-scp"],"contentSha256":"2e0dad00ac62642be2357957c22d078b73dfd64c36a232868ab2c2a426eb3236"},{"id":"chipswiki-31466-r92414","title":"Template:Packages/cavium/fcbga-1521 — revision 92414","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fcavium%2Ffcbga-1521&oldid=92414","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3850-400bg1521-nsp"],"contentSha256":"f96d0fe05472a5f566f5f285e1f1b8f9d681b7ca62b7b247b72130464742703a"},{"id":"chipswiki-8212-r25871","title":"CN3840-600 SCP — ChipsWiki, revision 25871","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-scp&oldid=25871","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3840-600bg1521-scp"],"contentSha256":"7b3debdeb19e687e667b873bf10e41517927980bb858c99c0c6febce70348f41"},{"id":"chipswiki-8213-r25872","title":"CN3840-600 NSP — ChipsWiki, revision 25872","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3840-600bg1521-nsp&oldid=25872","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5745-800bg1217-sp"],"contentSha256":"f2adb2904a6013ba16362ba1c2270c2830fbae2cc4365424ac1df509890d7b49"},{"id":"chipswiki-8176-r25835","title":"CN5745-1000 SSP — ChipsWiki, revision 25835","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5745-1000bg1217-ssp&oldid=25835","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5745-1000bg1217-sp"],"contentSha256":"aa8a4a9d050a7e406b389c53408a6e8c17994f03a4ad3a135c17f7e0e411fe5f"},{"id":"chipswiki-8180-r25839","title":"CN5740-800 SSP — ChipsWiki, revision 25839","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5740-800bg1217-ssp&oldid=25839","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5740-800bg1217-ssp"],"contentSha256":"e00a8c0555cc5952b565939fa1a869f7b7a41b59bb71aa17ba166cbd15a38c09"},{"id":"chipswiki-8186-r25845","title":"CN5734-900 SSP — ChipsWiki, revision 25845","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-900bg1217-ssp&oldid=25845","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5734-800bg1217-ssp"],"contentSha256":"4147123c344f06a928364236ab0c33facd21917a097a968f6dfb1a6dc5a4975e"},{"id":"chipswiki-8190-r25849","title":"CN5734-600 SSP — ChipsWiki, revision 25849","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-600bg1217-ssp&oldid=25849","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5734-600bg1217-ssp"],"contentSha256":"98d0e504f6c127fcd65853988f0e7cce540bf9f11f5ceb12892e20ec293412e1"},{"id":"chipswiki-8192-r25851","title":"CN5734-1000 SSP — ChipsWiki, revision 25851","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-ssp&oldid=25851","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5734-1000bg1217-ssp"],"contentSha256":"a6a7fbf6c4d93b8f78bc4949be1981477fddb8abf02f6fb1438fb10a81a1376f"},{"id":"chipswiki-8193-r25852","title":"CN5734-1000 SP — ChipsWiki, revision 25852","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5734-1000bg1217-sp&oldid=25852","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon_plus/cn5734-1000bg1217-sp"],"contentSha256":"112fc0c58b307553ce846324367102284efc36bb9c7d09c77865248352bcfd5d"},{"id":"chipswiki-8194-r25853","title":"CN3860-600 SCP — ChipsWiki, revision 25853","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%2Fcn3860-600bg1521-scp&oldid=25853","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Cavium/octeon/cn3850-500bg1521-scp"],"contentSha256":"eb46d01dd1c117635c231476470600f61823accea854dbdf6be636efea53f011"},{"id":"chipswiki-8116-r25775","title":"CN5860-900 EXP — ChipsWiki, revision 25775","url":"https://chipswiki.org/index.php?title=Cavium%2Focteon%20plus%2Fcn5860-900bg1521-exp&oldid=25775","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fhisilicon%2Ftfbga-460"],"contentSha256":"1d7c5b4a125e250a3ffe4f726f8cc08820ddba0838c474c4c42b99e4498eb0c3"},{"id":"chipswiki-1124-r3339","title":"POWER9 — ChipsWiki, revision 3339","url":"https://chipswiki.org/index.php?title=Ibm%2Fmicroarchitectures%2Fpower9&oldid=3339","publisher":"ChipsWiki / WikiChip contributors","published":"2020-05-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/c3758"],"contentSha256":"aabaff2bb42460251b8425934018122a99c7f9fc2a57422e2a60915e76c6995a"},{"id":"chipswiki-1075-r3109","title":"Atom C3538 — ChipsWiki, revision 3109","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3538&oldid=3109","publisher":"ChipsWiki / WikiChip contributors","published":"2020-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/c3538"],"contentSha256":"3582d0a8983cbc3c5f16b976a7e5ee4185e85ede341dd885606a6519a166db5e"},{"id":"chipswiki-1653-r5735","title":"Atom x5-E3930 — ChipsWiki, revision 5735","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3930&oldid=5735","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom_x5/x5-e3930"],"contentSha256":"3817d34bf5abed22de132b0a39608995d700e4e2229b45091cf56ad26ca0a9ce"},{"id":"chipswiki-1862-r6398","title":"Atom C3858 — ChipsWiki, revision 6398","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3858&oldid=6398","publisher":"ChipsWiki / WikiChip contributors","published":"2019-08-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/c3858"],"contentSha256":"7821e6a49295f836b34c14f1e8f08ab6ab3664e35dea039a66fb7ba413cdd542"},{"id":"chipswiki-1867-r6403","title":"Atom C3808 — ChipsWiki, revision 6403","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3808&oldid=6403","publisher":"ChipsWiki / WikiChip contributors","published":"2019-08-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/c3808"],"contentSha256":"7e9174eeeec2d3423da5719a8b43a60e41f03c3a2e32e1f2771f6c0de704fb3d"},{"id":"chipswiki-1869-r6405","title":"Atom C3955 — ChipsWiki, revision 6405","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fc3955&oldid=6405","publisher":"ChipsWiki / WikiChip contributors","published":"2019-08-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/c3850"],"contentSha256":"be9e9346b7f750604e1e26b4af2e2b9c925dfce42f1ec3cf79cc245daffaae91"},{"id":"chipswiki-3976-r12682","title":"Atom x5-Z8300 — ChipsWiki, revision 12682","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-z8300&oldid=12682","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom_x5/x5-z8300"],"contentSha256":"f48fb18ae30523717b15437d1c2e961c31d04eb476d058007fad9d73181e3e0a"},{"id":"chipswiki-6858-r21411","title":"Atom x5-E8000 — ChipsWiki, revision 21411","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e8000&oldid=21411","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom_x5/x5-e8000"],"contentSha256":"c65b12ffb9a3360c4a3fa321245bb0649ccfce7621d7688e1d9bb4c22f6b6c49"},{"id":"chipswiki-8045-r25680","title":"Atom x5-E3940 — ChipsWiki, revision 25680","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x5%2Fx5-e3940&oldid=25680","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom_x5/x5-e3940"],"contentSha256":"846dde6bc79af924af2ee468af582b36868f9c79e2f86cb7c821bc04cf9d1f29"},{"id":"chipswiki-31501-r92563","title":"Template:Packages/intel/fcbga-518 — revision 92563","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-518&oldid=92563","publisher":"ChipsWiki / WikiChip contributors","published":"2017-04-22","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-518"],"contentSha256":"f1ffbfd4b58b072ffd1c36ac32c15aaab5237364790346fdab8c36464d181f76"},{"id":"chipswiki-8056-r25692","title":"Atom Z612 — ChipsWiki, revision 25692","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz612&oldid=25692","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z612"],"contentSha256":"908334d4df08947ed7557f63186a5b38c1dfceb0e264ec7c646489f1577b916b"},{"id":"chipswiki-8058-r25694","title":"Atom Z605 — ChipsWiki, revision 25694","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz605&oldid=25694","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z605"],"contentSha256":"e850f37e9313bb35219b720735eed6569c620bd6e6ee5cb5c4f6b28c7167a86c"},{"id":"chipswiki-8060-r25696","title":"Atom Z560 — ChipsWiki, revision 25696","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz560&oldid=25696","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z560"],"contentSha256":"d3fd746c4bbe9bac28339864059af0a7f09f621984c8aaccf7b11d7d0b937da4"},{"id":"chipswiki-31513-r92656","title":"Template:Packages/intel/fcbga-441 — revision 92656","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-441&oldid=92656","publisher":"ChipsWiki / WikiChip contributors","published":"2017-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-441"],"contentSha256":"d9e160971d00f77069a736b38bb5059ddcefe49a63421da8fd9fbbfec01cbf3b"},{"id":"chipswiki-8061-r25697","title":"Atom Z550 — ChipsWiki, revision 25697","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz550&oldid=25697","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z550"],"contentSha256":"f82e397485c46f59edb5d27761a10b6d6c3bc19782017de639fb089af368b56c"},{"id":"chipswiki-8062-r25698","title":"Atom Z540 — ChipsWiki, revision 25698","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz540&oldid=25698","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z540"],"contentSha256":"9bae7797112c60ac78014ea361a11b28fa5474603d692cf09abf617a59a25869"},{"id":"chipswiki-8063-r25699","title":"Atom Z530P — ChipsWiki, revision 25699","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz530p&oldid=25699","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z530"],"contentSha256":"033db0f152e9d40193b1c8aff662d497916ff7336de2f05b0ede7f674d121039"},{"id":"chipswiki-8065-r25701","title":"Atom Z520PT — ChipsWiki, revision 25701","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520pt&oldid=25701","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/atom/z520pt"],"contentSha256":"2cf55f262a4919239c497e14f206672ff04490058006fab959669da3e0805423"},{"id":"chipswiki-8066-r25702","title":"Atom Z520 — ChipsWiki, revision 25702","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%2Fz520&oldid=25702","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/4305u"],"contentSha256":"be760b1e3fcf324817c75d45d0693bb406ca74cf37e67b6d750e8b2e73231429"},{"id":"chipswiki-3013-r10021","title":"Celeron 4205U — ChipsWiki, revision 10021","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F4205u&oldid=10021","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/4205u"],"contentSha256":"d03f3c0e42a9d299b1fd9c81ffc5c38eec78ef6b32fe0e7192f9aa36a9eabb0e"},{"id":"chipswiki-3805-r11882","title":"Celeron 1007U — ChipsWiki, revision 11882","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F1007u&oldid=11882","publisher":"ChipsWiki / WikiChip contributors","published":"2019-03-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-1356"],"contentSha256":"4cfd19a6e261e29b5adadd25f38364e531ab3773b9ed9a5ce082f4a306734da6"},{"id":"chipswiki-6434-r20119","title":"Celeron G3930 — ChipsWiki, revision 20119","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3930&oldid=20119","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/g3930"],"contentSha256":"4054586cdacd8857d34adf8702199f659bb1ee51c6d83b3c0d04767e948b1ea7"},{"id":"chipswiki-6923-r21609","title":"Celeron B860E — ChipsWiki, revision 21609","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb860e&oldid=21609","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/b860e"],"contentSha256":"0071c127fb510af73f9a1844dc5c2d042db13c44b7a32f39daeb7583dfdd391e"},{"id":"chipswiki-6926-r21612","title":"Celeron B820 — ChipsWiki, revision 21612","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb820&oldid=21612","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/b820"],"contentSha256":"9328da949c6bb0f3528f7b0cade2a6eff2b5fb0c70ce155bfaaac74cb6d69706"},{"id":"chipswiki-6927-r21613","title":"Celeron B810E — ChipsWiki, revision 21613","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb810e&oldid=21613","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/b810e"],"contentSha256":"8198914ad8308310607cb78c5ab80306ff950c9f0d0a53173209fced57fcb0ef"},{"id":"chipswiki-6929-r21615","title":"Celeron B800 — ChipsWiki, revision 21615","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb800&oldid=21615","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/b800"],"contentSha256":"cd84d99891ce06bc1111e5ea27990414946d0b7b672291f983513dfaff1ea98c"},{"id":"chipswiki-6930-r21617","title":"Celeron B720 — ChipsWiki, revision 21617","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb720&oldid=21617","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/b720"],"contentSha256":"377f52cfd9cb55b1e046e4c3642195d91339c4f3a9a0a4ca08a320aa45327215"},{"id":"chipswiki-6937-r21624","title":"Celeron 857 — ChipsWiki, revision 21624","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F857&oldid=21624","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/857"],"contentSha256":"8520fe15e99a3aaaedb936ee29dfb1d6a5c91c84445aebcf2aa0c0f186de7835"},{"id":"chipswiki-6939-r21626","title":"Celeron 847 — ChipsWiki, revision 21626","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F847&oldid=21626","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/847"],"contentSha256":"5ed0bc82689e82f6e2c6bd4df056e820ab3e723a71d44e60b802bf223589d1af"},{"id":"chipswiki-6940-r21627","title":"Celeron 837 — ChipsWiki, revision 21627","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F837&oldid=21627","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/837"],"contentSha256":"b876183d61f5a049facc55d67652403d3fb49fe89b3cd48f0d8b54a8ffd4a728"},{"id":"chipswiki-6942-r21629","title":"Celeron 827 — ChipsWiki, revision 21629","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F827&oldid=21629","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/827"],"contentSha256":"52166b97e72d718264389ab17e4c476f994a9d5de1a92cd1e7516e749116930f"},{"id":"chipswiki-6943-r21630","title":"Celeron 817 — ChipsWiki, revision 21630","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F817&oldid=21630","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/817"],"contentSha256":"7b1e8b98fbe0ab6bded1bec122dd68454289efc13324ca996ed3496015e766ed"},{"id":"chipswiki-6945-r21632","title":"Celeron 807 — ChipsWiki, revision 21632","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F807&oldid=21632","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/807"],"contentSha256":"23d1b97c10adbfcbf397b66289061419b2724963a41acab37205bf67cbde9330"},{"id":"chipswiki-6948-r21635","title":"Celeron B815 — ChipsWiki, revision 21635","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fb815&oldid=21635","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/b815"],"contentSha256":"509c849b1715ab321a948e831fcd84165c2de5ad79b17522c5a9ce5991c1b764"},{"id":"chipswiki-8028-r25632","title":"Celeron G3920 — ChipsWiki, revision 25632","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3920&oldid=25632","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/g3920"],"contentSha256":"6bc2169e538f6c4de9432b295e7b2e498fdaaf439b180831972f81ae9e2225c6"},{"id":"chipswiki-31379-r92181","title":"Template:Packages/intel/fclga-1151 — revision 92181","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffclga-1151&oldid=92181","publisher":"ChipsWiki / WikiChip contributors","published":"2017-10-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffclga-1151"],"contentSha256":"bb53e1fc289da3604b34d0cb074c908d9e9772f2d2ee1db38c7e68ea495e7642"},{"id":"chipswiki-31464-r92410","title":"Template:Packages/intel/fcbga-1440 — revision 92410","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-1440&oldid=92410","publisher":"ChipsWiki / WikiChip contributors","published":"2017-06-23","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-1440"],"contentSha256":"bc5146b75dca42ead40430b36ba257a6a251a1882c3639a875df189e6255f98d"},{"id":"chipswiki-8030-r25634","title":"Celeron G3900TE — ChipsWiki, revision 25634","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900te&oldid=25634","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/g3900te"],"contentSha256":"865a74f1aaa0f9261e0bd5e693ea072f528c8cba54cdf2f312090008435b2499"},{"id":"chipswiki-8032-r25636","title":"Celeron G3900E — ChipsWiki, revision 25636","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900e&oldid=25636","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/g3900e"],"contentSha256":"e151b63558dd2a2c2266654e82cc88b9212ac32a247431f73ae6ee4e4fa29326"},{"id":"chipswiki-8033-r25637","title":"Celeron G3900 — ChipsWiki, revision 25637","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3900&oldid=25637","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/g3900"],"contentSha256":"42828239dba491cc250851990f73a571e2a2273ad6048f3008265870218bd27c"},{"id":"chipswiki-8034-r25665","title":"Celeron 3965Y — ChipsWiki, revision 25665","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3965y&oldid=25665","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/3965y"],"contentSha256":"5b95bda9220098dd91e889659976c9af6f9d7aa219a5dd5055b81db551b0ef61"},{"id":"chipswiki-8038-r25670","title":"Celeron 3755U — ChipsWiki, revision 25670","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2F3755u&oldid=25670","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/3755u"],"contentSha256":"6ccd7f99befdea3de7e53750228e908c7ca979add19c37feded46ae1e5bb5b6d"},{"id":"chipswiki-8041-r25673","title":"Atom x7-E3950 — ChipsWiki, revision 25673","url":"https://chipswiki.org/index.php?title=Intel%2Fatom%20x7%2Fx7-e3950&oldid=25673","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/j3455"],"contentSha256":"a96d72a7c519ed17e1986e9691f50dc03470ce09f9212ccdcc14f0fc3175a375"},{"id":"chipswiki-4336-r13971","title":"Celeron N3150 — ChipsWiki, revision 13971","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3150&oldid=13971","publisher":"ChipsWiki / WikiChip contributors","published":"2018-12-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/n3060"],"contentSha256":"c8c437560568301528cc0a700ec71c8172f01bff2cff66177bbfcc157260e2bb"},{"id":"chipswiki-6285-r19523","title":"Celeron J3355 — ChipsWiki, revision 19523","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fj3355&oldid=19523","publisher":"ChipsWiki / WikiChip contributors","published":"2018-05-09","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/j3355"],"contentSha256":"a6d7309804b034186f48e03e604f0d03fd6123f360a2c2cfbc4f0678e8628b60"},{"id":"chipswiki-6432-r20114","title":"Celeron G3950 — ChipsWiki, revision 20114","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fg3950&oldid=20114","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/g3950"],"contentSha256":"120eccd218c55a8dd44831a310ff05642b0c00fd6acd327043c0eb1945f5caf0"},{"id":"chipswiki-7505-r24401","title":"Celeron N4100 — ChipsWiki, revision 24401","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn4100&oldid=24401","publisher":"ChipsWiki / WikiChip contributors","published":"2018-01-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/n4100"],"contentSha256":"e3f12e3b4640e95a877efc5a27640da8d796f4980e94267ccb69ad367f419d59"},{"id":"chipswiki-8014-r25595","title":"Core i3-2330E — ChipsWiki, revision 25595","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-2330e&oldid=25595","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-2330e"],"contentSha256":"e1647f45d9e8898a9439612da004d41f62585480edf7edee0c499a2a4e56ed8c"},{"id":"chipswiki-31577-r92963","title":"Template:Packages/intel/bga-1288 — revision 92963","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Fbga-1288&oldid=92963","publisher":"ChipsWiki / WikiChip contributors","published":"2016-12-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Fbga-1288"],"contentSha256":"d172922a320e4c7c5506e11a270eb7b27f7c2f363aa9a4286672a9e5521fab38"},{"id":"chipswiki-8022-r25604","title":"Celeron U3405 — ChipsWiki, revision 25604","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3405&oldid=25604","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/u3405"],"contentSha256":"d14122a15ad011e9e123b82001b566d430247284e3ff4f0618470b78329c9114"},{"id":"chipswiki-8023-r25605","title":"Celeron U3400 — ChipsWiki, revision 25605","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fu3400&oldid=25605","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/u3400"],"contentSha256":"fc475c7a0bd64577fe1edbbbd741839b06ae3234a3c193adece47683b26e96f3"},{"id":"chipswiki-31578-r92969","title":"Template:Packages/intel/rpga-988a — revision 92969","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Frpga-988a&oldid=92969","publisher":"ChipsWiki / WikiChip contributors","published":"2016-12-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Frpga-988a"],"contentSha256":"e8d6d9da975af29ad9350349cb1389a7eefeaa0559fd9057d9d1fc81d7789cc9"},{"id":"chipswiki-8026-r25608","title":"Celeron P4500 — ChipsWiki, revision 25608","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fp4500&oldid=25608","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/p4500"],"contentSha256":"69a6b3074e1d954a7007d74e9c01b8cc985f3c2e4596e2ddee2b5478869f1e49"},{"id":"chipswiki-8027-r25610","title":"Celeron N3350 — ChipsWiki, revision 25610","url":"https://chipswiki.org/index.php?title=Intel%2Fceleron%2Fn3350&oldid=25610","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/celeron/n3350"],"contentSha256":"7b07867a4d0161a9625c9617a42265780271b47086f198aaf57195285efbb78a"},{"id":"chipswiki-603-r1408","title":"Core i3-330M — ChipsWiki, revision 1408","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-330m&oldid=1408","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-330m"],"contentSha256":"4178e8f002ac68c7b5fcf0b2228d0e3af618923949e747838b3d381f28537d6b"},{"id":"chipswiki-3959-r12646","title":"Core i3-6006U — ChipsWiki, revision 12646","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-6006u&oldid=12646","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-6006u"],"contentSha256":"8c7e216206e546de87aa40f842090ee3d81db1d7f702c5c0207eea345f49a17c"},{"id":"chipswiki-6421-r20022","title":"Core i3-7100H — ChipsWiki, revision 20022","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100h&oldid=20022","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-7100h"],"contentSha256":"c46298c28f46734751b702d1cbceb2a1739fcf96a933534581b0f87011bf514d"},{"id":"chipswiki-6422-r20023","title":"Core i3-7100E — ChipsWiki, revision 20023","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-7100e&oldid=20023","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-1528"],"contentSha256":"2da6f3fdb11deb7225df6f09d98f09b9da7ebfe738a1a3781b1468be758c6526"},{"id":"chipswiki-5463-r17839","title":"Core i3-8120T — ChipsWiki, revision 17839","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8120t&oldid=17839","publisher":"ChipsWiki / WikiChip contributors","published":"2018-06-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i3/i3-8120t"],"contentSha256":"c8b91a2c39074f5cc1556c67dfed51dba032c8109412d63b57e58014cd514d0e"},{"id":"chipswiki-5569-r18090","title":"Core i3-8320 — ChipsWiki, revision 18090","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i3%2Fi3-8320&oldid=18090","publisher":"ChipsWiki / WikiChip contributors","published":"2018-06-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-2660m"],"contentSha256":"7481c11bb792700fbd8102fb6795b5fe08d0eeb13928509d529ca9c7d175c7e4"},{"id":"chipswiki-7889-r25393","title":"Core i7-2655QM — ChipsWiki, revision 25393","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-2655qm&oldid=25393","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-7700hq"],"contentSha256":"ab36102b7dc0140c38caa397f64ba163ff58bae28f260d815e15db2fdac722b6"},{"id":"chipswiki-3691-r11027","title":"Core i7-8510Y — ChipsWiki, revision 11027","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-8510y&oldid=11027","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-06","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-8510y"],"contentSha256":"315d76dfe418e68bd0d0161f18f77cfaeb1697dc0c8ceb9e3bc349ae73be7af7"},{"id":"chipswiki-3972-r12659","title":"Core i7-6820HQ — ChipsWiki, revision 12659","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6820hq&oldid=12659","publisher":"ChipsWiki / WikiChip contributors","published":"2019-01-16","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-6700hq"],"contentSha256":"019e3d0d9850bec00949cc2be630ba6d31c0c1406716f4cdb423508fbb7903c9"},{"id":"chipswiki-4728-r15166","title":"Core i7-7660U — ChipsWiki, revision 15166","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7660u&oldid=15166","publisher":"ChipsWiki / WikiChip contributors","published":"2018-10-04","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-7660u"],"contentSha256":"ecf5d2f67193198d40c2d70ec4e9998dc96c9290ab3a280deb1b140621af5bc6"},{"id":"chipswiki-6414-r20013","title":"Core i7-7820HQ — ChipsWiki, revision 20013","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7820hq&oldid=20013","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-7820hq"],"contentSha256":"2082c81cc9a7c2559362e186dafa5028a9aaa583d4f8a1c83916d61daee1e7e8"},{"id":"chipswiki-7830-r25318","title":"Core i7-7560U — ChipsWiki, revision 25318","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-7560u&oldid=25318","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/core_i7/i7-7560u"],"contentSha256":"a942a1172bdf01acaabfabe6ffbc617d418973166e6d73f80d2733bd15a6beca"},{"id":"chipswiki-7834-r25325","title":"Core i7-6870HQ — ChipsWiki, revision 25325","url":"https://chipswiki.org/index.php?title=Intel%2Fcore%20i7%2Fi7-6870hq&oldid=25325","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/957"],"contentSha256":"e509658c149a50904e47b4c8a660959a32cc23c0a5a7fc15c1b400df5a7621e1"},{"id":"chipswiki-7798-r25236","title":"Pentium 917 — ChipsWiki, revision 25236","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20(2009)%2F917&oldid=25236","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/pentium_(2009)/917"],"contentSha256":"1927575c290c36c63369fcb7ed67e4406432c814a0d28c169f2d9b00aca90c1c"},{"id":"chipswiki-7801-r25240","title":"Mobile Pentium II 400 — ChipsWiki, revision 25240","url":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F400&oldid=25240","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/mobile_pentium_ii/400"],"contentSha256":"6f3a1c4e1955f7131cb8f037d060b87012cc799d86157ccdde8701b7dda5e2c3"},{"id":"chipswiki-7802-r25241","title":"Mobile Pentium II 366 — ChipsWiki, revision 25241","url":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F366&oldid=25241","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/mobile_pentium_ii/366"],"contentSha256":"1674a870c99e6c0991005dfab6655d1dbe83e06d8272c3e24c2b9208e28c009f"},{"id":"chipswiki-7803-r25242","title":"Mobile Pentium II 333 — ChipsWiki, revision 25242","url":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F333&oldid=25242","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/mobile_pentium_ii/333"],"contentSha256":"9466e23f9438c88d9e26c15860dfe12ed5035db4e6d3123508053781d177283c"},{"id":"chipswiki-7807-r25246","title":"Mobile Pentium II 266 — ChipsWiki, revision 25246","url":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F266&oldid=25246","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/mobile_pentium_ii/266"],"contentSha256":"9511bb0f2081f01305062ebba7270e1ced87a54662a5692ad7712f93e98cee24"},{"id":"chipswiki-7808-r25247","title":"Mobile Pentium II 233 — ChipsWiki, revision 25247","url":"https://chipswiki.org/index.php?title=Intel%2Fmobile%20pentium%20ii%2F233&oldid=25247","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/mobile_pentium_ii/233"],"contentSha256":"b62c9c1fb6ad6f7db3e93eaaa70c220a8da6befc75b86bc25a323d91eca93a7d"},{"id":"chipswiki-8764-r27226","title":"Tukwila — ChipsWiki, revision 27226","url":"https://chipswiki.org/index.php?title=Intel%2Fmicroarchitectures%2Ftukwila&oldid=27226","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-30","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/microarchitectures/tukwila"],"contentSha256":"f28a4785c0b39bf401b303550acc306e6c29e6165890dccbb6f1e389e8867ae1"},{"id":"chipswiki-22-r96949","title":"Pentium Silver J5005 — ChipsWiki, revision 96949","url":"https://chipswiki.org/index.php?title=Intel%2Fpentium%20silver%2Fj5005&oldid=96949","publisher":"ChipsWiki / WikiChip contributors","published":"2022-11-17","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1523n"],"contentSha256":"8063003727974d561cc36bd61b0b24262ff366d1b8503838d84690be96da099b"},{"id":"chipswiki-3727-r11426","title":"Xeon D-1518 — ChipsWiki, revision 11426","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1518&oldid=11426","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1518"],"contentSha256":"9755698114f252a1964508474fcd39c2ce374e42b95a6d164ca78a56b49d4701"},{"id":"chipswiki-3728-r11428","title":"Xeon D-1529 — ChipsWiki, revision 11428","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1529&oldid=11428","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1529"],"contentSha256":"1dd0d2c8b5c8698662a3f962c5ff89ba59e43f79060eb5f10c75986f7a56dd12"},{"id":"chipswiki-3729-r11431","title":"Xeon D-1567 — ChipsWiki, revision 11431","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1567&oldid=11431","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1567"],"contentSha256":"bf911dde2ebdafa143ef25391ef00f3c6116cf1b03bfcae1a84b11e1edb0f118"},{"id":"chipswiki-3730-r11433","title":"Xeon D-1520 — ChipsWiki, revision 11433","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1520&oldid=11433","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1520"],"contentSha256":"00aa67ce527013d3d8ea5330a65e4b57c1bc3d6c192bff7ea881bd19dfd269e4"},{"id":"chipswiki-3731-r11435","title":"Xeon D-1521 — ChipsWiki, revision 11435","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1521&oldid=11435","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1521"],"contentSha256":"38df791e2d44903ad3cfdc4af2a22ba46f256c0c99870d01f420fffb1e78b9fc"},{"id":"chipswiki-3736-r11445","title":"Xeon D-1559 — ChipsWiki, revision 11445","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1559&oldid=11445","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1559"],"contentSha256":"23ca131629955e27da712b25c4d7b1cac370bec751f508988d717cc37621f1a3"},{"id":"chipswiki-3738-r11447","title":"Xeon D-1577 — ChipsWiki, revision 11447","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1577&oldid=11447","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1577"],"contentSha256":"99c0886e34b302e287e25e518bff53be1ce038be2fc38a30855c5e6003213557"},{"id":"chipswiki-3740-r11449","title":"Xeon D-1528 — ChipsWiki, revision 11449","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1528&oldid=11449","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1528"],"contentSha256":"ce8d705197b95a5d42cca0dd56ffd29d858fc123038fb2cede6afda7c29bc113"},{"id":"chipswiki-3741-r11450","title":"Xeon D-1537 — ChipsWiki, revision 11450","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1537&oldid=11450","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1537"],"contentSha256":"70d91588aa1ec2884b673a0285e2fe612c6c379219cc499a295386dc359d0de6"},{"id":"chipswiki-3742-r11451","title":"Xeon D-1539 — ChipsWiki, revision 11451","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-1539&oldid=11451","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-1539"],"contentSha256":"079855dfe4abadddcc9a3a8ec83d5d6623323dd20e11c1a4388d4a9452dcb24f"},{"id":"chipswiki-31304-r92006","title":"Template:Packages/intel/fcbga-2518 — revision 92006","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fintel%2Ffcbga-2518&oldid=92006","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fintel%2Ffcbga-2518"],"contentSha256":"13ba5e401091e4c702e84b8273b4abd2daa8a9dc8d883bc0bb7d7b70727e6d2c"},{"id":"chipswiki-7148-r22565","title":"Xeon D-2177NT — ChipsWiki, revision 22565","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2177nt&oldid=22565","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-2177nt"],"contentSha256":"53e755623f4af762cc798480ad13bb2b36f96e47bda0dd8ad123434007dd3ee2"},{"id":"chipswiki-7149-r22568","title":"Xeon D-2166NT — ChipsWiki, revision 22568","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2166nt&oldid=22568","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-2166nt"],"contentSha256":"4ad7af8db87d6156e88b54a9070d48507b88d9a34486bdd796fd6588d7103760"},{"id":"chipswiki-7151-r22574","title":"Xeon D-2145NT — ChipsWiki, revision 22574","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2145nt&oldid=22574","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-2145nt"],"contentSha256":"7c89bdab99f27fcaac66417ccb477c6c4b65ff1d27ff0add3a62a5e0b77fe3f8"},{"id":"chipswiki-7152-r22577","title":"Xeon D-2183IT — ChipsWiki, revision 22577","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2183it&oldid=22577","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-2183it"],"contentSha256":"985f323a5f3f945ec0faff8d4b9237be9cfa7db4da01c65460cebb6f345c4e15"},{"id":"chipswiki-7153-r22580","title":"Xeon D-2173IT — ChipsWiki, revision 22580","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2173it&oldid=22580","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-2173it"],"contentSha256":"1d62a0018b905f4461d416e3d908ca8ca5ddd4acf6227dee819c175f9e0e5634"},{"id":"chipswiki-7154-r22583","title":"Xeon D-2163IT — ChipsWiki, revision 22583","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2163it&oldid=22583","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-2163it"],"contentSha256":"0fc55b0c0d148bd94bc5012906d79d502724e82c6a008d4c712c0ce7011945f8"},{"id":"chipswiki-7157-r22592","title":"Xeon D-2123IT — ChipsWiki, revision 22592","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20d%2Fd-2123it&oldid=22592","publisher":"ChipsWiki / WikiChip contributors","published":"2018-02-08","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_d/d-2123it"],"contentSha256":"b7bf7392f6837c2c4e8a99d102d4d5d8334f9b4ffa6585c69f717df05ecbcb75"},{"id":"chipswiki-1242-r3963","title":"Xeon E-2236 — ChipsWiki, revision 3963","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2236&oldid=3963","publisher":"ChipsWiki / WikiChip contributors","published":"2020-03-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2236"],"contentSha256":"d93e92313c149b21b1579a1548d7152ed8551ac101ab557d64a12ec2befb7ac5"},{"id":"chipswiki-2403-r8029","title":"Xeon E-2276M — ChipsWiki, revision 8029","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2276m&oldid=8029","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2276m"],"contentSha256":"3ca860b4050d8bb97e77f55498c454d949f8443c11ee0c59ed4a20c87eeaf9bd"},{"id":"chipswiki-2406-r8038","title":"Xeon E-2278G — ChipsWiki, revision 8038","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2278g&oldid=8038","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2278g"],"contentSha256":"84fb6c64a2aec42c90a3ec2241df2b541bc2982d78da00ccbfa1187ae18df955"},{"id":"chipswiki-2408-r8042","title":"Xeon E-2274G — ChipsWiki, revision 8042","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2274g&oldid=8042","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2274g"],"contentSha256":"74931b60dd4b4c4cbcbf679aa40d4de8d6d19d801cf5fb315fdc7627bf52158f"},{"id":"chipswiki-2411-r8052","title":"Xeon E-2226G — ChipsWiki, revision 8052","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2226g&oldid=8052","publisher":"ChipsWiki / WikiChip contributors","published":"2019-06-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2226g"],"contentSha256":"64b348d7c16973943fb9812f71d58779f02f1a4bf4a501c79259957e19e91005"},{"id":"chipswiki-3027-r10094","title":"Xeon E-2186G — ChipsWiki, revision 10094","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e%2Fe-2186g&oldid=10094","publisher":"ChipsWiki / WikiChip contributors","published":"2019-04-25","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e/e-2186g"],"contentSha256":"38f848f2a5fa13a21eec958ca3f9cefa0ed0e88b329f2faec9fd8ce510200430"},{"id":"chipswiki-6436-r20134","title":"Xeon E3-1280 v5 — ChipsWiki, revision 20134","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1280%20v5&oldid=20134","publisher":"ChipsWiki / WikiChip contributors","published":"2018-04-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1280_v5"],"contentSha256":"93272b8880109fbfa1915490265f655ec1b957e5c3158f30dc2f501292934735"},{"id":"chipswiki-7762-r25150","title":"Xeon E3-1284L v3 — ChipsWiki, revision 25150","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1284l%20v3&oldid=25150","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1284l_v3"],"contentSha256":"5a85385bcbc9d83af74f52ce1ac88c11e722520b6c9f00141da1933369829e0d"},{"id":"chipswiki-7765-r25155","title":"Xeon E3-1270 v6 — ChipsWiki, revision 25155","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1270%20v6&oldid=25155","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1270_v6"],"contentSha256":"f7b8a7c591b3801fed2b3ffd15f7264dae64fe9fbf8ffc5d51f1c572c19d6b15"},{"id":"chipswiki-7769-r25162","title":"Xeon E3-1240 v6 — ChipsWiki, revision 25162","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1240%20v6&oldid=25162","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_e3/e3-1240_v6"],"contentSha256":"9a12d06c5ecaab33c78372c89d88785b7fdb3aed6f86d3580c61e42b77e011b5"},{"id":"chipswiki-7770-r25164","title":"Xeon E3-1235L v5 — ChipsWiki, revision 25164","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20e3%2Fe3-1235l%20v5&oldid=25164","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6222v"],"contentSha256":"6250746104923a7f1e000a1b1ee3196d7da9c28fd231be21d6c29eae29bd6317"},{"id":"chipswiki-1493-r4945","title":"Xeon Gold 6154 — ChipsWiki, revision 4945","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6154&oldid=4945","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6148"],"contentSha256":"754ba91fb973bc88cd5cccf33d98723807da2bbb570246aaf36fda79a93bbea9"},{"id":"chipswiki-1496-r4948","title":"Xeon Gold 6150 — ChipsWiki, revision 4948","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6150&oldid=4948","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6140"],"contentSha256":"130cb4ac8812286c3afc836fd57b5f1eca3d1993aec85654e826b7738ff22b4a"},{"id":"chipswiki-1506-r4958","title":"Xeon Gold 6138 — ChipsWiki, revision 4958","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138&oldid=4958","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6138"],"contentSha256":"75fb5f1b38cb3af86a60dbb0e28fb832b0bd44a3d76d0206100d16f91cb4b5e3"},{"id":"chipswiki-1507-r4959","title":"Xeon Gold 6138F — ChipsWiki, revision 4959","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6138f&oldid=4959","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6138f"],"contentSha256":"e6c03fa9b5d27b6feaac497903bbce0bb7368fae2dc22bac5152beeac91abdfa"},{"id":"chipswiki-1516-r4968","title":"Xeon Gold 6126 — ChipsWiki, revision 4968","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6126&oldid=4968","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6126"],"contentSha256":"12b0f24fe9415626be3b512ab0843721b48303418e69224b921e655c8a38de73"},{"id":"chipswiki-1518-r4970","title":"Xeon Gold 5220T — ChipsWiki, revision 4970","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220t&oldid=4970","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5220t"],"contentSha256":"e3fbc54e0a61744379ba931b4251803fdab84f14b96dff86dbd2f2022039d722"},{"id":"chipswiki-1519-r4971","title":"Xeon Gold 5220S — ChipsWiki, revision 4971","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220s&oldid=4971","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5220s"],"contentSha256":"00e8e94a600cd900a13a24bdf60d507ea50b2e0495b4bca301dd258cf8d17d80"},{"id":"chipswiki-1520-r4972","title":"Xeon Gold 5220 — ChipsWiki, revision 4972","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5220&oldid=4972","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/5220"],"contentSha256":"02cce4122989f9d68762d690973d05eaa9cf5b8f2e9b9bb8d82044c267dda5ed"},{"id":"chipswiki-1522-r4974","title":"Xeon Gold 5218N — ChipsWiki, revision 4974","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F5218n&oldid=4974","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8173m"],"contentSha256":"79400a0b5fb69cbe8092c469a14c25e189d469409a858877432866e575b3091f"},{"id":"chipswiki-589-r1362","title":"Xeon Gold 6240M — ChipsWiki, revision 1362","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240m&oldid=1362","publisher":"ChipsWiki / WikiChip contributors","published":"2021-10-10","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6240m"],"contentSha256":"c140a0f8658a4384cd77bad851220d24ab5787520a1fa37ab8ba74e26fbd6045"},{"id":"chipswiki-615-r1446","title":"Xeon Platinum 8124 — ChipsWiki, revision 1446","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20platinum%2F8124&oldid=1446","publisher":"ChipsWiki / WikiChip contributors","published":"2021-09-10","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_platinum/8124m"],"contentSha256":"5c0dfec6e17c1245d32dc1c8e4774b4dbc2f62cde90114c20b4abb13b8fe4401"},{"id":"chipswiki-1218-r3808","title":"Xeon Gold 6240 — ChipsWiki, revision 3808","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240&oldid=3808","publisher":"ChipsWiki / WikiChip contributors","published":"2020-04-03","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6262v"],"contentSha256":"62b5456922d9a11d4eb87b95bc76e93c59599ebafcf2a58e588d694fbab4b80c"},{"id":"chipswiki-1477-r4925","title":"Xeon Gold 6252N — ChipsWiki, revision 4925","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6252n&oldid=4925","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6248"],"contentSha256":"66e6c9b8a4ae9d8fd9c251f236fb864357756947d10cd1049123cca9cc76cfc5"},{"id":"chipswiki-1480-r4928","title":"Xeon Gold 6246 — ChipsWiki, revision 4928","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6246&oldid=4928","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6242"],"contentSha256":"da34d69fa8084d37c543a58969a3e903c8bd960c13d8d50b90454b0148e36200"},{"id":"chipswiki-1484-r4933","title":"Xeon Gold 6240L — ChipsWiki, revision 4933","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6240l&oldid=4933","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6240l"],"contentSha256":"9b6579327d5a4321d18c5734e47f849953ee1e9508371d3df831abedf7e51b7c"},{"id":"chipswiki-1485-r4935","title":"Xeon Gold 6238M — ChipsWiki, revision 4935","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238m&oldid=4935","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6238m"],"contentSha256":"f3ea8831f94e8c2cb474297f331698b472351290f377ff726dee410c13474b43"},{"id":"chipswiki-1486-r4936","title":"Xeon Gold 6238T — ChipsWiki, revision 4936","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238t&oldid=4936","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6238t"],"contentSha256":"894d527d8f8d8f4af66d73f63905e342973f1dd96d80f4eda15210d45fcb67a6"},{"id":"chipswiki-1487-r4937","title":"Xeon Gold 6238L — ChipsWiki, revision 4937","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6238l&oldid=4937","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_gold/6238l"],"contentSha256":"1c98baaabdf030d31f751a19939ee0920bab5f4c8092b173dd7fd35ac332d94b"},{"id":"chipswiki-1488-r4939","title":"Xeon Gold 6234 — ChipsWiki, revision 4939","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20gold%2F6234&oldid=4939","publisher":"ChipsWiki / WikiChip contributors","published":"2019-12-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-2135"],"contentSha256":"74839be2671146709cad027c7ca34ff3ae894ca9d12513874515ad52a40ce4a2"},{"id":"chipswiki-2531-r8691","title":"Xeon W-2133 — ChipsWiki, revision 8691","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2133&oldid=8691","publisher":"ChipsWiki / WikiChip contributors","published":"2019-05-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-3223"],"contentSha256":"3f03f608e914243368998042b16fe3ce30255ee61d14732909a30cd5eff9882b"},{"id":"chipswiki-1705-r5938","title":"Xeon W-3245M — ChipsWiki, revision 5938","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3245m&oldid=5938","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-3245m"],"contentSha256":"1689f44426b15e1c61ec17d160ed0a5f925a95d21a7650d9cca4d5f58fb7f35c"},{"id":"chipswiki-1709-r5944","title":"Xeon W-3275M — ChipsWiki, revision 5944","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-3275m&oldid=5944","publisher":"ChipsWiki / WikiChip contributors","published":"2019-10-07","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-2175"],"contentSha256":"bb7695944951472ed6ff0f236a892b4c5b185d3224717075ead1f9d4233896d5"},{"id":"chipswiki-4516-r14678","title":"Xeon W-2170B — ChipsWiki, revision 14678","url":"https://chipswiki.org/index.php?title=Intel%2Fxeon%20w%2Fw-2170b&oldid=14678","publisher":"ChipsWiki / WikiChip contributors","published":"2018-10-24","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intel/xeon_w/w-2170b"],"contentSha256":"db8b3484d779f39ed319ee302ffbd3bc2c407cf293e2ec64dd204d2b886950a9"},{"id":"chipswiki-7687-r24982","title":"FastMATH-LP — ChipsWiki, revision 24982","url":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-lp&oldid=24982","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Intrinsity/fastmath/fastmath-lp"],"contentSha256":"44f9c0e418bb13b0132b5fa00768641e6f7bc7a9d7e1e423e3204e4afc7f2d31"},{"id":"chipswiki-7690-r24985","title":"FastMATH 1.5 GHz — ChipsWiki, revision 24985","url":"https://chipswiki.org/index.php?title=Intrinsity%2Ffastmath%2Ffastmath-1.5&oldid=24985","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Kirin_990_4G"],"contentSha256":"e69141f5835668f32a8d9e388ca34e5eb9da523a3924a2fc5c3a08d5195147fb"},{"id":"chipswiki-7677-r24972","title":"Godson-2H — ChipsWiki, revision 24972","url":"https://chipswiki.org/index.php?title=Loongson%2Fgodson%202%2F2h&oldid=24972","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/7904"],"contentSha256":"e38411c367131d60ed3d493d1e870ec51f10877424cc7dce6448adbbc1284d52"},{"id":"chipswiki-983-r2788","title":"Exynos 9110 — ChipsWiki, revision 2788","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9110&oldid=2788","publisher":"ChipsWiki / WikiChip contributors","published":"2020-08-14","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos_auto/v9"],"contentSha256":"9560cd96618453472d982944cceccb270d1177db6b8333af9ce6642c1a481709"},{"id":"chipswiki-1182-r3689","title":"Exynos 9825 — ChipsWiki, revision 3689","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F9825&oldid=3689","publisher":"ChipsWiki / WikiChip contributors","published":"2020-04-26","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/9825"],"contentSha256":"d52fe5b632c4f525245998a349076c299ae99eb622ba075e650ae73e8bfc7ddf"},{"id":"chipswiki-1289-r4300","title":"Exynos 7420 — ChipsWiki, revision 4300","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7420&oldid=4300","publisher":"ChipsWiki / WikiChip contributors","published":"2020-02-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/7420"],"contentSha256":"8e69602f7a62e2d25b50f53a8b296658c0ecc8a4d40e730972b55a43a92636b2"},{"id":"chipswiki-3825-r12082","title":"Exynos M2 — ChipsWiki, revision 12082","url":"https://chipswiki.org/index.php?title=Samsung%2Fmicroarchitectures%2Fm2&oldid=12082","publisher":"ChipsWiki / WikiChip contributors","published":"2019-02-21","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/microarchitectures/m2"],"contentSha256":"2459c4d0134e4394161d830a820b6110ac969daaf416a0f8093a73d12f195f59"},{"id":"chipswiki-5172-r16835","title":"Exynos 4412 — ChipsWiki, revision 16835","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4412&oldid=16835","publisher":"ChipsWiki / WikiChip contributors","published":"2018-08-02","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/4412"],"contentSha256":"a9e007f78b31d4b25a6459abeb0fd58d4f29fd6e167006b64d49c998d64a7ca6"},{"id":"chipswiki-6841-r21323","title":"Exynos 7872 — ChipsWiki, revision 21323","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7872&oldid=21323","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/7872"],"contentSha256":"bbf5caafc829717a9debdf25905ecc5160473cc6cd94fa8e4a8f1d15b7b0800f"},{"id":"chipswiki-6844-r21329","title":"Exynos 7570 — ChipsWiki, revision 21329","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F7570&oldid=21329","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/7570"],"contentSha256":"066c8169c591c304055a868c52778fce3a2b0bbc7d3865483f3474371a7cc534"},{"id":"chipswiki-6848-r21340","title":"Exynos 5410 — ChipsWiki, revision 21340","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5410&oldid=21340","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/5410"],"contentSha256":"c0de0402fb572631b1a996dd8133a711ff841ce6cb6ac4b46e78b4e29ab33091"},{"id":"chipswiki-6849-r21342","title":"Exynos 5420 — ChipsWiki, revision 21342","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5420&oldid=21342","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/5420"],"contentSha256":"539faf679304f3b2a3ca3442343fe4451622301dac70684f5e5e56b78f165734"},{"id":"chipswiki-6850-r21344","title":"Exynos 5422 — ChipsWiki, revision 21344","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F5422&oldid=21344","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-29","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/5422"],"contentSha256":"3b33455beb3ea39d57ed8ceb40e4767a3b47583b8fe058d810ea45c9d1bd9038"},{"id":"chipswiki-6853-r21361","title":"Exynos 4212 — ChipsWiki, revision 21361","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4212&oldid=21361","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/4212"],"contentSha256":"c488b1998dd80692a394eb2f5641f7462dc8f8b2e4025846547603088f452886"},{"id":"chipswiki-6854-r21369","title":"Exynos 4210 — ChipsWiki, revision 21369","url":"https://chipswiki.org/index.php?title=Samsung%2Fexynos%2F4210&oldid=21369","publisher":"ChipsWiki / WikiChip contributors","published":"2018-03-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Samsung/exynos/4210"],"contentSha256":"df1ba98cd91eeceea26ec1aacd5bab7fbc0d761be340534f87d9b747bb9e7115"},{"id":"chipswiki-31351-r92104","title":"Template:Packages/sun microsystems/bga-521 — revision 92104","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fsun%20microsystems%2Fbga-521&oldid=92104","publisher":"ChipsWiki / WikiChip contributors","published":"2017-11-28","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fsun_microsystems%2Fbga-521"],"contentSha256":"90b140a8ce1fc768c9105fb15bd7efe559a53695d45d24301fe232e5f04c3adb"},{"id":"chipswiki-7638-r24895","title":"UltraSPARC-I 182MHz — ChipsWiki, revision 24895","url":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-182&oldid=24895","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Sun_microsystems/ultrasparc/stp1030bga-182"],"contentSha256":"35204f2fd12b6349f5d73ef804bd5e158cfaa51d5992ad4eaad04497d4112ee7"},{"id":"chipswiki-7639-r24896","title":"UltraSPARC-I 167MHz — ChipsWiki, revision 24896","url":"https://chipswiki.org/index.php?title=Sun%20microsystems%2Fultrasparc%2Fstp1030bga-167&oldid=24896","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fcdip-28"],"contentSha256":"ddbb42ce38cd1c968b2e16e22c62300df24339164be4579f683803bc4332d481"},{"id":"chipswiki-8669-r26879","title":"TMS1098 — ChipsWiki, revision 26879","url":"https://chipswiki.org/index.php?title=Ti%2Ftms1000%2Ftms1098&oldid=26879","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Ti/tms1000/tms1098"],"contentSha256":"c778e1149f809e36a978bcbff2a64f12d3aaa7fe7adc4c7b708718b7c55bf14a"},{"id":"chipswiki-6266-r19330","title":"SpiNNaker - APT — ChipsWiki, revision 19330","url":"https://chipswiki.org/index.php?title=University%20of%20manchester%2Fspinnaker&oldid=19330","publisher":"ChipsWiki / WikiChip contributors","published":"2018-05-19","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Via_technologies/microarchitectures/isaiah"],"contentSha256":"9fa13242f4bf646fc8b1b448a52075ececd3e713c1071196a2b87f0bd74c2851"},{"id":"chipswiki-7380-r23866","title":"Ezra — ChipsWiki, revision 23866","url":"https://chipswiki.org/index.php?title=Via%20technologies%2Fmicroarchitectures%2Fezra&oldid=23866","publisher":"ChipsWiki / WikiChip contributors","published":"2018-01-15","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Via_technologies/microarchitectures/ezra"],"contentSha256":"9a883762def8fc103253e5571f8a7d388130839faa1aeea3ed3a508d8da59a8f"},{"id":"chipswiki-31401-r92231","title":"Template:Packages/vti/tqfp-144 — revision 92231","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Ftqfp-144&oldid=92231","publisher":"ChipsWiki / WikiChip contributors","published":"2017-09-10","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Template%3APackages%2Fvti%2Ftqfp-144"],"contentSha256":"d2bace9f0c81a2f47cae4a6f5b4ce14a23a41da6d18d28b52ac89fa3fc853f9e"},{"id":"chipswiki-7623-r24878","title":"VY86C710A2 — ChipsWiki, revision 24878","url":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a2&oldid=24878","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Vti/vl86cx/vy86c710a2"],"contentSha256":"980ad36b61f3414bc8aed30fa835348dd1d48ec1edd1e688259186c214c67cd1"},{"id":"chipswiki-7624-r24879","title":"VY86C710A — ChipsWiki, revision 24879","url":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvy86c710a&oldid=24879","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Vti/vl86cx/vy86c060"],"contentSha256":"8b1aee1ad732db0944a8c5bbaff13c2d28f83cfaf79d60766f0f326fc90eaecd"},{"id":"chipswiki-7635-r24891","title":"VC2588 — ChipsWiki, revision 24891","url":"https://chipswiki.org/index.php?title=Vti%2Fvl86cx%2Fvc2588&oldid=24891","publisher":"ChipsWiki / WikiChip contributors","published":"2017-12-13","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Vti/vl86cx/vc2588"],"contentSha256":"cad95ef759c0cb62d255cd63bfef0256885b830e1b3fff1048fe8fa69112b487"},{"id":"chipswiki-31439-r92361","title":"Template:Packages/vti/plcc-82 — revision 92361","url":"https://chipswiki.org/index.php?title=Template%3APackages%2Fvti%2Fplcc-82&oldid=92361","publisher":"ChipsWiki / WikiChip contributors","published":"2017-07-01","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. 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Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Xiaomi/surge/s2"],"contentSha256":"6a2685e6c70381ea7f9a3f97c802487458bdf35f0b2468a27cdeda97558db4fb"},{"id":"chipswiki-5649-r18547","title":"KaiXian KX-U5580M — ChipsWiki, revision 18547","url":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-u5580m&oldid=18547","publisher":"ChipsWiki / WikiChip contributors","published":"2018-05-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Zhaoxin/kaixian/kx-u5580m"],"contentSha256":"fb970d40668dd16f74d9d491d3e070de2c0ab27fc8e94dbc39c078464515d1fd"},{"id":"chipswiki-5651-r18549","title":"KaiXian KX-5640 — ChipsWiki, revision 18549","url":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5640&oldid=18549","publisher":"ChipsWiki / WikiChip contributors","published":"2018-05-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Zhaoxin/kaixian/kx-5640"],"contentSha256":"9f8f04024746b36e9aeac932924fdc8b6587b4ed4acad5d992359e85fdb78808"},{"id":"chipswiki-5652-r18550","title":"KaiXian KX-5540 — ChipsWiki, revision 18550","url":"https://chipswiki.org/index.php?title=Zhaoxin%2Fkaixian%2Fkx-5540&oldid=18550","publisher":"ChipsWiki / WikiChip contributors","published":"2018-05-27","accessed":"2026-09-11","evidenceClass":"third-party-report","type":"structured-reference","license":"CC BY-NC-SA 4.0","licenseUrl":"https://chipswiki.org/ChipsWiki:About","attribution":"WikiChip and ChipsWiki contributors. Scalar infobox parameters extracted and normalized by VLSI Museum; narrative text is not reproduced.","derivedFrom":["https://en.wikichip.org/wiki/Zhaoxin/kaixian/kx-5540"],"contentSha256":"a82f6bde0306de92344c42936274365c7b6f9fdd62c784b5df0424e8d456990b"}]}